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Transcript
IEEE 1149.1 Test Access Port (JTAG)
1 TEST-LOGIC-RESET
0
0
RUN-TEST/IDLE
1
SELECT DR-SCAN
SELECT IR-SCAN
1
1
CAPTURE-DR
1
CAPTURE-IR
0
0
0
SHIFT-DR
1
EXIT1-DR
1
EXIT1-IR
1
1
0
0
0
PAUSE-DR
0
PAUSE-IR
1
1
EXIT2-DR
EXIT2-IR
0
1
1
UPDATE-DR
1
0
SHIFT-IR
1
0
1
0
0
UPDATE-IR
0
1
0
Figure 27-4. TAP Controller State Machine Flow
27.4.3
JTAG Instructions
Table 27-5 describes public and private instructions.
Table 27-5. JTAG Instructions
Instruction
IR[3:0]
Instruction Summary
EXTEST
0000
Selects boundary scan register while applying fixed values to output pins and
asserting functional reset
IDCODE
0001
Selects IDCODE register for shift
SAMPLE/PRELOAD
0010
Selects boundary scan register for shifting, sampling, and preloading without
disturbing functional operation
Freescale Semiconductor
27-7