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the I/O modules, like fast control loops is also directed to the FPGA. Tasks that involve input from
the user or presenting data to the user is not that time critical and is thereby natural to implement
in the embedded computer. Tasks involving signal processing before presentation to the user could
be implemented on the embedded computer or the FPGA. Where it is implemented depends on
demands on speed, amount of data, complexity of the algorithm and the integration with the rest of
the program. It is also possible to split it and do some processing in the FPGA and the rest in the
embedded computer.
4.2 Communication between the different parts
Everywhere in the programs, both in the embedded computer and the FPGA there is a need to send
and receive information from other parts of the program. As expected there is more than one way
to do this and the ones used in this project will be explained here.
4.2.1 Variables
Sometimes a control or an indicator on the front panel is needed in more than one place in the
program. This is achieved with a so called local variable to the control or indicator. Local
variables can only be used in the same VI and in this project they are only used in the embedded
computer. Related to the local variable is the global variable. Instead of being located on the front
panel of the program it is placed on the front panel of a separate VI. This makes the global
variable accessible from more than one VI. If more than one global variable is needed, more
variables can be added to the separate VI with the first global variable. The structure of the FPGA
program makes global variables very useful to create variables that are used within the FPGA. In
the program for the embedded computer global variables are only used for communication
between loops that run in parallel.
4.2.2 FIFO-queues
FIFO-Queues (First In First Out Queues) are essential in both the program for the embedded
computer and the transfer of large amounts of data from the FPGA program to the program in the
embedded computer or vice versa. A queue is a data structure that allows data to be produced and
consumed at different times but still not lose the order of the data. A FIFO-queue dequeues the
data in the same order as they are enqueued.
4.2.3 Interrupts
The program in the FPGA can generate an interrupt to the CPU in the embedded computer. An
interrupt is meant to interrupt the normal execution of the program in the embedded computer and
run a special part of the code called the interrupt routine. The interrupt routine is then supposed to
take care of the reason for the generation of the interrupt. It is possible to generate up 32 different
interrupts.
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