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5.23. State Machine 5.22.4 Model parameters Name Description Type Default Limits sr_delay Delay from s or r input change real 1nS 1e−12 − ∞ enable_delay Delay from clk real 1nS 1e−12 − ∞ set_delay Delay from set real 1nS 1e−12 − ∞ reset_delay Delay from reset real 1nS 1e−12 − ∞ ic Output initial state integer 0 0-2 rise_delay Rise delay real 1nS 1e−12 − ∞ fall_delay Fall delay real 1nS 1e−12 − ∞ sr_load S & r load values (F) real 1pF none enable_load Clk load value (F) real 1pF none set_load Set load value (F) real 1pF none reset_load Reset load value (F) real 1pF none family Logic family string UNIV none in_family Input logic family string UNIV none out_family Output logic family string UNIV none out_res Digital output resistance real 100 0−∞ out_res_pos Digital output res. pos. slope real out_res 0−∞ out_res_neg Digital output res. neg. slope real out_res 0−∞ min_sink Minimum sink current real -0.001 none max_source Maximum source current real 0.001 none sink_current Input sink current real 0 none source_current Input source current real 0 none 5.22.5 Device Operation This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high. 5.23 State Machine 5.23.1 Netlist entry Axxxx [ in_0 in_1 .. in_n ] clk reset [ out_0 out_1 .. out_n ] model_name 5.23.2 Connection details Name Description Flow Type Vector bounds in Input in d, vector none clk Clock in d n/a 163 SIMetrix Simulator Reference Manual
