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SYSTEM MANAGER
KS32C65100 RISC MICROPROCESSOR
ROM CONTROL REGISTER
The KS32C65100 ROM interface has one ROM bank for program memory and it provides configurable features
such as access timing, access size and page mode support, etc. The ROM Control Register (ROMCON) in SMR
supplies the control mode such as normal mode access, page mode access and wait cycles of each mode, for
the external ROM bank.
The initial address of ROMCON is 01001000h and it is the sum of the initial address of SYSCFG (01000000h)
and the ROM control register offset address (00001000h). The register address is re-configurable that
programmers can change the ROM control register by changing the contents of SYSCFG. The real address of
ROM control register is "SYSCFG address" + "Offset address" of the ROM control register.
Register
Offset Address
R/W
ROMCON
0x1000
R/W
Description
ROM control register
Reset Val.
0x02003002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ROMCON
Next Pointer
Base Pointer
Tacc
Tacp Pmc
[1:0] Bus Width (DW)
10 = 16 (half word)
Others = No use
(The ROM interface supports only 16 bits of external data bus width)
[8:7] Page Mode Configuration (Pmc)
00 = Normal ROM
01 = 4 data page
10 = 8 data page
11 = 16 data page
[10:9] Page Mode Access Cycles (Tacp)
00 = 5 cycles
01 = 2 cycles
10 = 3 cycles
11 = 4 cycles
[13:11] Access Cycles for ROM Bank (Tacc)
000 = Disable bank
100 = 5 cycles
001 = 2 cycles
101 = 6 cycles
010 = 3 cycles
110 = 7 cycles
011 = 4 cycles
111 = Not used
[22:14] Start Point of ROM Bank (Base Pointer)
Indicates ROM bank start address
[31:23] End Point + 1 of ROM (Next Pointer)
Indicates ROM bank end address + 1
(Next point value has to be bigger than base point value, if base point and next
point value are same, ROM bank is not valid anymore)
Figure 4-4. ROM Control Register (ROMCON)
4-6
DW