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IBM Confidential dcbst dcbst Data Cache Block Store (x’7C00 006C’) dcbst rA,rB Reserved 31 0 00 000 5 6 A 10 11 B 15 16 54 0 20 21 30 31 EA is the sum (rA|0) + (rB). The dcbst instruction executes as follows: • If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the data cache of this processor and has been modified, the writing of it to main memory is initiated. The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by EA. The processor treats this instruction as a load from the addressed byte with respect to address translation and memory protection. It is also treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. When HID2[LCE] = 1 and the byte addressed by EA is in the locked cache, the instruction is not forwarded to the L2 cache for sector invalidation/push, nor forwarded to the 60x bus for broadcast. Otherwise, the instruction will be forwarded to the L2 cache and to the 60x bus as described in Sections 3.4.2.4 and 9.2.1, in the PowerPC Microprocessor Family: The Programming Environments manual. Other registers altered: • None PowerPC Architecture Level Supervisor Level VEA Page 12-44 Version 1.2 Gekko Specific PowerPC Optional Form X IBM Confidential IBM Gekko RISC Microprocessor User’s Manual
