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Write Pipe
Data Queue
I-Cache
Write Pipe
Address
D-Cache
DMA Load
Address
BIU
Control
I-Cache
LD Addr
D-Cache
LD Addr
D-Cache
CST/ST Addr 0
D-Cache
CST/ST Addr 1
D-Cache
D-Cache
SNP Addr
Snoop
Control
Addr
Addr
Data
Data
Data
System Bus
Figure 8-1. Bus Interface Address Buffers
8.1 Bus Interface Overview
The bus interface prioritizes requests for bus operations from the instruction and data caches, and
performs bus operations in accordance with the protocol described in the PowerPC Microprocessor
Family: The Bus Interface for 32-Bit Microprocessors. It includes address register queues,
prioritization logic, and bus control unit. The bus interface latches snoop addresses for snooping in
the data cache and in the address register queues, and for reservations controlled by the Load Word
and Reserve Indexed (lwarx) and Store Word Conditional Indexed (stwcx.) instructions, and
maintains the touch load address for the cache. The interface allows one level of pipelining; that is,
with certain restrictions discussed later, there can be two outstanding transactions at any given time.
Accesses are prioritized with load operations preceding store operations.
Instructions are automatically fetched from the memory system into the instruction unit where they
are dispatched to the execution units at a peak rate of two instructions per clock. Conversely, load and
store instructions explicitly specify the movement of operands to and from the integer and
floating-point register files and the memory system.
When Gekko encounters an instruction or data access, it calculates the logical address (effective
address in the architecture specification) and uses the low-order address bits to check for a hit in the
on-chip, 32-Kbyte instruction and data caches.
During cache lookup, the instruction and data memory management units (MMUs) use the
higher-order address bits to calculate the virtual address from which they calculate the physical
address (real address in the architecture specification). The physical address bits are then compared
with the corresponding cache tag bits to determine if a cache hit occurred in the L1 instruction or data
cache. If the access misses in the corresponding cache, the physical address is used to access the L2
cache tags (if the L2 cache is enabled). If no match is found in the L2 cache tags, the physical address
is used to access system memory.
In addition to the loads, stores, and instruction fetches, Gekko performs hardware table search
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IBM Confidential
IBM Gekko RISC Microprocessor User’s Manual