Download 807_8300PUG

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Enable and assign priorities to interrupts of interest in the appropriate Group Priority Register
(GPR) in the ITCN module
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Enable interrupts and set IRQA and IRQB to level-sensitive or edge-sensitive in the Interrupt
Priority Register (IPR)
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Enable interrupts in the Status Register (SR)
As discussed in Section 6.3.3, the interrupt table has been rearranged. This, plus the availablity
of only five priority levels, means that the organization of the 56F8300/56F8100 devices’
Interrupt Priority Registers are different (but similar) to the 56F807 Group Priority Registers.
Please consult the 56F8300/56F8100 documentation for details. In the 56800E family, the
process for enabling interrupts is:
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Clear any outstanding peripheral interrupt status bits (peripheral-specific)
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Enable interrupts of interest in individual peripheral register sets
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Enable and assign priorities to interrupts of interest in the appropriate interrupt priority register
(IPRx) in the ITCN module. Note that a number of interrupt sources previously hardcoded on the
56F807 must be programmed into the 56F8300/56F8100 IPRx registers. These include IRQA,
IRQB and some of the EOnCE interrupts. A detailed mapping is shown in Table 6-13. See the
"Interrupt Vector Table Contents" section of the 56F8300/56F8100 Data Sheet for additional
information.
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Enable interrupts and set IRQA or IRQB to level-sensitive or edge-sensitive choices in the ICTL
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Select any two interrupt sources as fast interrupts and assign their ISR location using the ITCN Fast
Interrupt Match and Fast Interrupt Vector Address registers. Make sure these interrupts are
programmed as Level 2 interrupts.
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Enable interrupts in the Status Register (SR)
Fast interrupts are not available on the 56F80x devices, and represent a major enhancement in
56F8300/56F8100 devices.
56F807 to 56F8300/56F8100 Porting Guide, Rev. 0
Freescale Semiconductor
Preliminary
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