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Section 6 Issues Resulting from Chip Architectures
6.1 Higher Clock Speeds
The top peripheral clock speed on the 56F807 is 40MHz. On the 56F8300 devices, it is 60MHz.
Unless the system clock is slowed to 40MHz, the values of clock prescalars in serial interface
routines for SPI, SCI and CAN will have to be changed in order to preserve the frequency of
serial bit streams. This is handled automatically when utilizing Processor Expert. It will be
necessary to adjust timer prescalers and/or values for the on-board Quad Timers. PWM modulus
and counter values will also require adjustment.
6.2 Effects of Different Memory Sizes
On-chip memory sizes for each device are summarized in Table 6-1. Except for Data Flash,
56F8300 memory sizes meet or exceed 56F807 sizes in all cases. (The 56F8100 family of
devices have the same memory sizes, except there is no Program RAM or Data Flash.) Memory
sizes larger in the 56F83xx devices than in the 56F807 are shown in blue; memory sizes smaller
in the 56F83xx devices than in the 56F807 are shown in red. These larger memory sizes
significantly affected organization of the 56F8300 memory map. Subsequent sections will detail
the changes.
Table 6-1 Memory Configurations
On-Chip Memory
56F807
56F834x
56F835x
56F836x
Program Flash (PFLASH)
60K x 16
64K x 16
128K x 16
256K x 16
Data Flash (XFLASH)
8K x 16
4K x 16
4K x 16
16K x 16
Program RAM (PRAM)
2K x 16
2K x 16
2K x 16
2K x 16
Data RAM (XRAM)
4K x 16
2K x 32
4K x 32
8K x 32
Program Boot Flash
2K x 16
4K x 16
8K x 16
16K x 16
56F807 to 56F8300/56F8100 Porting Guide, Rev. 0
Freescale Semiconductor
Preliminary
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