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PROPRIETARY TO GENERAL ELECTRIC COMPANY
CT/e, CT ProSpeed AI/FI Series
ADVANCED THEORY OF OPERATION
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OVERVIEW (CONTINUED)
PCI Bus and NPR Bus
The NPR block is connected to the PCI bus.
Illustration 3-2 shows the main part of the address map of the NPR block.
The PCI side addresses (for Host Processor) are re-mapped into the local bus addresses as shown.
The data access is in 32 bit (word)/Little Endian only.
Illustration 3-2
NPR Address Map
PCI Bus Side
Local Bus Side
0000 0000
Global Memory 0
(128 MB)
0800 0000
(Allocated dynamically by a
base address set by Config
uration Register.)
0900 0000
Z#00 Internal Memory
(2 MB)
0920 0000
0930 0000
Communication Memory
(128 KB)
0932 0000
3-3
OPERATOR CONSOLE