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CD-XP120 CNS101 5.6V P_MUTE 5 4 3 2 1 M_GND D_GND CHANEL_SW INTR CLK STB 7 6 6.2V P_STB 2 1 DATA 5 4 3 D_GND 6 POW_SW CNS701 +B6 +B2 D405 D401 ZD401 CNP701 D404 Q412 Q413 Q411 CONSTANT VOLTAGE E CNS105 FM_ST P_MUTE FM_ST IR CD+B P_STB SYS_STOP P0W_KEY 38 UP_SW 39 DISC_SW BLKCK DATA CLK STB 37 SD 36 35 34 33 32 31 30 29 28 27 26 25 CE 23 CL 1 2 3 4 5 6 14 4 5 TO MAIN SECTION CNP105 6 CD+B X402 8 MHz 18 OSC2 15 P_CON MODE_CHK DEMO TAPE_DET GVSW ROTATE 48 LOAD- 46 MCLK 47 STAT 17 16 LOAD+ 44 3 CE DI 20 19 2 DI DO 21 IC403 XO IX0051SJ XI SYSTEM MMOD VSS MICROCOMPUTEROSC1 MRST MDATA DO 42 CD_STB 43 NRST 45 MLD 24 CL 22 40 LOAD_SW 41 PICK_IN 1 SD 7 8 +B5 9 10 VDD 13 7 8 9 10 11 12 TAPE_DET 1 5 MCLK TX DVSS1 CNS103 4 3 2 1 BCLK 6 LRCK 7 DVDD1 8 SRDATA 9 MDATA SENSE /FLOCK BLKCK SQCK SUBQ /TLOCK 21 TVR DMUTE STAT PMCK /RST 20 19 18 17 16 15 14 13 12 11 10 MLD 2 CD_R A_GND SSEL 80 22 TVD MSEL 79 23 PC PSEL 78 24 ECM CSEL 77 25 ECS RSEL 76 26 KICK OUTR 75 27 TRO AVSS1 74 28 FOO OUTL 73 29 VREF AVDD1 72 IC401 MN6627482W CD SIGNAL CONTROL 30 FBAL 31 TBAL 32 FE /TEST 71 IOSEL 70 RESY 69 33 TE DEMPH 68 34 RFENV CRC 67 35 VDET CLVS 66 FLAG 65 36 OFT 37 TRCRS IPFLAG 64 38 /RFDET VDD X2 X1 VSS SBCK BYTCK 61 SUBC VCDF2 CLOCK 62 PCK AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL TDFS PLLF1 40 LD EFM/CK384 FCLK 63 39 BDO 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Figure 13 BLOCK DIAGRAM (2/4) – 13 – CD_L 3 2 1 TO MAIN SECTION CNP103
