Download Service Manual - Basic Four Model 2460 Fixed Media Disk Drive

BFISD 8052
Basic Four@ Model 2460
Fixed Media Disc Drive
Service Manual
Basic Four
Information Systems
®
The information contained herein is proprietary to and considered a trade
secret of Management Assistance Inc.
All rights reserved. No part of this publication may be reproduced,
recorded or stored in a retrieval system, or transmitted, in any form or by
any means, whether electronic, mechanicaL photographic, or otherwise,
without prior written permission of the BaSic Four Information Systems
Division of Management Assistance Inc.
All Rights Reserved
SF/SD 8052
\
Copyright © 1981 by Management Assistance Inc.
All specifications are subject to change without notice.
Basic Four and MAl are registered trademarks of Management
Assistance Inc.
Printed in the United Sta,tes of America
Basic Four Information Systems Division/Management Assistance Inc.
14101 Myford Road, Tustin, California 92680/(714) 731-5100 .
,
TABLE OF CONTENTS
Page
CHAPTER 1
INTRODUCTION
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.3
General Description (Figure 1-1)
Physical Description • • • • • •
Head Disc Assembly • • • • • •
Main Logic PCB • • • • • • • •
Motor Control PCB • • • • • •
Photocell PCB • • • • • • • •
Frame Assembly • • • • • • • •
Power Supply Assembly •• • •
Terminator • • • • • • • • • •
Disc Drive Specifications • • •
• • • • • • • • • •
• • • • • • • • • •
1-1
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-3
CHAPTER 2
INSTALLATION AND OPERATION
2.1
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
2.4
2.5
General • • • • • • • • • • • • • • • • • • • • • •
Unpacking/Packing Procedure • • • • • • • • • • • •
Head Carriage Lock • • • • • • • • • • • • • • • •
Spindle Lock • • • • • • • • • • • • • • • • • • •
Installation Procedure • • • • • • • • • • • • • • •
Pre-Power Checks • • • • • • • • • • • • • • • • •
Interface Cabling • • • • • • • • • • • • • • • •
Dc Voltage Check • • • • • • • • • • • • • • • • •
Controls and Indicators • • • • • • • • • • • • • •
Switches and Jumpers • • • • • • • • • • • • • • • •
2-1
2-1
2-1
2-2
2-3
2-4
2-5
2-8
2-8
2-9
CHAPTER 3
MAINTENANCE
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.4.3
3.5
General Description • • • • • • • • • • • • • • • •
Block Diagram Functional Description (Figure 3-1) •
Diagnostic Tests • • • • • • • • • • • • • • • • • •
General Discription of Silver A5 • • • • • • • • •
General Description of FORMAP • • • • • •
•••
Adjustment Procedures • • • • • • • • • • • • • • •
Power Supply Adjustments • • • • • • • • • • • • •
Power Supply (P /N CP353-1) • • • • • • • • • • •
Power Supply (Model 2981) • • • • • • • • • • •
Write Current Adjustment • • • • • • • • • • • • •
Data Window Adjustement • • • • • • • • • • • ••
Fault Isolation • • • • • • • • • • • • • • • • • •
••••••••••
• • • • • • • • • •
• • • • • • • • • •
• • • • • • • • • •
• • • • • • • • • •
• • • • • • • • • •
• • • __ • • • • • •
• • • • • • • • • •
3-1
3-1
3-3
3-3
3-3
3-4
3-4
3-5
3-6
3-7
3-8
3-9
iii
TABLE OF CONTENTS (continued)
Page
CHAPTER 4
SPARE PARTS LIST/REMOVAL/REPLACEMENT PROCEDURES
4.1
4.2
4.2.1
4.2.2
4.2.3
Introduction • • • • • • • • • • •
Removal/Replacement Procedures • •
Head Disc Assembly (HDA) • • • •
Power Supply Assembly •• • • •
Main Logic PCB and Motor Control
CHAPTER 5
REFERENCE DATA
APPENDIX A
DISC CONTROLLER
iv
• •
• •
• •
• •
PCB
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4-1
4-3
4-3
4-3
4-4
LIST OF ILLUSTRATIONS
Page
Figure
1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
4-1
Model 2460 Fixed Media Disc Drive • • • • • • • • • •
Spindle and Head Carriage Lock • • • • • • • • • • •
Disc Drive Voltage Selection • • • • • • • • • • ••
Main Logic PCB • • • • • • • • • • • • • • • • • • •
Interface Cable/Pin Assignments and Bus Tag Decode •
Functional Block Diagram • • • • • • • • • • • • • •
Data Head Positions • • • • • • • • • • • • • • • • •
Power Supply Adjustments (P/N CP353-1) • • • • • ••
Power Supply Adjustments (Model 2981) • • • • • • ••
Write Current Adjustment • • • • • • • • • • • • • •
Data Window Adjustment • • • • • • • • • • • • • • •
Component Locations • • • • • • • • • • • • • • • • •
1-1
2-2
2-4
2-6
2-7
3-2
3-2
3-6
3-7
3-8
3-9
4-2
LIST OF TABLES
Page
Table
1-1
2-1
3-1
3-2
4-1
Specifications • • • • • • • • • • • • • • • • • • •
Switch Selection • • • • • • • • • • • • • • • • • •
Fault Isolation • • • • • • • • • • • • • • • • • • •
Status Bit Description • • • • • • • • • • • • • • •
Spare Parts List • • • • • • • • • • • • • • • • • •
1-3
2-9
3-9
3-13
4-1
v
CHAPTER 1
INTRODUCTION
1.1
GENERAL DESCRIPTION (FIGURE 1-1)
The Model 2460 Fixed Media Disc Drive, hereafter referred to as the Disc Drive,
is a fixed media, mass memory device used for data storage with a maximum
memory capacity of 66 Megabytes.
The Disc Drive contains a single linear voice
coil head positioner with three data read/write heads and one servo read only
head.
It has a spindle assembly with a single 14 inch disc and brushless dc
drive motor.
It contains the necessary circuitry for positioning the heads and
transferring data and status information via the Controller to a host CPU.
This manual contains physical and functional descriptions, installation/
operation procedures, spare parts lists, and maintenance procedures.
Figure 1-1.
Model 2460 Fixed Media Disc Drive
1-1
1.2
PHYSICAL DESCRIPTION
The Disc Drive stores data on both sides of a single disc using two moving
heads per surface.
A full head area is dedicated to servo information for
track following, seeking, and timing.
A microprocessor controls positioning
during track seeks, provides interface control and monitors disc drive
operation.
The major assemblies of the Disc Drive are: Head Disc Assembly
(HDA) , Main Logic Printed Circuit Board (PCB), Motor Control PCB, Photocell
PCB, Frame Assembly, Power Supply Assembly, and Terminator.
1.2.1
HEAD DISC ASSEMBLY
The Head Disc Assembly is a contamination-resistant enclosure which contains
the disc, spindle assembly, voice coil actuator, head carriage, read/write.
heads, and filter assemblies.
1.2.2
MAIN LOGIC PCB
The Main Logic PCB contains all the circuitry associated with read/write data
transfers, interface transfers, head positioning and control.
1.2.3
MOTOR CONTROL PCB
The Motor Control PCB contains all the circuitry associated with driving the
spindle motor.
This circuitry receives On/Off command from the Main Logic PCB
and spindle rotational feedback from the Photocell PCB.
1.2.4
PHOTOCELL PCB
The Photocell PCB contains three infrared light-emitting diodes and
phototransistors used to monitor and control spindle motor rotation.
1.2.5
FRAME ASSEMBLY
The Frame Assembly is designed to contain the standard assemblies of the Disc
Drive.
1.2.6
POWER SUPPLY ASSEMBLY
The Power Supply Assembly is an integrated power supply that will operate from
50 or 60 Hertz, and at a selectable input voltage of 100,120,220, or 240
volts ac.
1-2
1.2.7
TERMINATOR
The Terminator is a signal line terminator for the last drive connected to a
Controller~
1.3
DISC DRIVE SPECIFICATIONS
Table 1-1 list the Disc Drive specifications.
I
WARNING
This equipment generates, uses, and can radiate radio
frequency energy and if not installed and used in
accordance with the ins tructions manual, may cause
interference to radio communications, as temporarily
permitted by regulation. It has not been tested for
compliance with the limits for Class A Computing
Devices pursuant to Subpart J of Part 15 of FCC Rules,
which are designed to provide reasonable protection
against such interference. Operation of this equipment
in a residential area is likely to cause interference,
in which case the User at his own expense will be
required to take whatever measures may be required to
correct the interference.
TABLE 1-1.
Parameters
SPECIFICATIONS
Characteristics
PHYSICAL
Height
6.8 inches (17.3 cm)
Width
16.6 inches (42.2 cm)
Depth
20.0 inches (50.8 cm)
Weight
47 pounds (21.3 kg)
POWER
Ac Power
100 VAC, 120 VAC,
220 VAC or 240 VAC;
50 or 60 Hz, 425 Watts Max.
Dc Power
+24 VDC + 5%, 7A
-5 VDC + 5%, 2A
+5 VDC + 5%, 4A
+24 VDC-Return
-12 VDC + 5%, 0.7A
1-3
TABLE 1-1.
SPECIFICATIONS (continued)
Parameters
Characteristics
ENVIRONMENTAL
Temperature
Humidity
40% to 60% non-condensing
GENERAL
Capacity (formatted)-
66 Megabytes
Number of discs
1
Number of data heads
3
Number of data cylinders
1116 (0-1115) (excluding diagnostic)
Number of Diagnostic cylinders
5 (2-6 with Switch 10N-5 ON)
(1118-1122)
Bytes per cylinders
60,480
Bytes per track
20 ,160
Track density
960 Tracks per inch (double density)
Recording density
6,430 Bits per inch
Data transfer rate
1.04 Megabytes per second
Recording code
MFM
Interface code
NRZ
Rotational speed
3,100 RPM
Rotational latency (average)
9.7 milliseconds
Rotational latency (maximum)
21.5 milliseconds
Positioning speed
Maximum
(Milliseconds)
Single cylinder
Average
Maximum
1-4
10
48
90
Start Time
30 seconds
Stop Time
60 seconds
Typical
(Milliseconds)
8
45
85
CHAPTER 2
INSTALLATION AND OPERATION
2.1
GENERAL
This chapter contains complete installation and operation instructions for the
Disc Drive.
2.2
UNPACKING/PACKING PROCEDURE
The Disc Drive is normally shipped as part of a data processing system, and
unpacking/packing instructions are included in the appropriate system manual.
When the Disc Drive is shipped as a replacement unit, the following procedures
should be followed.
2.2.1
1.
Visually inspect the container for damage.
immediately.
Report any damage
2.
Remove Disc Drive from container and place on work surface.
3.
Visually inspect for loose, bent, or broken parts.
immediately.
4.
The head carriage and spindle locks (refer to paragraphs 2.2.1 and
2.2.2) are in the locked position for shipment. If received in the
unlocked position, DO NOT INSTALL THIS DISC DRIVE.
5.
When shipping a Disc Drive back to the factory, ensure that the
spindle lock and head carriage lock are properly installed (locked)
and the Disc Drive is packed to prevent damage in shipment.
Report any damage
HEAD CARRIAGE LOCK
Power not being applied to the unit, place the Disc Drive in a flat position
with the Main Logic PCB facing up.
The head carriage lock is located at one
end of the unit (indicated by arrow on the mechanism).
Avoid manual rotation of the spindle or movement of
the carriage. Damage to the disc surface may occur.
2-1
Pull up on the head carriage lock until free from its locked position.
Rotate
the head carriage lock to the unlock position as shown in Figure 2-1.
The head
carriage lock must be placed back in its locked position when the Disc Drive is
moved.
SPINDLE LOCK
HEAD CARRIAGE LOCK
I
f
/_:;:,;--~--_____ LOCKED POSITION
It";.- -~;:..,~ ~
....
_.;:""......
,/............
.......
.....
~:i~t1
Figure 2-1.
2.2.2
UNLOCK
~
Spindle and Head Carriage Lock
SPINDLE LOCK
Power not being applied to the unit and the Disc Drive still in the flat position, locate the spindle lock near the center of the unit (opposite the voice
coil motor) as shown in Figure 2-1.
I
WARNING
Ensure power has not been applied to the unit when the
spindle lock is placed in its unlocked position. The
Spindle motor must not be manually rotated when unlocked.
At this time the fan is free to move and can present
a hazard to the Service Representative.
Place the spindle lock lever in the unlocked position (refer to Figure 2-1).
The spindle lock must be placed back in its locked position when the Disc Drive
is moved.
2-:t.
2.3
INSTALLATION PROCEDURE
The following procedures detail the necessary steps to be followed when
installing a replacement Disc Drive.
1.
Verify the power switch is OFF, and the ac line cord is not connected.
2.
Check that the ac line includes a third-wire earth ground that meets
or exceeds the requirements of the National Electrical Code. This can
be checked by the following procedures:
a.
Locate the circuit breaker that is to supply power to the host
system. With a digital volt meter set to measure 20 volts ac,
and the circuit breaker turned on, measure the drop between the
green and white wires at the power source for the system (wall
outlet). The measured voltage must be less than 1.8 volts ac.
b.
Switch the source circuit breaker off. Measure the resistance
between the green and white wires at the wall outlet. The
resistance must be less than the value shown below for the
applicable circuit breaker rating.
CB Rating
Resistance
15 amperes
20 amperes
30 amperes
0.30 ohms
0.25 ohms
0.15 ohms
If either measurement in steps a or b above is not less than the value
given, request the customer to provide a power source that meets these
requirements.
3.
Remove cabinet covers to gain access to the Disc Drive.
4.
Disconnect and tag all cables from the Main Logic PCB connectors:
J2 (bus) and J9 (radial).
5.
Disconnect power supply plug at rear of cabinet.
6.
Lock Spindle and Head Carriage locks.
7.
Remove the four screws holding drive to host CPU cabinet.
8.
Remove the Disc Drive from the cabinet.
9.
Make pre-power checks (refer to paragraph 2.3.1).
10.
Replace Disc Drive in cabinet.
11.
Unlock Spindle and Head Carriage locks.
12.
Reconnect all tagged cables.
13.
Reconnect power supply plug at rear of cabinet.
14.
Replace covers.
15.
Plug ac line into power source.
2-3
2.3.1
PRE-POWER CHECKS
Verify that the input primary power voltage and the Disc Drive power supply are
configured in the same range.
1.
The following ac voltage ranges are available in the Disc Drive:
100, 120,220, and 240 volts ac.
2.
To select the correct voltage range to match the ac input voltage,
locate the Voltage Selection PCB at the rear of the power supply
mounted on drive frame (Figure 2-2).
VOLTAGE SELECTOR (WAFER)
SLIDING DOOR
REAR VIEH
~~~~~::::t::-
WAFER SLOT
FUSE PULLER
Figure 2-2.
2-4
Disc Drive Voltage Selection
a.
Voltage is selected by the position of this small PCB. The fuse
pull lever, situated above the PCB is pushed to the left to remove
the fuse.
b.
With the fuse removed the selected voltage is read directly from
the PCB. If a change in voltage is required, extract the PCB and
reinsert it so that it is properly positioned for the required ac
voltage designation (100, 120,220,240).
c.
Check the fuse value. A four amp fuse is used with 100 and 120
volts ac, a two amp fuse is used with 220 and 240 volts ac.
d.
Place the fuse pull lever in the extreme right hand position and
insert the correct value fuse into the fuse holder.
e.
No power supply modification is required for changing from 60
cycle to 50 cycle sources.
3.
Locate the Main Logic PCB (Figure 2-3) and verify that connectors,
switch settings and jumpers are in their correct position. The
connectors are listed as follows (for Switch Settings and Jumpers
refer to paragraph 2.5):
Connector
2.3.2
Description
Jl
Terminator connector, or daisy chain
cable connector from/to another Disc
Drive in system.
J2
Bus cable connector to the Controller.
J3
Dc power supply connector.
J4
Motor Control connector.
J5
Voice Coil connector
J6
Servo head and Data head 0 connector.
J7
Data heads 1 and 2 connector.
J8
Control Panel connector used for LEDs in
identifying malfunctions in Disc Drive.
J9
Radial cable connector to the Controller.
INTERFACE CABLING
The Bus cable (J2-P/N 902687) and Radial cable (J9-P/N 902622) are connected
directly from the Disc Drive to the Controller in the host CPU.
Figure 2-4
gives Interface Cabling/Pin assignments and Bus Tag Decode information.
2-5
TO CONTROL PANEL SWITCH
WRITE CURRENT ADJUSTMENT
DATA WINDOW ADJUSTMENT
TP2.
RADIAL "B"
TP9
•
-TP13
00
cc
UJ UJ
....J ....J
1->-
R32
....Jc
~c:(
c:(UJ
lJ.. 0::::
R351
BUS "A"
DRIVE ADDRESS IJI~OIINIIII
SEL. SWITCH *
1
12K
~~ii~~ ill!!!!il
1
HEAD l/HEAD 2
SERVO HEAD/HEAD
VOICE COIL
a
TERMINATOR
MOTOR CONTROL
POWER SUPPLY
* DRIVE ADDRESS SELECTION, 10N-1 THRU 10N-3
WRITE PROTECT, lON-7
DIAGNOSTIC MODE, lON-5
Figure 2-3.
2-6
Main Logic PCB
J2
P2
~
1
11
CONTROLLER PCB
13
15
17
19
21
23
25
27
29
31
33
35
3
5
7
47
37
29
41
43
45
49
BUS CABLE
UNIT SELECT TAG
TAG I(CYLINDER ADDRESS)
TAG 2 (HEAD SELECT)
TAG 3 (CONTROL)
BUS BIT 0
BUS BIT 1
BUS BIT 2
BUS BIT 3
BUS BIT 4
BUS BIT 5
BUS BIT 6
BUS BIT 7
BUS BIT 8
BUS BIT 9
UNIT SELECT 1
UNIT SELECT 2
UNIT SELECT 4
UNIT READY
INDEX
SECTOR
FAULT
SEEK ERROR
ON CYLINDER
OPEN CABLE
RADIAL CABLE
WRITE CABLE
15 SERVO CABLE
3
5 . READ DATA
READ CLOCK
9
WRITE CLOCK
11
SEEK END
19
UNIT SELECTED
21 SECTOR
23
INDEX
25
K
~
0
DISC MAIN
LOGIC PCB
-
~
BUS
BIT
J2
r-
TAG 1
TAG 2
CYLINDER HEAD
ADDRESS SELECT
1
1
1
2
2
2
4
4
3
8
8
4
16
5
32
6
64
7
126
8
256
1024*
9
512
2048*
'--
3214
2
6
8
12
'-
TAG 3
CONTROL
WRITE GATE
READ GATE
FAULT CLEAR
REZERO
READ STATUS
*USED. FOR HIGH ORDER CYLINDER ADDRESS
DURING TAG 2 TIME
Figure 2-4.
Interface Cable/Pin Assignments and Bus Tag Decode
2-7
2.3.3
DC VOLTAGE CHECK
Power is applied to the Disc Drive from the host CPU control panel.
To apply
power, complete the following steps (refer to system manual for detailed
system information).
1.
Place power switch in ON position.
2.
When READY indicator comes on, the dc voltage checks may be done
using the following procedure.
3.
2.4
a.
Locate connector J3 on the Main Logic PCB of the Disc Drive.
b.
Test the following voltages.
Connector J3
Voltage Check
Pin 1
GND
Pin 2
+24VDC+l.2VDC
Pin 3
-5VDC+O.25VDC
Pin 4
-12VDC+O.60VDC
Pin 5
+5VDC+O.25VDC
Pin 6
GND
If voltages are not within tolerance, refer to paragraph 3.4.1.
CONTROLS AND INDICATORS
Controls for the Disc Drive are located on the host CPU control panel.
There are two indicator lamps (LEDs) mounted on the Main Logic PCB near J8.
A green lamp will indicate a READY status.
status.
Connector J8 is provided to test the following signals.
Connector J8
Function
Pin 3
READY
Pin 4
GND
Pin 5
ON CYL
Pin 6
FAULT
Pin 7
PWR ON
Pin 8
+5V
Note:
2-8
A red lamp will indicate a FAULT
Pins 1 and 2 not used.
2.5
SWITCHES AND JUMPERS
Drive Address, Write Enable, and Diagnostic mode are selected on Switch ION
located on the Main Logic PCB (see Table 2-1 for Switch selection).
The Sector switch, 12K, is also located on the Main Logic PCB (see Table 2-1
for Switch selection).
TABLE 2-1.
SWITCH SELECTION
Switch ION
SW No.
Position
1
OFF**
Drive Select Address Bit (Binary Weight 1)
2
OFF**
Drive Select Address Bit (Binary Weight 2)
3
OFF**
Drive Select Address Bit (Binary Weight 4)
4
OFF
Reserved
5*
OFF
Diagnostic Mode
6
OFF
Reserved
7
ON
Wri te Enable, All Data Heads
8
OFF
Not used
Function
Switch 12K
SW No.
Position
Sector Number
Binary Weighted
1
OFF
1
2
ON
2
3
OFF
4
4
OFF
8
5
ON
16
6
OFF
32
7
OFF
64
8
OFF
Must be in off position
*SW5 must be placed in ON position when using Diagnostic mode.
**All OFF = Drive 0
2-9
Jumpers are preset at the factory and shall not be removed.
are in correct location.
Three Pin
Two Pin
W4
1-2
WI
we
2-3
W2
W7
1-2
W3
. Wi4
2-3
W5
Wll
1-2
W6
W12
2-3
W9
W16
1-2
WI0
W13
2-10
Verify all jumpers
Jumper contacts are listed as follows:
CHAPTER 3
MAINTENANCE
3.1
GENERAL DESCRIPTION
This chapter provides a block diagram functional description, adjustment
procedures, and troubleshooting procedures.
3.2
BLOCK DIAGRAM FUNCTIONAL DESCRIPTION (FIGURE 3-1)
The Parallel Interface communicates with all functional assemblies of the
Disc Drive and the Controller.
Its major function is to control and monitor
head positioning, spindle speed and status information.
The Servo circuits, head positioner assembly, and Servo Head align the three
Read/Write heads over a specified track location.
The Servo circuits drive
the heads to the landing zone upon detection of a low power condition or if
both On Track and the Move modes are detected.
These circuits also monitor
voice coil speed.
The Read/Write heads and the Read/Write circuits perform the reading and
writing of flux changes onto the disc.
There are three data heads and one Servo head.
Head 1 and head 2 utilize
the top surface, head 0 and the Servo head utilize the bottom surface of
the disc (Figure 3-2).
The Spindle Motor is a brushless permanent magnet dc motor.
The speed of the
motor is controlled by a closed loop optical position encoder and a frequency
to voltage converter.
The Serial Interface communicates with the Controller and handles the transfer
of data and timing signals.
3-1
PARALLEL INTERFACE
(HEAD POSITION,
~
SEQUENCING, STATUS, .................------~
AND OTHER CIRCUITS
CIRCUITS
SERVO CIRCUITS
HEAD POSITIONER
LINEAR VOICE
COIL MOTOR
READ/WRITE HEADS. _r__-------,
HD2
SERVO READ
AND
R/W CI RCU ITS
n
HDO
SERVO HEAD
SPINDLE ASM.
(BRUSHLESS DC
-------~ MOTOR, SPEED
CONTROL CIRCUITS)
->0
SERIAL INTERFACE
(DATA HANDLING
CIRCUITS, INDEX
AND SECTOR MARK)
-WRITE GATE
---.
*WRITE CLOCK
~
*WRITE DATA (NRZ) ~
-READ GATE
---.
1--1--1--1--1---
* REt'\D CLOCK
*(NRZ) READ DATA
-INDEX MARK
-SECTOR MARK
*SERVO CLOCK
* DESIGNATES DIFFERENTIAL SIGNALS
Figure 3-1.
Functional Block Diagram
CYLINDER NUMBERING
DATA BAND 1
HEAD LANDING ZONES
.,DATA BAND 2
~
~
~
~
DISC
"
~~~~~~@@@~~======~========~~
~
~
DATA BAND 0
A A
SERVO BAND
CYLINDER 1120
HEAD/ARM ASSEMBL,
I,
j I,
I
HEAD 2
SERV~
HEAD 1
~
HEAD 0
UPPER ARM
DISC
LOWER ARM
lri
SIDE VIEW OF DISC AND HEADS
Figure 3-2.
3-2
Data Head Positions
CYLINDER 0
3.3
DIAGNOSTIC TESTS
There are two types of diagnostic tests available for the Disc Drive; Silver
A5 and FORMAP.
For a complete functional description of Silver A5 and FORMAP,
refer to the appropriate User's Manual.
3.3.1
GENERAL DESCRIPTION OF SILVER A5
Silver A5 is divided into two groups:
1.
Group 1 - is designed to check most controller functions and the disc
drive's ability to seek and read.
2.
Group 2 - uses the Diagnostic Cylinders to write and format. Checks
are performed on the controller's ability to detect various errors
such as ID, Alternate Cylinder and CRC. In order to run Group 2,
the "Manual Intervention" option must be selected.
3.3.2
GENERAL DESCRIPTION OF FORMAP
FORMAP's basic function is to format the surface of the disc
all flaws, and to store the map on the subject disc.
~
create a map of
However, several of
FORMAP's options can be used for diagnostic purposes.
The six options are:
1.
Surface Read - will read the full surface of the
exceptions to normal status, which is '40' HEX.
2.
Fault Map Report - will display the contents of the fault map which
contains all flagged tracks and their assigned alternate tracks.
3.
Selected Track Certification - will read ori~inal data of a track,
store it, test the track, and if found bad or manually reassigned,
copy that data to the alternat~ track and flag the original as bad.
(REQUIRES OPTION 4 TO HAVE BEEN RUN PREVIOUSLY IN A FAULT MAP CREATED
BY OPTION 4)
4.
Full Surface Certification - will destroy the contents of the whole
disc, test it for flaws, create a new map, and write a bootstrap in
sector zero. The serial is kept in the map and once assigned, cannot
be changed. (REQUIRES AUTHORIZATION)
5.
Logical Sector to Sector, Head, Cylinder - will convert the logical
sector number to the location -of the disc surface by physical sector,
head, and cylinder.
6.
Sector Zero Recovery - will rewrite the-bootstrap in sector zero using
the serial stored in the map. (REQUIRES OPTION 4 TO HAVE BEEN RUN
PREVIOUSLY IN A FAULT MAP CREATED BY OPTION 4)
dis~
and report all
3-3
3.4
ADJUSTMENT PROCEDURES
3.4.1
POWER SUPPLY ADJUSTMENTS
One of two types of power supplies are found on the Disc Drive (pIN CP353-1)
and Model 2981).
Regardless of which type is found, the Disc Drive
must be removed from
adjustment.
th~
system before the power supply can be removed for
Once removed, the power supply can be placed near to and recon-
nected to the Disc Drive.
To remove power supply for adjustments, use the
following procedure.
NOTE
There is no power switch located on the dc power
supply. Power will be applied when the power cord
is connected.
3-4
1.
Remove ac power from the host CPU.
2.
Open host CPU cabinet to gain access to Disc Drive (if required).
3.
Remove ac power plug at rear of Disc Drive power supply.
4.
Remove Disc Drive.
S.
Disconnect dc power supply connector (J3) from Main Logic PCB.
6.
Remove six retaining screws securing power supply to deckplate.
7.
Remove power supply.
8.
Locate adjustments (refer to Figure 3-3 or 3-4).
9.
With power supply removed, reconnect power cable to J3 of the Main
Logic PCB.
10.
Reconnect ac power plug to power supply.
11.
Apply power to host CPU.
12.
Adjust voltages.
13.
If power supply will not meet tolerance, it must be replaced.
OFF power at host CPU.
Turn
14.
Disconnect power supply from Main Logic PCB.
IS.
Disconnect ac power plug from power supply.
16.
Reinstall new power supply in Disc Drive.
17.
Apply power to host
18.
Test voltages.
cpu.
Measurements will be done at connector J3 at the right rear of the Main Logic
PCB.
Ground meter at C186 on side with C186 designator.
Pin 2
+24VDC+1.2VDC
Pin S
+SVDC+O.2SVDC
Pin 3
-SVDC+O.2SVDC
Pin 4
-12VDC+O.60VDC
Check voltage on J3.
Pins 1 and 6 are ground
Use only an insulated shank screwdriver.
occur to the power supply.
Damage may
Adjusting of power supply will require a long (five inch) insulated shank
screwdriver with 1/8 inch blade.
3.4.1.1
Power Supply (P/N CP3S3-1)
Three voltages +S, -S, and +24 must be adjusted by reaching through holes
inside the power supply chassis as shown in Figure 3-3.
The -12 is not
adjustable.
Voltage
Adjustment
Wire Color Leaving Supply
+24V
R20
Red (return is Brown)
+SV
R40
Black (return is Grey)
-SV
R38
Yellow (return is Grey)
-12V
Not Adj.
Orange (return is Grey)
3-S
000000000000
-5 VOLT ADJUSTMENT
(R38)
0000000
+5 VOLT ADJUSTMENT
(R40)
Figure 3-3.
3.4.1.2
+24 VOLT ADJUSTMENT
(R20)
Power Supply Adjustments (PiN CP353-1)
Power Supply (Model 2981)
On this power supply, the adjustments are visible externally as shown in
Figure 3-4.
Voltage
3-6
Adjustment
Wire Color Leaving Supply
+24V
R3
Black with White Lettering
(return is Yellow)
+5V
R14
Red (return is Solid Black)
-5V
R20
Brown (return is Solid Black)
-12V
Not Adj.
Orange
(re~urn
is Solid Black)
(R20) -5 VOLT ADJUSTMENT
(R14) +5 VOLT ADJUSTMENT
(R3) +24 VOLT ADJUSTMENT
Figure 3-4.
3.4.2
Power Supply Adjustments (Model 2981)
WRITE CURRENT ADJUSTMENT
For this adjustment, you must be writing all-ones.
use any tracks which could contain customer data.
track as possible for best display.
Do not use Head 2.
Do not
Write as many sectors on one
With an oscilloscope, use the following
procedure (refer to Figure 2-3 for adjustment location).
Scope:
Tektronix 465 or equivalent
Probes: Two X10 attenuation
Channell to side of R46 facing transistors. Set input to 1 Volt/
Division (0.1 Volt/Division with non-indicating X10 probe).
Channel 2 to other side of R46. Set input to 1 Volt/Division
(0.1 Volt/Division with non-indicating probe).
Vertical display mode to ADD, Channel 2 INVERTED.
near top of graticule.
Time base = 0.2 ms, TRIGGER SLOPE
dc coupled.
=
Position trace
" ", TRIGGER SOURCE
=
Channel 2,
NOTE: Adjust R351 (near R46) for -5V (Figure 3-5).
3-7
ov
ADJUSTING R351
-5V--------------- ~------------------
Figure 3-5.
3.4.3
Write Current Adjustment
DATA WINDOW ADJUSTMENT
For this adjustment, you must first write all ones, then make the adjustments
while reading all-ones.
contain customer data.
display.
Do not use Head 2.
Do not use any tracks which could
Write as many sectors on one track as possible for best
With an oscilloscope, use the following procedure (refer to Figure
2-3 for adjustment location).
Scope:
Tektronix 465 or equivalent
Probes: Two XIO attenuation
Channel 1 to TPI3 (Window) , ground to TP2. Set input to display
0.5 Volt/Division (50 MV/Division with non-indicating XIO probes).
Channel 2 to TP9 (Data) , ground to TP2. Set input to display
0.5 Volt/Division (50 MV/Division with non-indicating XIO probes).
Vertical display mode = CHOPPED (Channel 2 should NOT be inverted).
Time base = 0.1 us with XIO mag, TRIGGER SOURCE = Channell, de
coupling NORMAL mode.
Adjust R32 so Positive-Going edge of Data is in center of low-going
Window pulse (Figure 3-6).
NOTE
It is normal for the display to "jitter".
3-8
DURING READ
FRONT
OF WINDO,W
REAR
OF WINDOW
I~IIIIII(~----
.06us
NOTE:
DURING WRITE, DATA MOVES TO REAR OF WINDOW
Figure 3-6.
3.5
Data Window Adjustment
FAULT ISOLATION
Table 3-1 lists the Fault Isolation procedures for the Disc Drive.
lists the Status Bit information.
Table 3-2
Both tables are designed as an aid in
troubleshooting the Disc Drive.
TABLE 3-1.
FAULT ISOLATION
Spindle Rotation
Symptom
Rotation does
not start.
Possible Cause
Suggested Action
Spindle lock.
Place in Unlock position
Incorrect or missing
voltage at Main PCB
connector J 4.
Check power supply.
+ OFF signal (J4-4)
Check microprocessor reset signal
on Main Logic PCB: should be
false. Check Power-On reset
(POR): should be false. Check
power reset (PRST): should be
false.
is +5 VDC, should be
o volts for rotation.
Defective Hotor
Control Assembly
Check JI-5 of Motor Control Assembly
for +12 volts (LED voltage).
Check fuse in Motor Control Assembly.
3-9
TABLE 3-1.
FAULT ISOLATION (continued)
Spindle Rotation
Symptom
Rotation does
not start.
Spindle rotates
and stops after
about one
minute.
Spindle rotates
but unit does
not come Ready,
or Ready condition comes and
goes.
3-10
Possible Cause
Suggested Action
Defective Photocell
Circui t Board
Check for open LED, defective
connector or phototransistor.
Defective Spindle
Motor
Manually rotate spindle in clockwise directly only (viewed from
bottom) to ensure motor is not
binding. If motor is binding
replaced Disc Drive. NOTE:
Rotation in opposite directions
may damage disc.
Carriage Lock
Place in Unlock position.
Defective Motor
Control Assembly
Replace Motor Control Assembly.
Defective Photocell
Circui t Board
Replace Disc Drive.
Speed Control not
being sensed by
Microprocessor.
Defective Main Logic PCB.
Spindle Motor has
excessive drag.
Replace Disc Drive
Fault Condition being
sensed.
Check Fault Status.
Intermittent power
supply failure.
Replace Power Supply.
Defective Main Logic
PCB.
Replace Main Logic PCB.
Defective Motor
Control Assembly
Replace Motor Control Assembly.
Defective Disc Drive
Replace Disc Drive.
TABLE 3-1.
FAULT ISOLATION (continued)
,...-------------------------_..-_._.. _ - - - - - - - - - - - - - - - - - .
Command Status Transfers
Symptom
Suggested Action
Possible Cause
Incorrect state Device address select
on Unit
switch (ION).
Selected (J9-2I)
Open Cable Detect
true (JI, J2 pin 28).
Refer to Table 2-1 for switch
definition.
Check controller, cable and
connectors.
Unit Select Tag or
Unit Address missing
or mistimed.
Check controller, cable and
connectors.
Selected unit
does not issue
status
Device Not Ready.
Replace Main Logic PCB.
Select unit
does not accept
commands.
Tag and bus da ta
malfunction.
Check controller, cable and
connectors.
Replace Main Logic PCB.
Select Unit
issue Seek
Error.
Defective servo
action.
See Head/Positioning/Servo.
Select Unit
fails to issue
Index.
Defective circuit.
Replace Main Logic PCB.
Servo Head fails to
READ.
See Head/Positioning/Servo.
Head/Positioning/Servo
Symptom
Fails to move
to new Address.
Suggested Action
Possible Cause
Replace Main Logic PCB.
Command transfer
circuitry defect.
Continuous Seek Defective circuitry
Error condition. or connection.
I
I
Defective servo circuitry on Main
Logic PCB. If fault continues
with operational spare installed,
and spindle speed and write circuits are not the source of the
fault, replacement of the disc
drive is recommended.
Fault connection to servo read
head, check J6.
Fault connection to voice coil
actuator, check J5.
Incorrect voltage, check J3.
I
Carriage locked.
3-11
TABLE 3-1.
FAULT ISOLATION (continued)
Head/Positioning/Servo
Symptom
Seeks to incorrect cylinder
address.
Suggested Action
Possible Cause
Defective circuitry
or servo system.
Defective signal from controller
or fault in the interface cable.
Defective circuitry on Main Logic
PCB. If symptom continues with
operational spare installed, and
controller and cable are not the
source of the fault, replacement
of the disc drive is recommended.
Seek rna be correct and method of
checking for correct seek locatio
may be defective. This could be
caused by a read/write fault.
Write Data Transfer
Symptom
Fault is set
with each
attempt to
write data.
Suggested Action
Possible Cause
Incorrect switch
setting or circuit
defect.
See Table 2-2 for switch definition
Multiple heads selected can be
checked at TP20 which will be high
if more than one head is selected.
Act Unsafe condition is checked at
TPI which will be high if there
are not write transitions with Write
Gate true or write transitions with
Write Gate false.
Data is written
incorrectly and
faults does not
set.
Reads data difficultly. See following section, Read Data
Transfer.
Read Data Transfer
Symptom
Reads header
fields and data
fields correctly, but will
not read newly
written data.
3-12
Possible Cause
Defect in write operation.
Suggested Action
Replace Main Logic PCB.
TABLE 3-1.
FAULT ISOLATION (continued)
Read Data Transfer
Symptom
Fails to read,
but will perform a write
operation without a Fault.
Suggested Action
Possible Cause
Defect in Read circuitry.
Check all cable connections.
Replace Main Logic PB. Replace
terminator.
If read error persists after
replacement of Main Logic PCB
and terminator and if cable
connections are correct, it is
possible that the format being
used is erroneous.
If format is correct, replacement
of the disc drive is recommended.
TABLE 3-2. STATUS BIT DESCRIPTION
Status Bit
Description
o
MULTIPLE HEAD SELECT indicates that more than one head
was selected.
1
NO WRITE DATA indicates that transitions in write current
failed to occur with WRITE GATE active.
2
NO WRITE GATE indicates that write current was sensed
when WRITE GATE was not active.
3
OFF TRACK WRITE indicates that the R/W heads were not
within acceptable track following limits while WRITE GATE
was active.
4
READ ONLY indicates that WRITE GATE became active while
the Disc Drive was not "WRITE ENABLED".
5
PLO LOCK ERROR indicates that the PLO signal was not
correctly synchronized.
6
NOT USED, always zero.
7
POWER FAULT indicates that spindle was already spinning
when power was applied.
8
MULTI-TAG indicates that two or more tag lines were
simultaneously active.
9
READ AND WRITE indicates that both READ GATE and WRITE
GATE were simultaneously active.
3-13
TABLE 3-2. STATUS BIT DESCRIPTION (continued)
Status Bit
Description
10
OFF CYLINDER indicates that the positioner was not ON
CYLINDER while WRITE GATE was active.
11
SEEK TIMEOUT indicates that the positioner failed to
return to track 0 with 900 msec; or it failed to complete
a seek operation within 130 msec.
12
SPEED ERROR indicates that the disc failed to reach or
failed to run at operating speed.
13
GUARD BAND ERROR indicates that the positioner entered
the inner or outer guard bands while performing a seek
or restore operation.
14
ILLEGAL CYLINDER indicates that the disc file was
commanded to seek to a cylinder address which does not
exist in the drive.
15
DIAGNOSTIC CYLINDER ERROR indicates that the positioner
has not moved to one of the Diagnostic Cylinders
(Cylinder Address Register 2 to 7).
CHAPTER 4
SPARE PARTS LIST/REMOVAL/REPLACEMENT PROCEDURES
4.1
INTRODUCTION
This chapter contains the spare parts list (Table 4-1) and removal/replacement
procedures. Figure 4-1 shows component locations.
TABLE 4-1.
SPARE PARTS LIST
Item
Number
Number
1
290000
2
290010
200098
Main Logic PCB
3
290020
200083
Motor Control PCB
4
290030
200138
Terminator
5
290100
400384-001
Power Supply Assy
6
293010
330410
Head Disc Assy
MM
Part
Number
B903028-01
Description
Disc Controller PCB
4-1
MAIN LOGIC PCB
TERMINATOR PCB
MOTOR CONTROL PCB
POWER SUPPL Y--~I-
HEAD DISC ASSEMBLY
Figure 4-1.
4-2
Component Locations
4.2
REMOVAL/REPLACEMENT PROCEDURES
Removal/Replacement procedures are given for spared parts.
4.2.1
READ DISC ASSEMBLY (RDA)
1.
Remove ac power from host CPU.
2.
Open host CPU cabinet to gain access to Disc Drive.
3.
Remove ac power from Disc Drive power supply.
4.
Remove four screws securing RDA to host CPU cabinet.
When removing connectors J6 and J7 (R/W Reads
and Servo Read) be careful not to bend the pins.
Damage may occur to the printed wiring.
5.
Disconnect and tag all cables and connectors from Main Logic PCB.
6.
Remove Main Logic PCB located on top of RDA.
7.
Remove Motor Control PCB located on bottom of RDA.
8.
Remove dc power supply located on bottom of RDA.
9.
Replace Disc Drve and reverse steps 8 thru 1.
10.
4.2.2
Ensure that all cables and connectors are secure.
POWER SUPPLY ASSEMBLY
1.
Remove ac power from the host CPU.
2.
Open host CPU cabinet to gain access to Disc Drive.
3.
Remove ac power plug at rear of Disc Drive power supply.
4.
Remove Disc Drive (refer to paragraph 4.2.1).
5.
Disconnect dc power supply connector (J3) from Main Logic PCB.
6.
Remove six screws securing power supply to the deckplate.
7.
Remove power supply.
8.
Replace new power supply in Disc Drive and reverse steps 7 thru 1.
9.
Apply power to host CPU.
4-3
4.2.3
MAIN LOGIC PCB AND MOTOR CONTROL PCB
When removing PCBs, disconnect and tag all cables and connectors.
when replacing PCBs that all cables and connectors are secure.
NOTE
When replacing Main Logic PCB, remove and save
terminator.
4-4
Ensure
CHAPTER 5
REFERENCE DATA
Title
Drawing Number
Main Logic PCB
Schematic
200098
200099
Motor Speed Control
Schematic
200083
200084
Power Supply (CP353-1)
17048
Power Supply (Model 2981)
2981-902
Filtered Power Supplies
330357
Terminator PCB
Schematic
200138
200139
5-1
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APPENDIX
DISC CONTROLLER
FOR
MODEL 2460
FIXED MEDIA DISC DRIVE
TABLE OF CONTENTS
Page
SECTION I
INTRODUCTION
AI.I
AI.2
AI.3
AI.3.1
AI.3.2
AI.4
General Description • •
Physical Description •
Physical Requirements •
Physical Envelope • •
Mounting • • • • • •
Data Reliability • • •
SECTION 2
MAINTENANCE
A2.1
A2.1.1
A2.1.2
A2.1.3
A2.1.4
A2.1.5
A2.1.6
A2.1.7
A2.1.8
A2.2
A2.2.1
A2.2.2
General Description • •
Controller ROM • • •
Microprocessor •• •
DMA Logic • • • • • •
Interrupt Logic • • •
I/O Logic • • • • • •
CRC Logic • • • • • •
Radial Logic • • • •
Bus Logic • • • • • •
Interface Requirements
Electrical Interface
CPU Interface • • • •
SECTION 3
GLOSSARY OF SIGNAL NAMES
A3.1
Glossary
SECTION 4
REFERENCE DATA
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
•
•
•
•
•
•
AI-I
AI-I
AI-3
AI-3
AI-3
AI-3
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
•
•
•
•
•
•
•
•
•
•
•
•
A2-1
A2-1
A2-2
A2-2
A2-2
A2-2
A2-3
A2-3
A2-3
A2-3
A2-3
A2-3
•
•
•
•
•
•
•
• •
• •
• •
• • •
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• • •
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • • • • • • • • • • • • • • • • • • • • • A3-1
LIST OF ILLUSTRATIONS
Figure
A-I
A-2
A-3
Page
System Interconnection • • • • • • • • • • • • • • • AI-I
Disc Interface and Tag Bus Decode • • • • • • • • • • AI-2
Block Diagram of Controller • • • • • • • • • • • • • A2-1
A-iii
APPENDIX A
SECTION I
INTRODUCTION
AI.I
GENERAL DESCRIPTION
The Disc Controller provides the interface between the CPU and Disc Drive.
It
interfaces the 2460 Fixed Media Disc Drive to a Basic Four data processor in a
system configuration.
See Figure A-I for a typical system interconnect
diagram.
BUS CABLE
CPU AND
CONTROLLER
RADIAL CABLE
Figure A-I.
AI.2
I-
BUS
TERMINATOR
DISC UNIT
I-
System Interconnection
PHYSICAL DESCRIPTION
The Diso Controller, hereafter referred to as the Controller, is a single PCB
plugged directy into the main card cage of the processor system.
Two cables
(Radial Cable, PiN 902622 and Bus Cable, PiN 902687) connect the controller to
the Disc Drive.
A complete pin to pin listing of these cables is given in
Figure A-2.
Al-I
P2
h
1
11
CONTROLLER PCB
13
15
17
19
21
23
25
27
29
31
33
35
3
5
7
47
37
29
41
43
45
49
~
K15
3
5
9
11
19
21
23
25
BUS CABLE
UNIT SELECT TAG
TAG I(CYLINDER ADDRESS)
TAG 2 (HEAD SELECT)
TAG 3 (CONTROL)
BUS BIT 0
BUS BIT 1
BUS BIT 2
BUS BIT 3
BUS BIT 4
BUS BIT 5
BUS BIT 6
BUS BIT 7
BUS BIT 8
BUS BIT 9
UNIT SELECT 1
UN IT SELECT 2
UNIT SELECT 4
UNIT READY
INDEX
SECTOR
FAULT
SEEK ERROR
ON CYLINDER
OPEN CABLE
RADIAL CABLE
WRITE CABLE
SERVO CABLE
READ DATA
READ CLOCK
WRITE CLOCK
SEEK END
UNIT SELECTED
SECTOR
INDEX
0
DISC MAIN
LOGIC PCB
'-
3214
2
6
8
12
'"'or
'-
--.-.I
BUS
BIT
J2
r-
TAG 1
TAG 2
CYLINDER HEAD
ADDRESS SELECT
1
1
1
2
2
2
4
4
3
8
8
4
16
5
32
6
64
7
126
8
256
1024*
9
512
2048*
TAG 3
CONTROL
WRITE GATE
READ GATE
FAULT CLEAR
REZERO
READ STATUS
*USED FOR HIGH ORDER CYLINDER ADDRESS
DURING TAG 2 TIME
Fig~re
Al-2
A-2.
Disc Interface and Tag Bus Decode
Al.3
PHYSICAL REQUIREMENTS
Al.3.1
PHYSICAL ENVELOPE
The Controller is housed on a standard Basic Four printed circuit board (PCB)
with all connectors and components mounted thereon.
Al.3.2
MOUNTING
The Controller is installed in the card cage of a standard Basic Four data processing system.
All clearances and airflow provisions normal to the Basic Four
system are observed.
Al.4
DATA RELIABILITY
The data reliability of the Controller is subject to the data reliability
limits of the disc unit.
These limits are:
1.
Soft Error Rate (Recoverable Errors) - Not more than one error in
10 10 of bits of data transferred.
2.
Hard Error Rate (Non-Recoverable Errors) - Not more than one error in
10 13 bits.
Al-3
SECTION 2
MAINTENANCE
A2.1
GENERAL DESCRIPTION
Maintenanc~
of the Controller is limited to replacement of the Controller.
This section will explain the Controller function only as an aid to the
Service Representatives in troubleshooting.
A Functional Block Diagram is given in Figure 3-1 and described below.
CONTROL ROM
(FIRMWARE)
f
-
DMA LOGIC
CPU
INTERRUPT
LOGIC
MIROPROCESSOR
CRC LOGIC
RADIAL
LOGIC
DISC UNIT
""'-
1/0
Figure A-3.
A2.1.1
-
LOGIC
BUS LOGIC
,
Block Diagram of Controller
CONTROLLER ROM
The Control ROM (FIRMWARE) automatically initiates the following:
1.
The Reset Routine.
2.
The Idle Loop.
3.
The Transfer Preparation Routine.
4.
Search ID Routine.
A2-l
A2.1.2
MICROPROCESSOR
The Microprocessor initiates, tests, or controls the entire operations of the
Controller as specified by firmware.
The Microprocessor does three things for each instruction cycle:
it executes
the present instruction (function), it fetches the next instruction, and it
computes the next fetch address, next address, and stack logic.
The Microprocessor does the following:
1.
Translate I/O commands issued by the CPU into commands that the
Disc Drive recognizes.
2.
Performs error checking of information passed between Disc Drive and
CPU.
3.
Detects particular conditions and then issues interrupt commands to
the CPU.
4.
Provides Controller and Disc Drive status information to the CPU.
5.
Implements Direct Memory Access (DMA) transfer between Disc Drive
and Main Memory.
6.
Sychronizes timing.
A2.1.3
DMA LOGIC
The DMA Logic consists of the following:
1.
DMA Interface Logic.
2.
DMA Read/Write Cycle.
3.
DMA Priority.
A2.1.4
INTERRUPT LOGIC
The Interrupt Logic consists of a mask F/F and an interrupt F/F.
If the mask
F/F is set and the interrupt F/F is set, an interrupt will be sent to the CPU
(DMAINT-) •
A2.1.5
I/O LOGIC
The I/O interface logic provides flags used for branch offset by the microprocessor.
These flags are part of the command word which comes from the CPU or
flags which indicate valid data is on the output data lines.
A2-2
A2.1.6
CRC LOGIC
The CRC Logic is responsible for generating and checking the cyclic redundartcy
check bytes for the header and data records on the disc.
A2.1.7
RADIAL LOGIC
The Radial Interface Logic is responsible for the assembly/disassembly of the
disc serial DATAl.
It provides flags for branch offsets to indicate to the
microprocessor when each process has been completed.
A2.1.8
BUS LOGIC
The Disc Bus Interface Logic sends commands to the disc drive and receives
FAULT, SKERR, READY, ONCLY, SCTR, and INDEX from the drive.
A2.2
INTERFACE REQUIREMENTS
A2.2.1
1.
ELECTRICAL INTERFACE
Signal Levels - All signals will be at standard TTL levels.
0.1 to +04
VDC equals logical low
+2.4 to Vcc
VDC equals logical high
The clock and data lines to the disc are differential balanced line
drivers/receivers.
2.
Termination - All TTL signals that pass through lines exceeding 2 feet
in length are terminated with 220 Ohm pull-up and 330 Ohm pull-down
resistors.
3.
Drivers/Receivers - All TTL line drivers are 7438 or equivalent line
drivers. All interface receiver lines are standard TTL input.
A2.2.2
CPU INTERFACE
The CPU Interface signals are as follows:
1.
Master Reset
2.
Clock Phase 1 and 2
3.
I/O Control Registers 1 thru 3
4.
Output Data Bits
a
thru 7
A2-3
5.
Memory Address Bits 0 thru 14 and DMA Memory Address Bit 15
6.
Memory Data Bits
7.
DMA Acknowledge
8.
DMA Request
9.
DMA Interrupt
10.
A2-4
Read Enable
o thru
7
SECTION 3
GLOSSARY OF SIGNAL NAMES
A3.1
GLOSSARY
I 6WAY
This output of the next address control ROM is used to indicate that
a 16-way branch is required.
ADDEN
This signal is generated by the DMA control logic and is used to gate
the contents of the DMA address counter onto the main frame memory
address bus. This signal is true throughout any DMA cycle.
BOX
X = 0 to 7. These are the outputs of the D-register. The D-register
is used to buffer data until it can be written into its destination.
BINDX
This signal is the synchronized and buffered version of the index
signal from the disc. This synchronization is necessary to prevent
a metastable flip-flop in the address logic for the processor.
BRDY
This signal is the synchronized and buffered version of RDY. This
synchronization is necessary to prevent a metastable flip-flop in
the next address logic.
BSCTR
This signal is the synchronized and buffered version of the logical
OR of the index and sector signals from the disc. This synchronization is necessary to prevent a metastable flip-flop in the address
logic for the processor.
BYTE
This signal is generated by the bit counter on each eighth bit during
a data transfer to determine the byte boundaries.
CHCLK
This signal is used by the processor to control the clock changeover
logic. In addition to loading the least significant bit of the
processor output bus into the clock control flip-flop, this signal
initates the series of events necessary to insure a smooth changeover
from one clock to another.
CLKEN
This is a test signal that is used to gate the processor clocks on
and off for testing and single cycle operation with the WCS.
CLRCRC
This signal is used by the processor to reset the CRC generator/
checker.
CLTAG
Set Cylinder Tag. This signal is used by the disc unit to determine
that the information on the disc control bus in cylinder address
information.
CPHX
x
These are timing clocks from the cpu. The controller
runs from these clocks during read data operations and at all other
times except during a write data operation.
CRC
This signal switches the CRC data-into the serial write data stream.
This signal is enabled by CRCENB.
=
I or 2.
A3-1
CRCDTA
This is the serial CRC information that is generated by the CRC chip
for a write operation.
CRCENB
This signal is used during write data transfers to enable the writing
of the CRC. This signal is directly controlled by the processor.
CRCERR
This signal is generated by the CRC chip to indicate that the CRC
that was read in was in error.
CRY
This is the raw carry output of the 2901.
CRYIN
This signal is controlled by the ROM and is used to gate one, zero
or carry saved into the carry input of the 2901.
CRYSAV
This is the saved output of the carry output from the 2901 to be used
for testing, carries, or shift operations in the next processor cycle.
CTTAG
Control Tag. This signal is used by the disc unit to determine that
the information on the disc control bus is control information.
DATAEN
This signal is used by the DMA control logic to gate the contents of
the D-register onto the main frame memory data bus. This signal is
true throughout a DMA cycle only when the controller is performing a
disc data read operation.
DBX
X = 0 thru 7.
u
~",K
This is the processor data input bus.
Disc Generated Clock. This clock is either the disc servo clock or
the disc read clock as the occasion demands.
DECCNT
This signal is used by the processor to decrement the general counter
and test for zero result.
DFLAG
This is the synchronized output of the D-f1ag. The synchronization
is necessary to prevent a metastable flip flop in the address logic
for the processor.
DFLG
This is the raw output of the D-f1ag. This flag is set at any time
that the D-register is loaded, and cleared when data is read from the
D-register.
DIXX
This signal in the I/O control logic is true when IOACTV is true and
the controller detects the DIXX command from the CPU. This signal
is used to transfer data from the controller to the CPU.
DKBSX
x
= 0 thru 9.
These are the disc control bus signals. The information
on this bit is used by the disc unit as either control information,
head addresses, or as a cylinder address.
DMX
x
=
0 thru 7. This is the outputs of the S-register that are directed
to the processor input.
DMA15
This is the most significant address bit from tne DMA address logic to
the memory page control in the CPU. This bit is converted to the
appropriate page control bits in the CPU.
A3-2
DMACK
DMA Acknowledge. This signal from the CPU is used to determine that
the current DMA request has been granted, and the next memory cycle
belongs to the DMA logic.
DMAINT
This is the DMA interrupt request line in the CPU backplane.
DMAQ
This is the output of the D~~ request latch. This signal is true any
time that the processor wants to initiate a DMA cycle.
DMAR
This is the DMA request bus signal on the CPU backplane.
DMASTB
DMA Strobe. This signal is generated by the DMA interface control
logic. This signal is true during the last third of the DMA cycle,
and is used to strobe read data into the controller and to advance
the address counter.
DOXX
This signal in the I/O control logic is true any time that the signal
IOACTV is true and the DOXX command is detected from the CPU. This
signal is used to transfer data from the CPU to the controller.
DTAX
X = 0 thru 7. This is the output from a multiplexer that can switch
from either the shift register or the memory data bus into the
S-register.
E/INSYC
Enable INSYNC. This signal is controlled by the processor and is
used by the processor to control the state of the INSYNC flip-flop.
FAULT
This signal from the disc unit is used to determine that the disc
unit has detected a condition that could lead to the destruction of
data. The disc is therefore interlocked from further data transactions.
FX
X = 0 thru 7. This is the processor output bus. The data on this
bus is moved from the processor to any of several destinations.
HTAG
Set Head Tag. This signal is used by the disc unit to determine that
the data on the disc control bus is head address information.
IDOX
X = 0 thru 7. This is the CPU input bus. This bus is used to transfer
information from the controller to the CPU.
INDEX
This signal from the disc unit is used to indicate that the heads are
currently positioned over the beginning of the track which is also the
beginning of sector zero.
INSYNC
Literally "In Sync". The state of this ,flip-flop is used to permit
data flow when the bit counter is in sync with the data flow.
INT
This signal in the DMA interrupt logic is used to interrupt the CPU
any time this signal is true and MASK is also true.
IONX
N = I thru 3. These are the I/O control signals from the CPU. By
decoding these bits, the appropriate I/O action can be determined.
A3-3
IOACTV
This signal in the I/O control logic is true any time that the (
troller detects its address in conjunction with a COXX command.
signal remains true for the duration of the I/O transfer.
LDADRH
Load the High Address Register. This signal is used by the pro(
to strobe the contents of the processor output bus into the uppe
byte of the DMA address counter.
LDADRL
Load Lower Address Register. This strobe is used by the proces~
to strobe the contents of the processor output bus into the lowe
byte of the DMA address counter.
LDBREG
Load the Buffer Register. This signal is used during data trans
to load the D-register from either the memory or the disc, deper
on the direction of data flow.
LDCLB
This signal is used by the processor to load the contents of the
processor output bus into the lower byte of the general counter.
LDCMB
This signal is used by the processor to load the contents of the
processor output bus into the high byte of the general counter.
LDDREG
This is a strobe generated by the processor that is used to load
contents of the processor into the D-register.
LDLDB
Load Lower Disc Bus Control Register. This strobe which is gene
by the processor is used to clock the contents of the processor
put bus into the lower disc bus control register.
LDPC
This signal is used by the processor to control the contents of
control ROM page control flip-flop.
LDSR
Load the Shift Register. This signal is used during the write c
ation to parallel load the shift register with data.
LDSTAT
This signal is used by the processor to strobe the contents of
processor output bus into the status register.
LDUDB
Load Upper Disc Bus Control Register. This strobe is generated
the processor and is used to clock the contents of the processor
output bus into the upper disc control bus register.
LSHFT
This signal is used by the processor to control the inputs to th
shift registers in the 2901 for a left shift operation.
MAXX
xx
MASK
This signal in the DMA interrupt logic is used to enable the DMA
interrupt request line to the CPU.
MDOX
x
=
00 thru 14.
= 0 thru 7.
memory.
A3-4
t
These are the main frame memory address lines.
This is the unbuffered memory bus from the main f
This is a bi-directional data bus.
MIDCY
This signal generated by the DMA control logic, is used to indicate
that the middle third of a DMA data transfer is now in progress.
MRST
This is the master reset signal from the CPU backplane.
MUXN
N = 1 or 2. These are the raw clocks that are used to generate the
signals TO and Tl. During clock changeover, these signals may contain truncated clocks.
NAX
x
These signals form the least significant four bits of
the next processor address. Since many different signals may be gated
into these bus, this forms the basis for N-way branches.
ODOX
x=0
thru 7. These are the output data lines from the CPU. This
information is used to determine the controller address or to transfer
data from the CPU to the controller.
OFL
This is the raw overflow status bit from the 2901.
OFLSAV
This is the saved overflow bit form the 2901 to be used for testing in
the next processor cycle.
ONCYL
This signal from the disc unit indicates that the disc unit is on a
cylinder and not seeking.
OUTEN
Output Enable. This signal is used to disable the disc bus output
lines when the controller is first powered up. This is to prevent the
random'control information contained in the registers from cauing the
disc unit to force a fault. Once the registers assume a known state,
this signal can be enabled.
POP
This signal is used to indicate that the next address for the processor instruction will come from the contents of the address stack
register.
QO
This is the I/O line for bit 0 of the Q-register in the 2901. Whether
this line is an input or an output is determined by whether there is a
right or left shift operation in progress.
QOSAV
This is the saved output of the QO bit in the 2901 to be used for right
shift operations in the Q-register.
Q7
This. line is the I/O for bit 7 of the Q-register in the 2901. Whether
this line is an input or an output is dependent on the type of shift
operation in progress.
Q7SAV
This is the saved output of bit 7 of the Q-register to be used in left
shift operations for the Q-register in the 2901 in the next processor
cycle.
ROSAV
This is the save output of RAM bit 0 in the 2901 to be used in left
shift operations in the RAM.
R7SAV
This is the saved output of RAM bit 7 from the 2901 to be used in left
shift operations in the next processor cycle.
= 0 thru 3.
A3-5
x
=0
RADX
thru 8. These are the ROM address bits used to fetch the next
instruction from the control ROM for the processor.
RAMO
This is the input/output line for RAM bit 0 in the 2901. Whether this
line is an input or an output is determined by the type of shift operation that is in progress.
RAM7
This is the I/O line for RAM bit 7 in the 2901. Whether this line is
an input or an output is determined by the type of shift operation
that is in progress.
RCLKX
x
L. These are the differential balanced line signals from
the disc that, carry the read data clock. When the read gate is
asserted, this signal may be used to clock data in from the disc unit.
RDATA
This is the received read data from the disc unit. The data takes
the form of serial NRZ data that is clocked in using the read clock.
RDCLK
This is the received read clock from the disc unit. This clock is
used to time the flow of data from the disc unit to the controller
during a read data operation.
RDDLB
Read the Lower Disc Bus Control Register. This strobe generated
by the processor is used to gate the contents of the lower disc bus
control register into the processor data input bus.
RDDMX
This signal is used in the data bus control logic to enable the output of the data mux onto the processor data input bus.
RDDUB
Read Disc Upper Bus Control Register. This strobe is generated by
the processor and is used to gate the contents of the upper disc bus
control register into the processor data input bus.
RDFLAG
Reset the D-flag.
necessary.
RDTAX
x
H or L. These are the differential balanced line signals that
carry read data from the disc unit to the controller.
RDY
This signal is the logical OR of the ready and on cylinder signals
from the disc unit. When this signal is true, a data transfer may
occur.
READ
This flag is controlled by the processor. It is used to control the
flow of data from the disc unit to the memory.
READY
This signal from the disc unit is used to determine that the disc
unit is rotating and up to speed, and no fault exists.
RINT
This signal is used by the processor to reset the MASK and INT flipflops.
ROXX
xx
A3-6
= H or
This signal is used to reset the D-flag whenever
=
= 00 thru 25.
These are the raw ROM outputs that feed the inputs
of the instruction pipeline register. These bits are not used anywhere else since it is the output of the pipeline register that is
used while the next instruction fetch is in progress.
xx
ROMXX
These are the outputs of the ROM pipeline buffer
that contains the instruction for the 2901 part of the processor.
This buffer is loaded on the rising edge of TO.
ROMYY
YY = 26 thru 39. These are the raw ROM output bits that are used
directly in the next address computation logic. The results of the
next address computation are strobed into the address register at the
rising edge of TO.
RSHFT
This signal is used by the processor to control the inputs to the
shift registers in the 2901 for a right shift operation.
RST
This signal is the controller reset from the system. It is used to
reset all of the important functions in the controller for power-on
or for the bootstrap.
RTXX
This signal generated by the DMA transfer logic is used to indicate
that the first third of a DMA transfer cycle is underway.
SADDEN
This output of the DMA control ROM is used to set the address enable
flip-flop on the next clock edge.
SCLK
This is the received servo clock from the disc unit. This clock is
used to time the flow of data from the controller to the disc unit
during a write data transfer. The clock is also re-transmitted to
the disc unit.
SCLKX
x = H or
L. These are the differential balanced line signals for the
disc servo clock. This clock is always kept in sync with the servo
pattern on the disc surface.
SCTR
Sector. This signal from the disc unit indicates that the heads are
currently positioned over the beginning of any sector except sector
zero.
SDFLAG
This signal is used to set the D-flag any time that the D-register
is loaded from the processor.
SDMAQ
This signal is used by the processor to set the DMA request latch.
SDMST
This output of the DMA control ROM is used to set the DMA strobe flipflop on the next clock edge.
SERIN
This is serial data that has been read from the disc.
zero at all times when the read flag is not set.
SEROUT
Serial output of the parallel to serial shift register.
SETS5
Set the S-flag On the Count of 5. This term is used to set the S-flag
during read operations in anticipation of loading data into the
S-register so that by the time that the processor responds to the
S-flag, the data will be there.
= 00 thru 25.
This signal is
A3-7
SF LAG
This is the synchronized and buffered output of the S-flag. The
synchronization is necessary to prevent a metastable flip-flop in
the address logic for the processor.
SFLG
This is the raw output of the S-flag flip-flop. The S-flag is set
when data is loaded into the S-register, and cleared when data is read
from the S-register.
SGNSAV
This is the saved output of the sign bit from the 2901 to be used for
testing in the next processor cycle.
SIGN
This is the raw sign bit from the 2901.
SINT
This signal is used by the processor to control the state of the
signals MASK and INT.
SKERR
Seek Error. This signal from the disc unit is used to determine that
the disc has not completed a seek within a specified time interval and
therefore, the servo is lost and needs to be re-oriented by a rezero
operation.
SMDCY
This output of the DMA control ROM is used to set the mid-cycle
signal flip-flop on the next clock edge.
SRX
X = 0 thru 7.
SRTXX
This output of the DMA control ROM is used to set the RTXX flip-flop
on the next clock edge.
STDC
Set the Disc Control. This signal is used to load the disc transfer
control flags from the processor.
SYNDET
This signal is true when the sync pattern (EE 16 ) is found in the
shift register.
TO
This is the processor clock that is used to define the beginning and
end of the data processing cycle in the processor. On the rising edge
of this clock, all data from the current cycle is strobed into destinations and the new instruction for the upcoming cycle is strobed into
the instruction pipeline register.
Tl
This is one of the major clock signals that controls the processor.
This clock overlaps and lags TO. This clock defines the loading of
the next fetch address for the processor instruction.
W+SD
Write or Sync Detected.
WRITE and SYNDET.
WCLKX
X = H or L. This is the differential balanced line write clock to
the disc unit. This signal is the servo clock re-transmitted by the
controller. This is done to absorb some of the cable and interface
delays.
WDATA
This is the serial data that is to be written on the disc during a
write operation. All data to the disc will pass through this line.
A3-8
Shift register parallel output bit.
This signal is the logical OR of the signals
x
WDTAX
H or L. This is the differential balanced line write data signal
to the disc unit. This passes all data signals to be written to the
disc.
WRITE
This flag is controlled by the processor. It is used to control the
direction of data flow to move data from the memory to the disc.
ZERO
This signal indicates that the general counter has counted down to
zero.
ZEROR
This is the raw zero result flag from the 2901.
ZROSAV
This is the saved output of the zero results bit from the 2901 to
be used for testing in the next processor cycle.
=
A3-9
SECTION 4
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(//)
(I)
(II)
RCU<H
RCLKL
GNO
WCLJ:L
14
WCLKJI
GND
WDTAN
WDTAL
15
lIP
17
GND
U5LCT- (1/)
113
£XPC
(3)
ZD
21
TIPA-
((3)
zz
USBO
0/)
USBI
(I I)
USB 2
(/I)
I~
23
(I)
24
(II)
(I)
25
2ft,
DKBS 5 (II)
(I)
GND
DKB5 ID (Ill
(I)
GND
DKB57 (II)
(I)
GND
DKBsB (In
(I)
6ND
DK859 (It)
38
GND
(I)
¢DQO-
(13 )
MO(/;Co
MAI7-
(I2 )
"'"
(Ill
40
4D
(~)
41
42
SCTJ?GNO
!="AULTGND
4~
MD¢2
(/2)
'13
5KD2R-
44
45
MRST-
(/3)
44
45
MAIS
ACKO{lT-
(12)
OIVlAINT-
(;3)
5V
GND
(II)
39
(lz)
to
USB3
(II)
(II)
SCLJ(L
GND
RDTAL
RDTAI-I
(I)
GND
IND£X-
(I)
(lJ)
(I)
(II)
(I)
47
48
(II)
(I)
GND
(/;NCLY- (II)
(n
GND
READY- (//)
(I)
GND
<I'"
OPNC8L (/I)
4~
3
4
5
GND
n
4f<,
GND
SCLKW
7
8
9
.310
47
48
49
MA03-
2
(I)
4~
(12)
I
(I)
(II)
(I)
(Ill
(I)
GND
USBD
GND
( 13)
41
DMAR-
33
UNIT 7:lIG (II)
r/J004 -
GNJJ
38
(12)
P3
B
51
(13)
(12)
2tD
<'9
30
(0
(I)
15
ltD
17
18
19
20
21
22
PZ
PI
so
baSIC I Four corporatIon ~
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'C!"WGNO 9030'29
I
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scALE
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14
SH
rv
.D
OF
14
Bask; Four
Information Systems
®
Service Manual Change Request
Prepared By:
Title
Address
Date
Manual No. _ _ _ _ _ _ _ Equipment Covered
Pages effected _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Description of requested changes
T
"0
"0
u.
Reason for re.quested change
Fold and staple
IIIII1
BUSINESS REPLY MAIL
FIRST CLASS PERMIT NO. 4388 SANTA ANA. CA
POSTAGE WILL BE PAID BY
Basic Four Information Systems Division/
Management Assistance Inc.
14101 Myford Road,
Tustin, Califo'rnia 92680
Attention: Manager. Field Service Technical Publications Department
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES