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SALIDA_RAM<=nSALIDA_RAM;-----------------------------------------------------------------------------------------------CONSIGNAx256<=nCONSIGNAx256;--------------------------------------------------------------------------------------------CONSIGNABAJARx256<=nCONSIGNABAJARx256;-----------------------------------------------------------------------------------------CNT13<=nCNT13;
CNT_TIME <= nCNT_TIME;
REG_DTX <= nREG_DTX;
end if;
if (CE_200='1') then --Registros con habilitacion de 200 Hz
----------------------------------------------------------------------------------CNT_READ_RAM<=nCNT_READ_RAM;----------------------------------------------------------------------------------------end if;
end if;
end process;
-- Clock enable 10 kHz
process(DIV_10K)
begin
if (DIV_10K = 4999) then
nDIV_10K <= (others=>'0');
else
nDIV_10K <= DIV_10K + 1;
end if;
end process;
CE_10K <= '1' when (DIV_10K=4999) else '0';
-- Clock enable 100 kHz
process(DIV_100K)
begin
if (DIV_100K = 499) then
nDIV_100K <= (others=>'0');
else
nDIV_100K <= DIV_100K + 1;
end if;
end process;
CE_100K <= '1' when (DIV_100K=499) else '0';----------------------------Añadido para la frecuencia
de 100 KHz----------------- Clock enable 100 Hz (DIV_100 se habilita con CE_10K)
process(DIV_100)
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