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Chapter 6
Decoder Architecture and Basic Block
Cache
6.1 Basic Block Cache
As described in Section 5.1, x86 instructions are decoded into transops prior to actual execution
by the core. To achieve high performance, PTLsim maintains a basic block cache (BB cache)
containing the program ordered translated uop (transop) sequence for previously decoded basic
blocks in the program. Each basic block (BasicBlock structure) consists of up to 64 uops and
is terminated by either a control flow operation (conditional, unconditional, indirect branch) or a
barrier operation, i.e. a microcode assist (including system calls and serializing instructions).
6.2 Identifying Basic Blocks
In a userspace only simulator, the RIP of a basic block’s entry point (plus a few other attributes
described below) serves to uniquely identify that basic block, and can be used as a key in accessing
the basic block cache. In a full system simulator, the BB cache must be indexed by much more
than just the virtual address, because of potential virtual page aliasing and the need to persistently
cache translations across context switches. The following fields, in the RIPVirtPhys structure, are
required to correctly access the BB cache in any full system simulator or binary translation system
(128 bits total):
• rip: Virtual address of first instruction in BB (48 bits), since embedded RIP-relative constants and branch encodings depend on this. Modern OS’s map shared libraries and binaries
at the same addresses every time, so translation caching remains effective across runs.
• mfnlo: MFN (Machine Frame Number, i.e. physical page frame number) of first byte in
BB (28 bits), since we need to handle self modifying code invalidations based on physical
addresses (because of possible virtual page aliasing in multiple page tables)
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