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Chapter 4
PTLsim Code Base
4.1 Code Base Overview
PTLsim is written in C++ with extensive use of x86 and x86-64 inline assembly code. It must be
compiled with gcc on a Linux 2.6 based x86 or x86-64 machine. The C++ variant used by PTLsim
is known as Embedded C++. Essentially, we only use the features found in C, but add templates,
classes and operator overloading. Other C++ features such as hidden side effects in constructors,
exception handling, RTTI, multiple inheritance, virtual methods (in most cases), thread local storage and so on are forbidden since they cannot be adequately controlled in the embedded “bare
hardware” environment in which PTLsim runs, and can result in poor performance. We have our
own standard template library, SuperSTL, that must be used in place of the C++ STL.
Even though the PTLsim code base is very large, it is well organized and structured for extensibility. The following section is an overview of the source files and subsystems in PTLsim:
• PTLsim Core Subsystems:
– ptlsim.cpp and ptlsim.h are responsible for general top-level PTLsim tasks and
starting the appropriate simulation core code.
– uopimpl.cpp contains implementations of all uops and their variations. PTLsim implements most ALU and floating point uops in assembly language so as to leverage the
exact semantics and flags generated by real x86 instructions, since most PTLsim uops
are so similar to the equivalent x86 instructions. When compiled on a 32-bit system,
some of the 64-bit uops must be emulated using slower C++ code.
– ptlhwdef.cpp and ptlhwdef.h define the basic uop encodings, flags and registers.
The tables of uops might be interesting to see how a modern x86 processor is designed
at the microcode level. The basic format is discussed in Section 5.1; all uops are
documented in Section 27.
– seqcore.cpp implements the sequential in-order core. This is a strictly functional
core, without data caches, branch prediction and so forth. Its purpose is to provide fast
execution of the raw uop stream and debugging of issues with the decoder, microcode
or virtual hardware rather than a specific core model.
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