Download Xilinx UG029 ChipScope Pro Software and Cores User Guide v6.3

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Chapter 2: Using the ChipScope Pro Core Generator
Output Clock and Data Pin Locations
The clock and data pins are instantiated inside the ILA/ATC core for your convenience.
This means that although you do not have to manually bring the clock and data pins
through every level of hierarchy to the top-level of your design, you do need to specify the
location of these pins in the Core Generator. The pin locations are then added to the *.ncf
file of the ILA/ATC core.
Data Width and Depth
The data width and depth of the ILA/ATC core depend on the transmit rate and the
number of data pins (Table 2-7).
Table 2-7: ILA/ATC Core Capabilities
Number of Transmit
Data Pins
Rate
2-26
Max Width of
DATA Port
Max DATA Depth
(with timestamps)
4
1x
3
2,097,120 (1,048,560)
4
2x
5
1,048,560 (1048560)
4
4x
11
524,280 (262,136)
8
1x
7
2,097,120 (1,048,560)
8
2x
13
1,048,560 (524,280)
8
4x
27
524,280 (262,136)
12
1x
11
2,097,120 (1,048,560)
12
2x
21
1,048,560 (524,280)
12
4x
43
524,280 (262,136)
16
1x
15
2,097,120 (1,048,560)
16
2x
29
1,048,560 (524,280)
16
4x
59
524,280 (262,136)
20
1x
19
2,097,120 (1,048,560)
20
2x
37
1,048,560 (524,280)
20
4x
75
524,280 (262,136)
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ChipScope Pro Software and Cores User Guide
UG029 (v6.3.1) October 4, 2004