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P160 Prototype Module User’s Guide Version 1.1 November 2002 PN# DS-MANUAL-MBEXP2 Memec Design Development Kit Owners Certificate Thank you for purchasing your Memec Design development kit. As an owner of this kit, you can register for access to the Reference Design Center. In the Reference Design Center, you may download reference design examples for this particular kit, along with source code, and application notes. As more reference designs are added, you will be notified via e-mail. Visit the Reference Design Center today at: http://legacy.memec.com/solutions/reference/xilinx/ Your kit serial number is: For technical assistance, contact your local Memec Design distributor office (Memec, Insight or Impact) or send an e-mail to: [email protected] WARRANTY AND LIABILITY DISCLAIMER Notwithstanding any additional, different or conflicting terms or conditions contained in the purchaser’s ordering document or other document, to the maximum extent permitted by applicable law, Memec, LLC and its subsidiaries (“Insight” and “Impact”) expressly disclaim all warranties, conditions, or representations, express, implied, statutory or otherwise, regarding this product or any other services provided by Memec in connection with this product, all of which are provided “as is”, and this disclaimer shall apply to any implied warranties or conditions of merchantability, satisfactory or merchantable quality and fitness for a particular purpose, or those arising from a course of dealing or usage of trade. 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Table of Contents 1 OVERVIEW ....................................................................................................................1 2 P160 PROTOTYPE MODULE.........................................................................................1 3 USER HEADERS ...........................................................................................................2 REVISION HISTORY..............................................................................................................5 APPENDIX A - P160 PROTOTYPE MODULE SCHEMATICS ..................................................6 November 27, 2002 i Figures FIGURE 1– P160 PROTOTYPE MODULE BOARD .............................................................................1 FIGURE 2 – P160 PROTOTYPE MODUL E BLOCK D IAGRAM...............................................................2 November 27, 2002 ii Tables TABLE 1 – J3 PIN ASSIGNMENTS .................................................................................................2 TABLE 2 – J4 PIN ASSIGNMENTS .................................................................................................3 TABLE 3 – J5 PIN ASSIGNMENTS .................................................................................................3 TABLE 4 – J6 PIN ASSIGNMENTS .................................................................................................4 November 27, 2002 iii 1 Overview The P160 Prototype Module provides a useful expansion, probe, and prototype feature in a small, low cost daughter card form-factor, compatible with any main system board containing the P160 expansion interface. The Spartan-II, Spartan-IIE, Virtex-II and Virtex -II Pro system boards from Memec Design all include the P160 interface and can support the P160 Communications Module. Proper user configuration of the main system board is required to enable the P160 interface and the corresponding expansion module test points. This user guide helps provide the necessary details to develop such a configuration. Complete board schematics are provided in Appendix A for your reference. 2 P160 Prototype Module The Memec Design P160 Prototype module connects to the main system development board via the P160 I/O module connectors. This board can be used to prototype various user I/O interfaces. A high-level block diagram of this module is given below followed by tables that show the connector pin assignments. Figure 1– P160 Prototype Module Board November 27, 2002 1 1 2 1 2 P160 Prototype Board 1 2 1 2 Prototype Area J6 Connector J5 Connector J4 Connector J3 Connector 3.3V GND 39 40 39 40 Vin 3.3V 2.5V user led led led led 39 40 39 40 Figure 2 – P160 Prototype Module Block Diagram 3 User Headers The P160 Prototype module provides four 2 x 20 headers for connection to the P160 Expansion signals. These signals are driven from the main system board and are defined by the FPGA design implemented. Tables 1 through 4 define the connections between the headers and the P160 connectors. Corresponding connections between the P160 connectors and the system board FPGA can be found in the related system board User Guide. Table 1 – J3 Pin Assignments FPGA Pin # Vin 2.5V RIOA1 RIOA2 LIOB9 LIOB11 LIOB13 LIOB15 LIO17 LIOB19 LIOB21 LIOB23 LIOB25 LIOB27 LIOB29 LIOB31 LIOB33 LIOB35 LIOB37 LIOB39 November 27, 2002 J3 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA Pin # 3.3V GND NC LIOB8 LIOB10 LIOB12 LIOB14 LIOB16 LIOB18 LIOB20 LIOB22 LIOB24 LIOB26 LIOB28 LIOB30 LIOB32 LIOB34 LIOB36 LIOB38 LIOB40 2 Table 2 – J4 Pin Assignments FPGA Pin # Vin 2.5V TCK TDO TDI TMS FPGA.BITSTREAM SM.DOUT/BUSY FPGA.CCLK DONE INITn PROGRAMn GND GND GND GND GND GND GND GND J4 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA Pin # 3.3V RIOB2 LIOA9 LIOA11 LIOA13 LIOA15 LIOA17 LIOA19 LIOA21 LIOA23 LIOA25 LIOA27 LIOA29 LIOA31 LIOA33 LIOA35 LIOA37 LIOA39 RIOA39 RIOA40 Table 3 – J5 Pin Assignments FPGA Pin # Vin 2.5V NC JTAG_LOOPBACK JTAG_LOOPBACK NC NC NC NC NC NC NC GND GND GND GND GND GND GND GND November 27, 2002 J5 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA Pin # 3.3V RIOB4 RIOB6 RIOB8 RIOB10 RIOB12 RIOB14 RIOB16 RIOB18 RIOB20 RIOB22 RIOB24 RIOB26 RIOB28 RIOB30 RIOB32 RIOB34 RIOB36 RIOB38 RIOB40 3 Table 4 – J6 Pin Assignments FPGA Pin # Vin 2.5V RIOA4 RIOA6 RIOA8 RIOA10 RIOA12 RIOA14 RIOA16 RIOA18 RIOA20 RIOA22 RIOA24 RIOA26 RIOA28 RIOA30 RIOA32 RIOA34 RIOA36 RIOA38 November 27, 2002 J6 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA Pin # 3.3V GND RIOA3/USERLED RIOA5 RIOA7 RIOA9 RIOA11 RIOA13 RIOA15 RIOA17 RIOA19 RIOA21 RIOA23 RIOA25 RIOA27 RIOA29 RIOA31 RIOA33 RIOA35 RIOA37 4 Revision History V1.0 Initial Release V1.1 Update Minor format updates only November 27, 2002 2/13/02 11/27/02 5 Appendix A - P160 Prototype Module Schematics November 27, 2002 6 10 NAME 9 LED 8 7 6 5 4 3 2 1 TEST LOOP VIN H H R1 750R VIN VIN JP2 DS1 LST670-HK G Test Point Loop - Red G 3.3V R2 330R 3.3V JP4 3.3V Test Point Loop - Red DS2 LST670-HK F F 2.5V R3 130 2.5V 2.5V JP6 Test Point Loop - Red DS3 LST670-HK E E JP7 Test Point Loop - Black D GND JP8 D Test Point Loop - Black RIO.A3/USERLED C R4 130 C USER DS4 LST670-HK B B V2MB Test module A A LEDS MemecBoard <OrgAddr1> <OrgAddr2> <OrgAddr3> <OrgAddr4> 10 9 8 7 6 5 4 3 2 Last Modified Friday, October 05, 2001 Size C Designer Jim Elliott 1 Rev 1 Sheet 1 of 3 5 4 3 2 1 D D 2.5V VIN 3.3V 3.3V VIN 2.5V JX1 TCK TMS TDI TDO LIO.A9 LIO.A11 LIO.A13 LIO.A15 LIO.A17 C LIO.A19 LIO.A21 LIO.A23 LIO.A25 LIO.A27 LIO.A29 LIO.A31 LIO.A33 LIO.A35 LIO.A37 LIO.A39 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 GND AIO16 AIO17 AIO18 VIN AIO19 AIO20 AIO21 AIO22 VIN AIO23 AIO24 AIO25 AIO26 VIN AIO27 AIO28 AIO29 AIO30 GND GND AIO46 AIO47 AIO48 GND AIO49 AIO50 AIO51 AIO52 3.3V AIO53 AIO54 AIO55 AIO56 GND AIO57 AIO58 AIO59 AIO60 GND JX2 GND AIO1 BIO2 AIO3 VIN AIO4 AIO5 AIO6 AIO7 VIN AIO8 AIO9 AIO10 AIO11 VIN AIO12 AIO13 AIO14 AIO15 GND GND AIO31 AIO32 AIO33 GND AIO34 AIO35 AIO36 AIO37 3.3V AIO38 AIO39 AIO40 AIO41 GND AIO42 AIO43 AIO44 AIO45 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 FPGA.BITSTREAM SM.DOUT/BUSY RIO.A1 RIO.A2 RIO.A3/USERLED RIO.A4 RIO.A5 RIO.A6 RIO.A7 RIO.A8 RIO.A9 RIO.A10 RIO.A11 RIO.A12 RIO.A13 RIO.A14 RIO.A15 RIO.A16 RIO.A17 RIO.A18 RIO.A19 RIO.A20 RIO.A21 RIO.A22 RIO.A23 RIO.A24 RIO.A25 RIO.A26 RIO.A27 RIO.A28 RIO.A29 RIO.A30 RIO.A31 RIO.A32 RIO.A33 RIO.A34 RIO.A35 RIO.A36 RIO.A37 RIO.A38 RIO.A39 RIO.A40 FPGA.CCLK DONE INITn PROGRAMn LIO.B8 LIO.B9 LIO.B10 LIO.B11 LIO.B12 LIO.B13 LIO.B14 LIO.B15 LIO.B16 LIO.B17 LIO.B18 LIO.B19 LIO.B20 LIO.B21 LIO.B22 LIO.B23 LIO.B24 LIO.B25 LIO.B26 LIO.B27 LIO.B28 LIO.B29 LIO.B30 LIO.B31 LIO.B32 LIO.B33 LIO.B34 LIO.B35 LIO.B36 LIO.B37 LIO.B38 LIO.B39 LIO.B40 X115 Socket JX4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 GND 3.3V CIO1 CIO2 CIO3 CIO4 CIO5 CIO6 CIO7 GND CIO8 CIO9 CIO10 CIO11 3.3V CIO12 CIO13 CIO14 CIO15 GND CIO16 CIO17 CIO18 CIO19 3.3V CIO20 CIO21 CIO22 CIO23 GND CIO24 CIO25 CIO26 CIO27 CIO28 CIO29 CIO30 CIO31 3.3V GND GND DISPLAY.F TCK DISPLAY.G TMS DISPLAY.E TDI DISPLAY.D TDO GND SS.DONE DISPLAY.DP SS.INITn DISPLAY.C SS.DATA DISPLAY.B SS.PROGRAMn DISPLAY.A SS.CCLK GND DIP1 LED1 DIP2 LED2 GND PUSH1 DIP3 PUSH2 DIP4 GND DIP5 PUSH3 DIP6 PUSH4 GND RXD DIP7 TXD DIP8 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 RIO.B2 RIO.B4 RIO.B6 RIO.B8 RIO.B10 RIO.B12 RIO.B14 RIO.B16 RIO.B18 C RIO.B20 RIO.B22 RIO.B24 RIO.B26 RIO.B28 RIO.B30 RIO.B32 RIO.B34 RIO.B36 RIO.B38 RIO.B40 X115 Socket JX3 B B A A V2MB Test module EXPANSION CONNECTORS MemecBoard Suite 540, 1212 31st Ave. NE Calgary, Alberta Canada T2E 7S8 5 4 3 2 1 Last Modified Friday, October 05, 2001 Size C Designer Jim Elliott Rev 1 Sheet 2 of 3 5 4 3 VIN VIN 3.3V RIO.A1 RIO.A2 LIO.B9 LIO.B11 LIO.B13 LIO.B15 LIO.B17 LIO.B19 LIO.B21 LIO.B23 LIO.B25 LIO.B27 LIO.B29 LIO.B31 LIO.B33 LIO.B35 LIO.B37 LIO.B39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 TCK TDO TDI TMS LIO.B8 LIO.B10 LIO.B12 LIO.B14 LIO.B16 LIO.B18 LIO.B20 LIO.B22 LIO.B24 LIO.B26 LIO.B28 LIO.B30 LIO.B32 LIO.B34 LIO.B36 LIO.B38 LIO.B40 FPGA.BITSTREAM SM.DOUT/BUSY FPGA.CCLK DONE INITn PROGRAMn CON2X20 3.3V 2.5V J4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VIN 3.3V 2.5V J3 1 VIN 3.3V 2.5V D 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2.5V J5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RIO.B2 LIO.A9 LIO.A11 LIO.A13 LIO.A15 LIO.A17 LIO.A19 LIO.A21 LIO.A23 LIO.A25 LIO.A27 LIO.A29 LIO.A31 LIO.A33 LIO.A35 LIO.A37 LIO.A39 RIO.A39 RIO.A40 Completes JTAG chain in loopback mode CON2X20 J6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RIO.B4 RIO.B6 RIO.B8 RIO.B10 RIO.B12 RIO.B14 RIO.B16 RIO.B18 RIO.B20 RIO.B22 RIO.B24 RIO.B26 RIO.B28 RIO.B30 RIO.B32 RIO.B34 RIO.B36 RIO.B38 RIO.B40 RIO.A4 RIO.A6 RIO.A8 RIO.A10 RIO.A12 RIO.A14 RIO.A16 RIO.A18 RIO.A20 RIO.A22 RIO.A24 RIO.A26 RIO.A28 RIO.A30 RIO.A32 RIO.A34 RIO.A36 RIO.A38 CON2X20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RIO.A3/USERLED RIO.A5 RIO.A7 RIO.A9 RIO.A11 RIO.A13 RIO.A15 RIO.A17 RIO.A19 RIO.A21 RIO.A23 RIO.A25 RIO.A27 RIO.A29 RIO.A31 RIO.A33 RIO.A35 RIO.A37 D CON2X20 3.3V J7 J8 1 1 J9 1 J10 1 J11 1 J12 1 J13 1 J14 J15 1 1 CON1 CON1 J19 CON1 J20 1 1 CON1 J21 1 CON1 J22 1 CON1 J23 1 CON1 J24 1 J25 1 CON1 CON1 CON1 CON1 CON1 J32 1 1 J33 1 J34 1 J35 1 CON1 J27 J28 J29 1 CON1 CON1 J43 CON1 J44 1 CON1 J45 1 CON1 J46 1 CON1 J47 1 CON1 J48 1 CON1 J55 CON1 J56 1 1 CON1 J57 1 CON1 J58 1 CON1 J59 1 CON1 J67 CON1 J68 1 1 CON1 J69 1 CON1 J70 1 CON1 J71 1 CON1 CON1 J51 J52 J53 1 CON1 J79 CON1 J80 1 1 CON1 J81 1 CON1 CON1 CON1 J63 J64 J65 J82 1 J83 1 1 CON1 CON1 CON1 J75 J76 J77 1 CON1 J91 CON1 J92 1 1 CON1 J93 1 CON1 J94 1 CON1 J95 1 CON1 J87 J88 J89 1 CON1 J103 CON1 J104 1 1 CON1 J105 1 CON1 J106 1 CON1 J107 1 CON1 J108 1 CON1 CON1 CON1 J99 J100 J101 1 CON1 J115 CON1 J116 1 1 CON1 J117 1 CON1 J118 1 CON1 J119 1 CON1 J120 1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 J111 J112 J113 1 J127 J128 1 J129 1 CON1 J130 1 J139 CON1 J131 1 J140 1 1 CON1 CON1 J132 1 J141 1 CON1 J142 1 J143 1 CON1 CON1 J123 J124 J125 1 J135 CON1 J151 CON1 J152 1 1 CON1 J153 1 CON1 J154 1 CON1 J155 1 CON1 J163 CON1 J164 1 1 CON1 J165 1 CON1 J166 1 CON1 J167 1 CON1 CON1 J147 J148 J149 1 CON1 J175 CON1 J176 1 1 CON1 J177 1 CON1 J178 1 CON1 J179 1 CON1 CON1 J159 J160 J161 1 CON1 CON1 CON1 CON1 CON1 CON1 CON1 J171 J172 J173 1 J188 1 J189 1 J190 1 J191 1 CON1 J183 J184 J185 1 CON1 J199 CON1 J200 1 1 CON1 J201 1 CON1 J202 1 CON1 J203 1 CON1 J204 1 CON1 CON1 CON1 CON1 CON1 J211 J212 1 J213 1 J214 1 J215 1 CON1 J216 1 CON1 CON1 CON1 J207 J208 J209 1 CON1 CON1 CON1 CON1 CON1 CON1 J224 J225 J226 J227 J228 J229 J230 1 1 1 1 1 CON1 J235 CON1 J236 1 1 CON1 J237 1 CON1 J238 1 CON1 J239 1 1 CON1 J240 1 CON1 CON1 CON1 J220 J221 J222 1 CON1 CON1 CON1 CON1 CON1 CON1 J231 J232 J233 1 4 CON1 J234 1 1 CON1 CON1 CON1 CON1 J243 J244 J245 J246 V2MB Test Module HEADERS 1 1 MemecBoard 1 CON1 CON1 5 A 1 CON1 J242 1 CON1 1 CON1 1 CON1 1 CON1 J241 1 J210 1 J219 1 CON1 CON1 CON1 1 CON1 J223 1 J198 1 J218 1 CON1 1 CON1 J197 1 CON1 J217 1 CON1 J196 1 J206 1 A 1 CON1 J195 1 CON1 1 CON1 J205 1 J186 1 J194 1 1 CON1 CON1 CON1 J193 1 J174 1 CON1 J182 1 CON1 J192 1 CON1 1 CON1 CON1 J187 1 1 CON1 1 CON1 J162 1 CON1 J181 1 CON1 J170 1 CON1 J180 1 1 CON1 1 CON1 J150 1 CON1 J169 1 CON1 J158 1 CON1 J168 1 J138 1 CON1 1 CON1 J137 1 CON1 J157 1 B CON1 J146 1 CON1 J156 1 1 CON1 J136 1 1 CON1 J126 1 CON1 CON1 J145 1 CON1 J134 1 CON1 J144 1 1 CON1 J133 1 CON1 J114 1 CON1 1 CON1 CON1 J122 1 CON1 1 1 CON1 1 B J102 1 CON1 J121 1 CON1 J110 1 1 CON1 1 CON1 J109 1 J90 1 J98 1 1 CON1 CON1 CON1 J97 1 J78 1 CON1 J86 1 CON1 J96 1 CON1 1 CON1 1 CON1 1 CON1 J85 1 J66 1 J74 1 CON1 J84 1 CON1 CON1 J73 CON1 1 CON1 1 CON1 J54 1 J62 1 1 CON1 CON1 CON1 J72 1 J42 1 CON1 1 CON1 J41 1 J50 J61 1 CON1 C 1 CON1 J60 1 CON1 J40 1 1 CON1 CON1 J39 CON1 J49 1 1 J38 1 1 1 J30 1 CON1 J37 1 CON1 J26 1 CON1 J36 1 J18 1 CON1 CON1 J31 C J17 1 CON1 1 CON1 J16 1 CON1 3 CON1 CON1 CON1 2 Suite 540, 1212 31st Ave. NE Calgary, Alberta Canada T2E 7S8 1 Last Modified Friday, October 05, 2001 Size C Designer Jim Elliott Rev 1 Sheet 3 of 3