1
Download VCS/VCSi User Guide
Transcript
The following example shows how to instantiate a checker, called ova_one_hot, from the OVA Checker Library: module test(); Uses a single-line, C style pragma to instantiate the reg [3:0] x; ova_mutex checker from the Checker Library, and wire clk; checks for mutual exclusive of a and b. wire a,b; wire error; // other verilog code // ova bind ova_mutex (1'b1,clk,a,b); /* ova bind Uses a multi-line C++ style ova_forbid_bool (error,clk); pragma to instantiate */ ova_forbid_bool, and check that // ova_begin bind an error is never asserted. // ova_one_hot // #(0, // strict // 4) // bit width // (1'b1, // enable // clk, // clock Uses a multi-line modified C++ // x); // data style pragma to instantiate // ova_end ova_one_hot and checks that // other verilog code signal x has only 1 bit. endmodule // module test Instantiating Context-Independent Full Custom OVA You can inline OVA within Verilog by instantiating independent custom OVA code located in the Verilog file but outside a Verilog module definition. The unit definition associated with the code must be specified outside a Verilog module. This method is demonstrated in the following example: Using OpenVera Assertions 14-56
