Download UG070 Virtex-4 User Guide

Revision History
The following table shows the revision history for this document.
Version
Revision
08/02/04
1.0
Initial Xilinx release. Printed Handbook version.
09/10/04
1.1
In Chapter 1, “Clock Resources”:
Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated Table 1-1, Table 1-2,
Table 1-5, the new Table 1-6. Revised Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7,
Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14, and Figure 1-16. Associated text around
these tables and figures were revised.
In Chapter 2, “Digital Clock Managers (DCMs)”, changes to “FACTORY_JF Attribute” and
in Table 2-7.
In Chapter 9, “System Monitor”:
Changed in Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21,
Figure 9-25, Figure 9-26, and Figure 9-27. Changes to the equation in the Temperature Sensor
section. The following tables had changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 911, Table 9-12, Table 9-14, and Table 9-15. Changes to the entire System Monitor Calibration,
System Monitor VHDL and Verilog Design Example sections.
02/01/05
1.2
In Chapter 1, “Clock Resources”, revised “Global Clock Buffers”, “Clock Regions”, and
“Clock Capable I/O” sections.
In Chapter 4, “Block RAM,” revised “Reset,” page 148 description and Table 4-13.
In Chapter 6, “SelectIO Resources,” removed the device configuration section. The Virtex-4
Configuration Guide describes this information in detail. Edited “SSTL (Stub-Series
Terminated Logic),” page 268. Replaced LVDS_25_DCI with LVDCI_25 in “Compatible
example:,” page 286. Added rule “7” to “DCI in Virtex-4 Hardware,” page 227. Added
“Simultaneous Switching Output Limits,” page 294.
Removed Chapter 9: System Monitor.
04/11/05
1.3
Chapter 1: Revised Table 1-1, page 24, Figure 1-14, and “BUFR Attributes and Modes”
section including Figure 1-21, page 41.
Chapter 2: Revised FACTORY_JF value in Table 2-7, page 67. Added “Phase-Shift Overflow”
section. Clarified global clock discussion in “Global Clock Buffers”, “Clock Regions”, and
“Clock Capable I/O”.
Chapter 4: Added “Built-in Block RAM Error Correction Code” section. Revised Figure 4-6
and Figure 4-8, page 120.
Chapter 5: Revised Table 5-1 and Table 5-2, page 168.
Chapter 6: Revised Table 6-29, page 278.
Chapter 7: Revised “REFCLK - Reference Clock” and added Table 7-10, page 326.
Chapter 8: Added “ISERDES Latencies,” page 364 and “OSERDES Latencies,” page 378.
Revised “Guidelines for Using the Bitslip Sub-Module” section.
09/12/05
1.4
Chapter 2: Revised FACTORY_JF value in Table 2-7, page 67. The LOCKED signal
description is updated in Figure 2-19 and Figure 2-20.
Chapter 6: Revised the “Simultaneous Switching Output Limits” section.
Chapter 8: Added more information to “Clock Enable Inputs - CE1 and CE2,” page 356.
UG070 (v2.0) January 4, 2007
www.xilinx.com
Virtex-4 User Guide