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Download EP93xx User's Guide
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99 9 1/10/100 Mbps Ethernet LAN Controller EP93xx User’s Guide RXStsEnq 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSV 15 14 13 12 11 10 9 8 RSVD RSI Address: 0x8001_00AC - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged Definition: Receive Status Enqueue register. The Receive Status Enqueue register is used to define the number of free entries available in the status queue. Only the Receive Status Increment field is writable and any value written to this field will be added to the existing Receive Status Value. Whenever complete statuses are written by the MAC, the Receive Status Value is decremented by the number read. For example, if the Receive Status Value is 0x07, and the Host writes 0x03 to the Receive Status Increment, the new Receive Status Value will be 0x0A. If the controller then reads two descriptors, the Value will be 0x08. Bit Descriptions: RSVD: Reserved. Unknown During Read. RSV: Receive Status Value. RSI: Receive Status Increment. RXHdrLen 31 30 29 28 27 26 25 24 23 22 RSVD 15 14 13 21 20 19 18 17 16 4 3 2 1 0 RHL2 12 11 10 9 8 7 6 RSVD 5 RHL1 Address: 0x8001_00EC - Read/Write 9-78 DS785UM1 Copyright 2007 Cirrus Logic
