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Download EP93xx User's Guide
Transcript
2222 AC’97 Controller EP93xx User’s Guide Table 22-2. AC’97 Register Memory Map (Continued) 22 Address Type Name Description 0x8088_0030 0x8088_0034 0x8088_0038 0x8088_003C 0x8088_0040 0x8088_0044 0x8088_0048 0x8088_004C 0x8088_0050 0x8088_0054 0x8088_0058 0x8088_005C 0x8088_0060 0x8088_0064 0x8088_0068 0x8088_006C 0x8088_0070 0x8088_0074 0x8088_0078 0x8088_007C 0x8088_0080 0x8088_0084 0x8088_0088 0x8088_008C 0x8088_0090 0x8088_0094 0x8088_0098 0x8088_009C 0x8088_00A0 0x8088_00A4 0x8088_00A8 Read Read Read/Write Read/Write Read/Write Read/Write Read Read Read Read/Write Read/Write Read/Write Read/Write Read Read Read Read/Write Read/Write Read/Write Read/Write Read/Write Read Read/Write Write Read/Write Read/Write Read/Write Read AC97RISR2 AC97ISR2 AC97IE2 AC97DR3 AC97RXCR3 AC97TXCR3 AC97SR3 AC97RISR3 AC97ISR3 AC97IE3 AC97DR4 AC97RXCR4 AC97TXCR4 AC97SR4 AC97RISR4 AC97ISR4 AC97IE4 AC97S1Data AC97S2Data AC97S12Data AC97RGIS AC97GIS AC97IM AC97EOI AC97GCR AC97Reset AC97SYNC AC97GCIS Raw interrupt status register Interrupt Status Interrupt Enable Reserved Data read or written from/to FIFO3. Control register for receive Control register for transmit Status register Raw interrupt status register Interrupt Status Interrupt Enable Reserved Data read or written from/to FIFO4. Control register for receive Control register for transmit Status register Raw interrupt status register Interrupt Status Interrupt Enable Reserved Data received/transmitted on SLOT1 Data received/transmitted on SLOT2 Data received/transmitted on SLOT12 Raw Global interrupt status register Global interrupt status register Interrupt mask register End Of Interrupt register Main Control register RESET control register. SYNC control register. Global channel FIFO interrupt status register. Register Descriptions AC97DRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSVD / DATA (See Definition, below.) 15 14 13 12 11 10 9 8 17 16 1 0 DATA 7 6 5 4 3 2 DATA 22-6 DS785UM1 Copyright 2007 Cirrus Logic
