Download Cortex-M0+ Devices Generic User Guide

The Cortex-M0+ Instruction Set
3.5.1
ADC, ADD, RSB, SBC, and SUB
Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
Syntax
ADCS
{Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS
{Rd,} Rn, Rm, #0
SBCS
{Rd,} Rn, Rm
SUB{S} {Rd,} Rn, <Rm|#imm>
Where:
S
Rd
Rn
Rm
imm
Causes an ADD or SUB instruction to update flags
Specifies the result register
Specifies the first source register
Specifies the second source register
Specifies a constant immediate value.
When the optional Rd register specifier is omitted, it is assumed to take the same value as Rn, for
example ADDS R1,R2 is identical to ADDS R1,R1,R2.
Operation
The ADCS instruction adds the value in Rn to the value in Rm, adding another one if the carry flag
is set, places the result in the register specified by Rd and updates the N, Z, C, and V flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value specified by imm
and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C and V
flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic negative of the
value, and places the result in the register specified by Rd and updates the N, Z, C and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, deducts another one if the
carry flag is set. It places the result in the register specified by Rd and updates the N, Z, C and
V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It places the
result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C and V
flags.
Use ADC and SBC to synthesize multiword arithmetic, see Examples on page 3-22.
See also ADR on page 3-12.
ARM DUI 0662A
ID041812
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