Download Cortex-M0+ Devices Generic User Guide

Contents
Cortex-M0+ Devices Generic User Guide
Preface
About this book ........................................................................................................... vi
Feedback .................................................................................................................. viii
Chapter 1
Introduction
1.1
Chapter 2
The Cortex-M0+ Processor
2.1
2.2
2.3
2.4
2.5
Chapter 3
Instruction set summary ........................................................................................... 3-2
Intrinsic functions ..................................................................................................... 3-5
About the instruction descriptions ............................................................................ 3-6
Memory access instructions .................................................................................. 3-11
General data processing instructions .................................................................... 3-19
Branch and control instructions ............................................................................. 3-33
Miscellaneous instructions ..................................................................................... 3-36
Cortex-M0+ Peripherals
4.1
4.2
4.3
4.4
ARM DUI 0662A
ID041812
Programmers model ................................................................................................ 2-2
Memory model ....................................................................................................... 2-10
Exception model .................................................................................................... 2-16
Fault handling ........................................................................................................ 2-22
Power management ............................................................................................... 2-23
The Cortex-M0+ Instruction Set
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Chapter 4
About the Cortex-M0+ processor and core peripherals ........................................... 1-2
About the Cortex-M0+ peripherals ........................................................................... 4-2
Nested Vectored Interrupt Controller ....................................................................... 4-3
System Control Block .............................................................................................. 4-8
System timer, SysTick ........................................................................................... 4-16
Copyright © 2012 ARM. All rights reserved.
Non-Confidential
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