Download DEVA001 PCI encoder interface card User's Manual

DEVA001 User’s Manual
PCI Absolute SSI interface hardware
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
DO7s[1:0] DO6s[1:0] DO5s[1:0] DO4s[1:0] DO3s[1:0] DO2s[1:0] DO1s[1:0] DO0s[1:0]
5.3.1.12Offset 24h, 28h – Digital I/O direction register
The upper 16 bits of this register are designated the Digital I/O direction registers.
These read / write registers control the direction of digital I/Os.
Digital I/O direction register:
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
IOb1d IOb0d
IOb0d Direction of digital I/O byte 0 (1=Input, 0=Output)
IOb1d Direction of digital I/O byte 1 (1=Input, 0=Output)
5.3.1.13Offset 40h, 44h, 48h – Channel control register 0
The lower 16 bits of these registers are designated Channel control register 0. These
read / write registers are used to configure the data acquisition mode (such as clock
frequency and bit length) from the SSI encoder. There is a register for each channel.
The registers hold zero after a system reset.
Channel control register 0:
Bit 15
Out Output
0 = Out Low
1 = Out High
Bit 14
Bit 13 - Bit 12
Bit 11 - Bit 8
Gray / Binary
Extra bit mode
Offset
0 = Binary mode 0 = No Extra bit 0 to 15 bits
1 = Gray mode 1 = Power Fail bit
2 = Even Parity bit
3 = Odd Parity bit
Bit 7 - Bit 3
Data length
1 to 31 bits
0 = 32 bits
Bit 2 - Bit 0
Frequency
0 = 2.78 MHz
1 = 1.39 MHz
2 = 926 KHz
3 = 694 KHz
4 = 463 KHz
5 = 347 KHz
6 = 174 KHz
7 = 86.8 KHz
5.3.1.14Offset 40h, 44h, 48h – Channel status register 0
The upper 16 bits of these registers are designated Channel status register 0. These
read-only registers allow access to channel based status information. These bits are
treated as ‘don’t cares’ when writing to these registers.
Channel status register 0:
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
DI0o RCo RARF PWRFDi
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