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Trace
Table 7-2. Data Transfer Instructions (Continued)
PMem Addr [PC[A0..22]
Reg.Val
RegFileL
[0..7]
Dat.Addr
RAM_EEADDR
[0..22]
Dat.Val
1. Address of instruction
1. NA
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. N/A
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. N/A
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. NA
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. NA
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. NA
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data read
3. Data read
3. N/A
3. N/A
1. Address of instruction
1. N/A
1. N/A
1. N/A
2. Address of next instruction
2. N/A
2. N/A
2. N/A
3. Word address of data
write
3. Data write
3. N/A
3. N/A
IN Rd, P
Address of instruction
Value read from port
6 LSB give I/O
address (A)
Value read from port
N/A
OUT P, Rr
Address of instruction
Value written to port
6 LSB give I/O
address (A)
Value written to port
N/A
1. Address of instruction
1. N/A
1. N/A
1. N/A
2. Address of next instruction
2. Value pushed
2. Stack Pointer
2. Value pushed
1. Address of instruction
1. N/A
1. N/A
1. N/A
2. Address of next instruction
2. Value popped
2. Stack Pointer
2. Value popped
Instruction
INSTA[0..15]
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
SPM
PUSH Rr(1)
POP Rd(1)
Note:
Status
Register
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1. Internal Memory
7-8
2523A–AVR–11/02
ICE50 User Guide