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Hardware Description
3V3
nTRST
TDI
TMS
TCK
RTCK
TDO
nSRST
DBGRQ
DBGACK
1 2
3V3
GND
GND
GND
GND
GND
GND
GND
GND
GND
19 20
Figure 3-13 Multi-ICE connector pinout
Table 3-6 JTAG signal description
Name
Description
Function
DBGRQ
Debug request
(from JTAG equipment)
DBGRQ is a request for the processor core to enter the debug
state. It is provided for compatibility with third-party JTAG
equipment.
DBGACK
Debug acknowledge
(to JTAG equipment)
DBGACK indicates to the debugger that the processor core has
entered debug mode. It is provided for compatibility with
third-party JTAG equipment.
DONE
FPGA configured
DONE is an open-collector signal which indicates when FPGA
configuration is complete. Although this signal is not a JTAG
signal, it does effect nSRST. The DONE signal is routed between
all FPGAs in the system through the HDRB connectors. The
master reset controller on the motherboard senses this signal and
holds all the boards in reset (by driving nSRST LOW) until all
FPGAs are configured.
nCFGEN
Configuration enable
(from jumper on module at the
top of the stack)
nCFGEN is an active LOW signal used to put the boards into
configuration mode. In configuration mode all FPGAs and PLDs
are connected to the scan chain so that they can be configured by
the JTAG equipment.
nRTCKEN
Return TCK enable (from core
module to motherboard)
nRTCKEN is an active LOW signal driven by any core module
that requires RTCK to be routed back to the JTAG equipment. If
nRTCKEN is HIGH, the motherboard drives RTCK LOW. If
nRTCKEN is LOW, the motherboard drives the TCK signal back
up the stack to the JTAG equipment.
ARM DUI 0138A
Copyright © 2000 ARM Limited. All rights reserved.
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