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R Chapter 4: PowerPC 405 APU Controller Virtex4 FX PowerPC405 block APU Controller PowerPC405 core Fabric Co-processor Module (FCM) Decode_Stage Instruction Execute_Stage Operands Exe_Unit Result Writeback_Stage FCM_Decode APUC_Decode Resynchronization_Interface Decode FCM_Exe_Unit LoadData load_reg LoadWB_Stage UG018_04_01_040904 Figure 4-1: Pipeline Flow Diagram The APU Controller serves two purposes: It performs clock domain synchronization between the fast PowerPC clock and the slow FCM interface clock, and it can be configured to decode certain FCM instructions. Depending on the FCM application, the APU Controller can decode all instructions or no instructions at all, or decode some while the FCM decodes others. A floating point unit (FPU) is an example of a good FCM candidate. In the case of an FCM FPU, the APU Controller is capable of decoding all PowerPC floating point instructions. The FCM interface is a Xilinx adaptation of the native Auxiliary Processor Unit interface implemented on the IBM processor core. The hard core APU Controller bridges the PowerPC 405 APU interface and the external FCM interface. FCM Instruction Processing FCM instruction decoding can be done by the APU Controller or by the FCM, however, all instruction execution is done in the FCM. There are two types of instructions that can be executed by an FCM: pre-defined and user-defined (UDI). A pre-defined instruction has its format defined by the PowerPC instruction set (for example, floating point), and the FCM is simply a co-processor performing the ISA-defined execution. A user-defined instruction 184 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004
