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DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
Identification
DTM64315B 256Mx72
2GB 1Rx4 PC3-10600R-9-10-C1
Performance range
Clock / Module Speed / CL-tRCD -tRP
667 MHz / PC3-10600 / 9-9-9
533 MHz / PC3-8500 / 8-8-8
533 MHz / PC3-8500 / 7-7-7
400 MHz / PC3-6400 / 6-6-6
Description
Features
240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high
Operating Voltage: 1.5V ± 0.075
I/O Type: SSTL_15
On-board I2C temperature sensor with integrated serial presencedetect (SPD) EEPROM
Data Transfer Rate: 10.6 Gigabytes/sec
Data Bursts: 8 and burst chop 4 mode
ZQ Calibration for Output Driver and On-Die Termination (ODT)
Programmable ODT / Dynamic ODT during Writes
Programmable CAS Latency: 6, 7, 8, and 9
Bi-Directional Differential Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 14/11/3
DTM64315B is a registered 256Mx72
memory module, which conforms to
JEDEC's DDR3, PC3-10600 standard. The
assembly is a Single-Rank comprised of
eighteen 256Mx4 DDR3 Hynix SDRAMs.
One 2K-bit EEPROM is used for Serial
Presence Detect and a combination
register/PLL, with Address and Command
Parity, is also used.
Both output driver strength and input
termination impedance are programmable to
maintain signal integrity on the I/O signals in
a Fly-by topology.
A thermal sensor accurately monitors the
DIMM module and can prevent exceeding
the maximum operating temperature of 95C.
Fully RoHS Compliant
Pin Configuration
Front Side
Pin Description
Back Side
Name
Function
1 VREFDQ 31 DQ25
61 A2
91 DQ41 121 VSS
151 VSS
181 A1
211 VSS
CB[7:0]
Data Check Bits
2 VSS
32 VSS
62 VDD
92 VSS
152 DQS12
182 VDD
212 DQS14
DQ[63:0]
Data Bits
3
4
5
6
33 /DQS3
34 DQS3
35 VSS
36 DQ26
63 CK1*
64 /CK1*
65 VDD
66 VDD
93
94
95
96
153
154
155
156
183
184
185
186
213
214
215
216
DQS[17:0], /DQS[17:0]
CK[1:0], /CK[1:0]
CKE[1:0]
/CAS
Differential Data Strobes
Differential Clock Inputs
Clock Enables
Column Address Strobe
7 DQS0 37 DQ27
8 VSS
38 VSS
9 DQ2
39 CB0
67 VREFCA
68 PAR_IN
69 VDD
97 DQ43 127 VSS
98 VSS
128 DQ6
99 DQ48 129 DQ7
157 VSS
158 CB4
159 CB5
187 /Event
188 A0
189 VDD
217 VSS
218 DQ52
219 DQ53
/RAS
/S[3:0]
/WE
Row Address Strobe
Chip Selects
Write Enable
10 DQ3
11 VSS
12 DQ8
40 CB1
41 VSS
42 /DQS8
70 A10/AP
71 BA0
72 VDD
100 DQ49 130 VSS
101 VSS
131 DQ12
102 /DQS6 132 DQ13
160 VSS
161 DQS17
162 /DQS17
190 BA1
191 VDD
192 /RAS
220 VSS
221 DQS15
222 /DQS15
A[15:0]
BA[2:0]
ODT[1:0]
Address Inputs
Bank Addresses
On Die Termination Inputs
13 DQ9
43 DQS8
73 /WE
103 DQS6 133 VSS
163 VSS
193 /S0
14 VSS
15 /DQS1
16 DQS1
17 VSS
44 VSS
45 CB2
46 CB3
47 VSS
74 /CAS
75 VDD
76 /S1
77 ODT1
104 VSS
105 DQ50
106 DQ51
107 VSS
18 DQ10
19 DQ11
20 VSS
48 VTT
49 VTT
50 CKE0
78 VDD
79 /S2, NC*
80 VSS
108 DQ56 138 DQ15
109 DQ57 139 VSS
110 VSS
140 DQ20
168 /RESET
169 CKE1
170 VDD
198 /S3, NC*
199 VSS
200 DQ36
171 A15
DQ0
DQ1
VSS
/DQS0
122 DQ4
/DQS5 123 DQ5
DQS5 124 VSS
VSS
125 DQS9
DQ42 126 /DQS9
134 DQS10 164
135 /DQS10 165
136 VSS
166
137 DQ14 167
/DQS12
VSS
DQ30
DQ31
VDD
CK0
/CK0
VDD
/DQS12
VSS
DQ46
DQ47
223 VSS
SA[2:0]
SPD Address
224
225
226
227
SCL
SDA
VSS
VDD
SPD Clock Input
SPD Data Input/Output
Ground
Power
228 DQ61
229 VSS
230 DQS16
VDDSPD
VREFDQ
VREFCA
SPD EEPROM Power
Reference Voltage for DQ
Reference Voltage for CA
201 DQ37
231 /DQS16
VTT
Termination Voltage
202
203
204
205
206
207
232
233
234
235
236
237
/Event
NC
Temperature Sensing
No Connection
CB6
194
CB7
195
VSS
196
NC (TEST) 197
VDD
ODT0
A13
VDD
DQ54
DQ55
VSS
DQ60
21 DQ16
51 VDD
81 DQ32
111 /DQS7 141 DQ21
22 DQ17
23 VSS
24 /DQS2
25 DQS2
26 VSS
27 DQ18
52 BA2
53 /ERR_OUT
54 VDD
55 A11
56 A7
57 VDD
82 DQ33
83 VSS
84 /DQS4
85 DQS4
86 VSS
87 DQ34
112 DQS7
113 VSS
114 DQ58
115 DQ59
116 VSS
117 SA0
142 VSS
172
143 DQS11 173
144 /DQS11 174
145 VSS
175
146 DQ22 176
147 DQ23 177
28 DQ19
58 A5
88 DQ35
118 SCL
148 VSS
178 A6
208 VSS
238 SDA
29 VSS
30 DQ24
59 A4
60 VDD
89 VSS
90 DQ40
119 SA2
120 VTT
149 DQ28
150 DQ29
179 VDD
180 A3
209 DQ44
210 DQ45
239 VSS
240 VTT
A14
VDD
A12/ /BC
A9
VDD
A8
VSS
DQS13
/DQS13
VSS
DQ38
DQ39
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
* Not used
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 1
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
Front view
133.35
[5.250]
9.50
[0.374]
30.00
[1.181]
17.30
[0.681]
5.00
[0.197]
5.175
[0.204]
47.00
[1.850]
71.00
[2.795]
2.50
[0.098]
123.00
[4.843]
Back view
Side view
4.00Max
[0.157] Max
4.00 Min
[0.157] Min
1.27 ±.10
[0.0500 ±0.0040]
Notes
Tolerances on all dimensions except where otherwise
indicated are ±.13 (.005).
All dimensions are expressed: millimeters [inches]
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 2
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
/RS0
/DQS0
DQS0
V SS
/DQS9
DQS9
/DQS CS
DQS
DQR[3:0]
/DQS DQS
CS
/CS DM
I/O[3:0]
/DQS10
DQS10
/DQS1
DQS1
/DQS
DQR[11:8]
DQS
CS
/CS DM
/DQS DQS
CS
I/O[3:0]
DQR[15:12]
/DQS2
DQS2
/CS DM
/DQS DQS
CS
I/O[7:0]
I/O[3:0]
DQR[23:20]
/DQS3
DQS3
/CS DM
/DQS DQS
CS
I/O[3:0]
I/O[7:0]
DQR[31:28]
/DQS8
DQS8
/CS DM
/DQS DQS
CS
I/O[3:0]
I/O[7:0]
CBR[7:4]
/DQS4
DQS4
/CS DM
/DQS DQS
CS
I/O[3:0]
I/O[7:0]
DQR[39:36]
/DQS5
DQS5
/CS DM
/DQS DQS
CS
I/O[3:0]
I/O[7:0]
DQR[47:44]
/DQS6
DQS6
/CS DM
/DQS DQS
CS
I/O[3:0]
I/O[7:0]
/DQS16
DQS16
/DQS DQS
CS
/DQS DQS
CS
/CS DM
I/O[3:0]
I/O[7:0]
DQR[63:60]
All 15 OHMS
CBR[7:0]
DQSR[17:0]
DQS[17:0]
/DQS[17:0]
/DQSR[17:0]
GLOBAL SDRAM CONNECTS
All 39 OHMS
BA[2:0]R
PAR_IN
/CASR
/WER
VTT
BA[2:0]R
A[15:0]R
CK0
120
OHMS
/CK0
All 39 OHMS 100 nF
LCLK[1:0]
RCLK1:0]
/LCLK[1:0]
/RCLK[1:0]
/RASR
/CASR
/WER
DECOUPLING
VDDSPD
VDD
VREF_DQ
VSS
VREF_CA
VTT
CKE0R
ODT0R
/ERR_OUT
L,R(CLK)[1:0]
Serial PD
All Devices
All SDRAMs
All Devices
All SDRAMs
All SDRAMs
/EVENT
/L,R(CLK)[1:0]
All 240 OHMS
/RESET
All 39 OHMS
CKE0R
ODT0R
CS0R
/RS0
A[15:0]
/RAS
/CAS
/WE
CKE0
VDD
All 39 OHMS 100 nF
/S0
/S1
BA[2:0]
ODT0
A[15:0]R
/RASR
VDD
All
22 OHMS
REG / PLL
CB[7:0]
/CS DM
I/O[3:0]
I/O[7:0]
TO SDRAMS
DQR[63:0]
DQ[63:0]
/CS DM
I/O[3:0]
I/O[7:0]
DQR[55:52]
/DQS7
DQS7
DQR[59:56]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS15
DQS15
/DQS DQS
CS
DQR[51:48]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS14
DQS14
/DQS DQS
CS
DQR[43:40]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS13
DQS13
/DQS DQS
CS
DQR[35:32]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS17
DQS17
/DQS DQS
CS
CBR[3:0]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS12
DQS12
/DQS DQS
CS
DQR[27:24]
/CS DM
I/O[3:0]
I/O[7:0]
/DQS11
DQS11
/DQS DQS
CS
DQR[19:16]
/CS DM
I/O[3:0]
DQR[7:4]
SDRAMS
ZQ
VTT
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
SCL
V SS
TEMPERATURE MONITOR/
SERIAL PD
SA0
SA1
SDA
SA2
Page 3
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
Absolute Maximum Ratings
(Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.)
PARAMETER
Symbol
Minimum
Maximum
Unit
Temperature, non-Operating
TSTORAGE
-55
100
C
TA
0
70
C
Ambient Temperature, Operating
TCASE
0
95
C
VDD
-0.4
1.975
V
VIN,VOUT
-0.4
1.975
V
DRAM Case Temperature, Operating
Voltage on VDD relative to VSS
Voltage on Any Pin relative to VSS
Notes:
DRAM Operating Case Temperature above 85C requires 2X refresh.
Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Power Supply Voltage
Symbol
VDD
Minimum
1.425
Typical
1.5
Maximum
1.575
Unit
V
Note
I/O Reference Voltage
VREFDQ
0.49 VDD
0.50 VDD
0.51 VDD
V
1
I/O Reference Voltage
VREFCA
0.49 VDD
0.50 VDD
0.51 VDD
V
1
Notes:
1) The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may
not exceed ±1% of its DC value. For Reference VDD/2 ± 15 mV.
DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(DC)
Minimum
VREF + 0.1
Maximum
VDD
Unit
V
Logical Low (Logic 0)
VIL(DC)
VSS
VREF - 0.1
V
AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(AC)
Minimum
VREF + 0.175
Maximum
-
Unit
V
Logical Low (Logic 0)
VIL(AC)
-
VREF - 0.175
V
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 4
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Differential Input Logic High
Differential Input Logic Low
Differential Input Cross Point Voltage
relative to VDD/2
Symbol
VIH.DIFF
Minimum
+0.200
Maximum
DC:VDD AC:VDD+0.4
Unit
V
VIL.DIFF
DC:VSS AC:VSS-0.4
-0.200
V
VIX
- 0.150
+ 0.150
V
Capacitance (TA = 25 C, f = 100 MHz)
PARAMETER
Pin
Symbol
Minimum
Maximum
Unit
CCK
1.5
2.5
pF
BA[2:0], A[15:0], /RAS, /CAS, /WE
CI
1.5
2.5
pF
/S[1:0], CKE[1:0], ODT[1:0]
CI
1.5
2.5
Input Capacitance, Clock
Input Capacitance,
Address
Input Capacitance Control
CK0, /CK0
Input/Output Capacitance
DQ[63:0], CB[7:0] DQS[17:0], /DQS[17:0]
CIO
1.5
2.5
pF
ZQ Capacitance
ZQ
CZQ
-
6
pF
DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Input Leakage Current
Symbol
Minimum
Maximum
Unit
Note
IIL
-18
+18
μA
1,2
IOL
-10
+10
μA
2,3
(Any input 0 V < VIN < VDD)
Output Leakage Current
(0V < VOUT < VDDQ)
Notes:
1) All other pins not under test = 0 V
2) Values are shown per pin
3) DQ, DQS, DQS and ODT are disabled
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 5
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Operating One
Bank ActivePrecharge Current
Operating One
Bank Active-ReadPrecharge Current
Precharge PowerDown Current
Precharge PowerDown Current
Precharge Quiet
Standby Current
Precharge Standby
Current
Active Power-Down
Current
Active Standby
Current
Operating Burst
Write Current
Operating Burst
Read Current
Burst Refresh
Current
Self Refresh
Current
Operating Bank
Interleave Read
Current
Symbol
IDD0
IDD1
IDD2P
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
Test Condition
Operating current : One bank ACTIVATE-to-PRECHARGE
Operating current : One bank ACTIVATE-to-READ-toPRECHARGE
Precharge power down current: (Slow exit)
Precharge power down current: (Fast exit)
Precharge quiet standby current
Precharge standby current
Active power-down current
Active standby current
Burst write operating current
Burst read operating current
Refresh current
Self-refresh temperature current: MAX TC = 85°C
All bank interleaved read current
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Max
Value
Unit
1440
mA
1710
mA
180
mA
540
mA
990
mA
990
mA
540
mA
1170
mA
2430
mA
2430
mA
3060
mA
180
mA
3600
mA
Page 6
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
AC Operating Conditions
PARAMETER
Symbol
Min
Max
Unit
Internal read command to first data
tAA
13.5
20
ns
CAS-to-CAS Command Delay
tCCD
4
-
tCK
tCH(avg)
0.47
0.53
tCK
tCK
1.5
1.875
ns
tCL(avg)
0.47
0.53
tCK
tDH
65
-
ps
Clock High Level Width
Clock Cycle Time
Clock Low Level Width
Data Input Hold Time after DQS Strobe
tDIPW
400
-
ps
DQS Output Access Time from Clock
tDQSCK
-255
+255
ps
Write DQS High Level Width
tDQSH
0.45
0.55
tCK(avg)
Write DQS Low Level Width
tDQSL
0.45
0.55
tCK(avg)
DQS-Out Edge to Data-Out Edge Skew
tDQSQ
-
125
ps
Data Input Setup Time Before DQS Strobe
tDS
30
-
ps
DQS Falling Edge from Clock, Hold Time
tDSH
0.2
-
tCK(avg)
DQS Falling Edge to Clock, Setup Time
tDSS
0.2
-
tCK(avg)
Clock Half Period
tHP
minimum of tCH or tCL
-
ns
Address and Command Hold Time after Clock
tIH
140
-
ps
DQ Input Pulse Width
tIS
65
-
ps
Load Mode Command Cycle Time
tMRD
4
-
tCK
DQ-to-DQS Hold
tQH
0.38
-
tCK(avg)
Active-to-Precharge Time
tRAS
36
9*tREFI
ns
Active-to-Active / Auto Refresh Time
tRC
49.5
-
ns
RAS-to-CAS Delay
tRCD
13.5
-
ns
-
7.8
μs
Address and Command Setup Time before Clock
o
o
tREFI
o
o
Average Periodic Refresh Interval 0 C < TCASE < 95 C
tREFI
-
3.9
μs
Auto Refresh Row Cycle Time
tRFC
110
-
ns
Row Precharge Time
tRP
13.5
-
ns
Read DQS Preamble Time
tRPRE
0.9
Note-1
tCK(avg)
Read DQS Postamble Time
tRPST
0.3
Note-2
tCK(avg)
Row Active to Row Active Delay
tRRD
Max(4nCK, 6ns)
-
ns
Internal Read to Precharge Command Delay
tRTP
Max(4nCK, 7.5ns)
-
ns
Average Periodic Refresh Interval 0 C < TCASE < 85 C
Write DQS Preamble Setup Time
tWPRE
0.9
-
tCK(avg)
Write DQS Postamble Time
tWPST
0.3
-
tCK(avg)
Write Recovery Time
tWR
15
-
ns
Internal Write to Read Command Delay
tWTR
Max(4nCK, 7.5ns)
-
ns
Notes:
1.
2.
The maximum preamble is bound by tLZDQS(min)
The maximum postamble is bound by tHZDQS(max)
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 7
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
SERIAL PRESENCE DETECT MATRIX
Byte#
Function.
Value
Hex
176
256
Bytes 0-116
0x92
Rev. 1.0
0x10
DDR3 SDRAM
0x0B
Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved -
RDIMM
0
0x01
SDRAM Density and Banks.
Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved -
1Gb
8 banks
0
0x02
11
14
0
0x12
UNUSED
0x00
Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved
4-Bits
1-Rank
0
0x00
Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved -
64-Bits
8-Bits
0
0x0B
2
5
1 (MTB =
0.125ns)
8 (MTB =
0.125ns)
0x52
0x01
1.5ns
0x0C
UNUSED
0x00
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage.
Bit 3 ~ Bit 0. SPD Bytes Used Bit 6 ~ Bit 4. SPD Bytes Total Bit 7. CRC Coverage -
0
1
SPD Revision.
2
Key Byte / DRAM Device Type.
3
4
Key Byte / Module Type.
SDRAM Addressing.
Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved
5
6
Reserved.
Module Organization.
7
Module Memory Bus Width.
8
9
10
11
Fine Timebase (FTB) Dividend / Divisor.
Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor
Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend
Medium Timebase (MTB) Dividend.
Medium Timebase (MTB) Divisor.
12
SDRAM Minimum Cycle Time (tCKmin).
13
Reserved.
14
CAS Latencies Supported, Least Significant Byte.
0x3C
Bit 0. CL = 4 Bit 1. CL = 5 -
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
0x08
Page 8
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 -
X
X
X
X
CAS Latencies Supported, Most Significant Byte.
Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved.
15
0x00
16
Minimum CAS Latency Time (tAAmin).
13.5ns
0x6C
17
Minimum Write Recovery Time (tWRmin).
15.0ns
0x78
18
Minimum RAS# to CAS# Delay Time (tRCDmin).
13.5ns
0x6C
19
Minimum Row Active to Row Active Delay Time (tRRDmin).
6.0ns
0x30
20
Minimum Row Precharge Delay Time (tRPmin).
13.5ns
0x6C
1
1
0x11
36.0ns
0x20
49.5ns
0x8C
Upper Nibbles for tRAS and tRC.
21
24
Bit 3 ~ Bit 0. tRAS Most Significant Nibble Bit 7 ~ Bit 4. tRC Most Significant Nibble Minimum Active to Precharge Delay Time (tRASmin), Least Significant
Byte.
Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant
Byte.
Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant
Byte.
25
Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte.
26
27
22
23
110.0ns
0x70
110.0ns
0x03
Minimum Internal Write to Read Command Delay Time (tWTRmin).
7.5ns
0x3C
Minimum Internal Read to Precharge Command Delay Time (tRTPmin).
7.5ns
0x3C
0
0
0x00
30.0ns
0xF0
X
X
0x83
Upper Nibble for tFAW.
28
29
Bit 3 ~ Bit 0. tFAW Most Significant Nibble Bit 7 ~ Bit 4. Reserved Minimum Four Activate Window Delay Time (tFAWmin), Least Significant
Byte.
SDRAM Optional Features.
30
Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 9
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
SDRAM Drivers Supported.
Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Partial Array Self Refresh (PASR) -
31
32
X
0x81
X
Module Thermal Sensor.
0x80
Bit 6 ~ Bit 0. Thermal Sensor Accuracy Bit 7. Thermal Sensor -
0
With TS
Bit 6 ~ Bit 0. Non-Standard Device Description Bit 7. SDRAM Device Type -
0
Std Mono
0x00
UNUSED
0x00
29<h<=30
0
0x0F
1<th<=2
1<th<=2
0x11
R/C C
Rev.1
0
0x22
1 Register
1 Row
0
0x05
0
No HS
0x00
SDRAM Device Type.
33
34-59
Reserved
Module Nominal Height.
60
Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness.
61
Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used.
Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved -
62
(Registered) DIMM Module Attributes.
Bit 1 ~ Bit 0. # of Registers used on RDIMM Bit 3 ~ Bit 2. # of Rows of DRAMs on RDIMM Bit 7 ~ Bit 4. Reserved -
63
RDIMM Thermal Heat Spreader Solution.
64
Bit 6 ~ Bit 0. Heat Spreader Thermal Characteristics Bit 7. Heat Spreader Solution -
65
Register Manufacturer ID Code, Least Significant Byte (Optional).
UNUSED
0x00
66
Register Manufacturer ID Code, Most Significant Byte (Optional).
UNUSED
0x00
67
Register Revision Number (Optional).
ÿ
0xFF
SSTE32882
0
0x00
UNUSED
0x00
Register Type.
68
69
Bit[2-0] Support Device Bit[7-3] Reserved [SSTE32882]: RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved. SPD must
be programmed as 0x00.
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 10
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
70
71
[SSTE32882]: RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength,
Command/Address.
Bit 1, Bit 0. RC2/DA3,4 Value.Bit 3, Bit 2. RC2/DBA0,1 Value Bit 5, Bit 4. RC3/DA4,3 value, Command/Address A Outputs Bit 7, Bit 6. RC3/DBA0,1 value, Command/Address B Outputs SSTE32882]: RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength,
Control and Clock.
Bit 1, Bit 0. RC4/DA3,4 Control Signals, A Outputs.Bit 3, Bit 2. RC4/DBA0,1 Control Signals, B Outputs Bit 5, Bit 4. RC5/DA4,3 value, Y1/Y1# and Y3/Y3# Clock Outputs Bit 7, Bit 6. RC5/DBA0,1 value, Y0/Y0# and Y2/Y2# Clock Outputs -
RESERVED
RESERVED
Moderate
Moderate
Moderate
Moderate
Moderate
Moderate
0x50
0x55
72
[SSTE32882]: RC7 (MS Nibble) / RC6 (LS Nibble).
UNUSED
0x00
73
[SSTE32882]: RC9 (MS Nibble) / RC8 (LS Nibble).
UNUSED
0x00
74
[SSTE32882]: RC11 (MS Nibble) / RC10 (LS Nibble).
UNUSED
0x00
75
[SSTE32882]: RC13 (MS Nibble) / RC12 (LS Nibble).
UNUSED
0x00
76
[SSTE32882]: RC15 (MS Nibble) / RC14 (LS Nibble).
UNUSED
0x00
77-112
Module-Specific Section
UNUSED
0x00
113
114116
117
Module-Specific Section.
UNUSED
0x00
Module-Specific Section
UNUSED
0x00
Module Manufacturer ID Code, Least Significant Byte
0x01
118
Module Manufacturer ID Code, Most Significant Byte
0x91
119
Module Manufacturing Location
120,121
122125
126
UNUSED
0x00
Module Manufacturing Date
0x20
Module Serial Number
0x20
Cyclical Redundancy Code (CRC).
CRC
0x6B
127
128131
132
Cyclical Redundancy Code (CRC).
CRC
0x70
Module Part Number
D
0x44
133
Module Part Number
A
0x41
134
Module Part Number
T
0x54
135
Module Part Number
A
0x41
136
Module Part Number
R
0x52
137
Module Part Number
A
0x41
138
Module Part Number
M
0x4D
139
Module Part Number
140
Module Part Number
6
0x36
141
Module Part Number
4
0x34
Module Part Number
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
0x20
0x20
Page 11
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
142
Module Part Number
3
0x33
143
Module Part Number
1
0x31
144
Module Part Number
5
0x35
145
Module Part Number
0x20
Module Revision Code
0x20
146,147
148
DRAM Manufacturer ID Code, Least Significant Byte
UNUSED
0x00
149
150175
176255
DRAM Manufacturer ID Code, Most Significant Byte
UNUSED
0x00
Manufacturer’s Specific Data
UNUSED
0x00
Open for customer use
UNUSED
0x00
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 12
DTM64315B
2GB - 240-Pin 1Rx4 Registered ECC DDR3 DIMM
DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528;
Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com
All rights reserved.
The information contained in this document has been carefully checked and is believed to be reliable. However,
Dataram assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the copyrights, patent rights or
trademarks claimed and owned by Dataram.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party
without prior written consent of Dataram.
Document 06566, Revision A, 24-Sep-09, Dataram Corporation © 2009
Page 13