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Processor Configuration Registers
2.19.8
SSKPD—Sticky Scratchpad Data Register
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
Attr
0/0/0/MCHBAR PCU
5D10–5D17h
0000_0000_0000_0000h
RWS
64 bits
Reset
Value
RST/
PWR
Description
63:32
RWS
00000000h
Powerg
ood
Scratchpad Data (SKPD)
Field [34:32] contains the value to match with the PCI PMSYNC
configuration done by BIOS required for discrete USB2PCI cards.
Refer to BWG for more details.
Field [47:35] contains the timer value on top of the PCH hysteresis
value. It is given in units of 10.24 us. Refer to BWG for more
details.
31:30
RWS
00b
Powerg
ood
Reserved for Future Use (RWSVD3)
Bit 30 controls the way BIOS calculate WM3 value. It reflects the
value of PCU_MISC_ENABLES[LNPLLfastLockDisable].
Bit 31 is reserved for future use.
29:24
RWS
00h
Powerg
ood
MPLL Shutdown Latency Time (WM3)
Number of microseconds to access memory if memory is in Self
Refresh (SR) with MDLLs and Memory PLLs shut off (0.5us
granularity).
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
NOTE: The value in this field corresponds to the memory latency
requested to the Display Engine when Memory PLL Shutdown is
enabled. The Display LP3 latency and watermark values
(GTTMMADR offset 0x45110) should be programmed to match the
latency in this register.
23:22
RWS
00b
Powerg
ood
Reserved for Future Use (RWSVD2)
MDLL Shutdown Latency Time (WM2)
Number of microseconds to access memory if the MDLL is
shutdown (requires memory in Self Refresh). The value is
programmed in 0.5 us granularity.
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
NOTE: The value in this field corresponds to the memory latency
requested to the Display Engine when MDLL shutdown is enabled.
The Display LP2 latency and watermark values (GTTMMADR offset
4511Ch) should be programmed to match the latency in this
register.
21:16
RWS
000000b
Powerg
ood
15:14
RWS
00b
Powerg
ood
Datasheet, Volume 2
Reserved for Future Use (RWSVD1)
261