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Host-Primary PCI Express* Bridge Registers (D1:F0)
6.55
ESD—Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
144–147h
02000100h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access
Default
Value
31:24
RO
02h
Port Number (PN): Specifies the port number associated with this element
with respect to the component that contains this element. This port number
value is utilized by the egress port of the component to provide arbitration to
this Root Complex Element.
23:16
RWO
00h
Component ID (CID): Identifies the physical component that contains this
Root Complex Element.
15:8
RO
01h
Number of Link Entries (NLE): Indicates the number of link entries following
the Element Self Description. This field reports 1 (to Egress port only as we don't
report any peer-to-peer capabilities in our topology).
7:4
RO
0h
Reserved
3:0
RO
0h
Element Type (ET): Indicates Configuration Space Element.
6.56
Description
LE1D—Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/MMR
150–153h
00000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access
Default
Value
Description
31:24
RO
00h
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16
RWO
00h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry.
15:2
RO
0000h
1
RO
0b
0
RWO
0b
Reserved
Link Type (LTYP): Indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
Link Valid (LV):
190
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Datasheet