Download Transcend 64MB SDRAM PC133 Unbuffer Non-ECC Memory
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168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C Placement Description The TS8MLS64V6C is an 8M bit x 64 Synchronous Dynamic RAM high-density for PC-133. The TS8MLS64V6C consists of 4pcs CMOS 8Mx16 bits Synchronous DRAMs in TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 168-pin printed circuit board. The TS8MLS64V6C is a Dual In-Line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with A the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high B performance memory system applications. C E Features D • RoHS Production compliant E • Performance Range: PC-133 H • Conformed to JEDEC Standard Spec. G F • Burst Mode Operation. • Auto and Self Refresh. PCB: 09-7132 • CKE Power Down Mode. • DQM Byte Masking (Read/Write) • Serial Presence Detect (SPD) with serial EEPROM • LVTTL compatible inputs and outputs. • Single 3.3V ± 0.3V power supply. • MRS cycle with address key programs. Latency (Access from column address) Burst Length (1,2,4,8 & Full Page) Data Sequence (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. Transcend Information Inc. 1 I 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C Dimensions Side Millimeters Pin Identification Symbol Inches A 133.35±0.40 5.250±0.016 B 65.67000 2.585000 C 23.49000 0.925000 D 8.89000 0.350000 E 3.00000 0.118000 F 31.75±0.20 1.250±0.00800 G 19.80000 0.788000 H 15.80 0.622 I 1.27±0.10 0.050±0.004 Function A0~A11, BA0, BA1 Address input DQ0~DQ63 Data Input/Output. CLK0, CLK2 Clock Input CKE0 Clock Enable Input. /CS0, /CS2 Chip Select Input. /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQM0~DQM7 Data (DQ) Mask SA0~SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add/Data input/output Vcc +3.3 Voltage Power Supply Vss Ground NC No Connection (Refer Placement) Transcend Information Inc. 2 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C Pinouts: Pin Pin Pin Pin No Name No Name 01 Vss 43 Vss 02 DQ0 44 NC 03 DQ1 45 /CS2 04 DQ2 46 DQM2 05 DQ3 47 DQM3 06 Vcc 48 NC 07 DQ4 49 Vcc 08 DQ5 50 NC 09 DQ6 51 NC 10 DQ7 52 *CB2 11 DQ8 53 *CB3 12 Vss 54 Vss 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 Vcc 18 Vcc 60 DQ20 19 DQ14 61 NC 20 DQ15 62 *Vref 21 *CB0 63 *CKE1 22 *CB1 64 Vss 23 Vss 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 Vcc 68 Vss 27 /WE 69 DQ24 28 DQM0 70 DQ25 29 DQM1 71 DQ26 30 /CS0 72 DQ27 31 NC 73 Vcc 32 Vss 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 Vss 37 A8 79 *CLK2 38 A10/AP 80 NC 39 BA1 81 NC 40 Vcc 82 SDA 41 Vcc 83 SCL 42 CLK0 84 Vcc * Please refer Block Diagram Transcend Information Inc. Pin No 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 3 Pin Name Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 *CB4 *CB5 Vss NC NC Vcc /CAS DQM4 DQM5 */CS1 /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc *CLK1 *A12 Pin No 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name Vss CKE0 */CS3 DQM6 DQM7 *A13 Vcc NC NC *CB6 *CB7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC *Vref *REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss *CLK3 NC SA0 SA1 SA2 Vcc 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C Block Diagram /CS0 /CS /CS DM0 DQ DQ DQ DQ DQ DQ DQ DQ 32 33 34 35 39 38 37 36 DM4 DQ 7 DQ 6 DQ 5 DQ 4 DQ 0 DQ 1 DQ 2 DQ 3 D M I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 40 DQ 41 DQ 42 DQ 43 DQ 47 DQ 46 DQ 45 DQ 44 D M I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D M DM5 D M I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQ 15 DQ 14 DQ 13 DQ 12 DQ 8 DQ 9 DQ 10 DQ 11 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DM1 U 1 U 3 /CS2 /CS DQ 51 DQ 50 DQ 49 DQ 48 DQ 52 DQ 53 DQ 54 DQ 55 D M I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM6 D M DM2 DQ 19 DQ 18 DQ 17 DQ 16 DQ 20 DQ 21 DQ 22 DQ 23 CK0/2 10 Ohms DQ DQ DQ DQ DQ DQ DQ DQ U 2 U2/U4 15pF DM7 D M DQ DQ DQ DQ DQ DQ DQ DQ I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 24 25 26 27 31 30 29 28 U 4 SCL 470 Ohms WP A0 A1 A2 SDA SA0 SA1 SA2 Every DQpin of SDRAM VDD 0.1 uF VSS 10 Ohms U1/U3 56 57 58 59 63 62 61 60 EEPROM U1 ~ U4 U1 ~ U4 U1 ~ U4 U1 ~ U4 U1 ~ U4 10 Ohms±5% D M I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM3 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0 ~A12 , BA0 & 1 /RAS /CAS /WE CKE0 DQn /CS CK1/3 10pF U1~U4 0.1 uF U1~U4 This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0~4.6 V Voltage on VDD supply to Vss VDD, VDDQ -1.0~4.6 V Storage temperature TSTG -55~+150 °C Power dissipation PD 16 W Short circuit current IOS 50 mA Operating Temperature TA 0 ~ 70 °C Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Note: Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDD+0.3 V Input low voltage VIL -0.3 0 0.8 V Output high voltage VOH 2.4 V Output low voltage VOL 0.4 V Input leakage current (Inputs) IIL -10 10 uA Note: Note 1 2 IOH=-2mA IOL=2mA 3 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD=.3V, TA = 23°C, f = 1MHz, VREF=1.4+ 200mV) Parameter Input capacitance (A0~A11, BA0~ BA1) Input capacitance (/RAS, /CAS, /WE) Input capacitance (CKE0) Input capacitance (CLK0, CLK2) Input capacitance (/CS0, /CS2) Input capacitance (DQM0~DQM7) Data input/output capacitance (DQ0~DQ63) Transcend Information Inc. Symbol Min Max Unit CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT 15 15 15 10 10 8 9 25 25 25 13 15 10 12 pF pF pF pF pF pF pF 5 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating Current (One Bank Active) Symbol Test Condition Value Unit Note ICC1 Burst Length =1 tRC≥tRC(min) IOL=0mA 400 mA 1 Precharge Standby Current ICC2P in power-down mode ICC2PS ICC2N Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) CKE≤VIL(max), tCC=10ns 8 CKE & CLK≤VIL(max), tCC=∞ 8 CKE≥VIH(min), /CS≥VIH(min), tCC=10ns 80 Input signals are changed one time during 30ns mA CKE≥VIH(min), CLK≤VIL(max), tCC=∞ 40 Input signals are stable ICC3P CKE≤VIL(max), tCC=10ns 20 ICC3PS CKE & CLK≤VIL(max), tCC=∞ 20 ICC3N CKE≥VIH(min), /CS≥VIH(min), tCC=10ns mA 120 Input signals are changed one time during 30ns mA ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞ 100 Input signals are stable Operating Current (Bust Mode) mA IOL= 0 mA Page Burst ICC4 560 mA 1 mA 2 tccD = 2CLKs Refresh Current ICC5 Self Refresh Current ICC6 tRC≥tRC(min) CKE≤0.2V Note: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing is CMOS (VIH/VIL=VDDQ/VSSQ) Transcend Information Inc. 6 800 C 8 L 3.2 mA 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf=1/1 ns 1.4 V AC Input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 Vtt=1.4V 3.3V 50 Ohm 1200 Ohm Output VOH (DC)=2.4V, IOH=-2mA VOL (DC)=0.4V, I OL=2mA Output Z0=50 Ohm 50pF 50pF 870 Ohm (Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay /RAS to /CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 - output data Value Unit Note 15 20 20 45 100 65 2 2CLK+tRP 1 1 1 2 ns ns ns ns us ns CLK CLK CLK CLK 1 1 1 1 ea - Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Transcend Information Inc. 7 1 2 2 2 3 4 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual component, not the whole module. Parameter Symbol Value Min Unit Note 1000 ns 1 5.4 ns 1, 2 Max CLK cycle time tCC CLK to valid output delay tSAC Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z tOH 3.0 ns 2 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 ns ns ns ns ns 3 3 3 3 2 CLK to output in Hi-Z Note: 7.5 tSHZ 5.4 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)= 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Transcend Information Inc. 8 ns 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn /CS /RAS (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) A11, /CAS /WE DQM BA0,1 A10/AP Note A0~A9 Register Mode Register Set H X L L L L X OP CODE 1,2 Refresh Auto Refresh Self Refresh H H L L L L H X X 3 3 L H H X H 3 3 X H X H X H H X L X Bank Active & Row Addr. L H L X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable H X L H L L X V Entry Exit Auto Precharge Enable Precharge Power Down Mode X X L L H L H H L L X X H L H X X X X Exit L H L X V X V X V X X Entry H L H X X X X L H H H H X X X L V V V H X X X X L H H H Exit DQM No Operation Command Note: L H H H X V X V X A0~A11, BA0~BA1: Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatically precharge without row precharge command is meant by “Auto”. Auto/self refresh can be issued only at both banks precharge state. 4. BA0~BA1: Bank select address. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected. If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) 9 X L H X Column Address (A0~A8) Column Address (A0~A8) 4 4, 5 4 4, 5 6 X X X 1. OP Code: Operand Code Transcend Information Inc. L H H H Bank Selection Both Banks Clock Suspend or Entry Active Power Down L H Auto Precharge Enable Burst Stop Precharge Row Address X X 7 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C Serial Presence Detect Specification Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function Described # of Bytes Written into Serial Memory Total # of Bytes of S.P.D Memory Fundamental Memory Type # of Row Addresses on this Assembly # of Column Addresses on this Assembly # of Module Banks on this Assembly Data Width of this Assembly Data Width Continuation Voltage Interface Standard of this Assembly SDRAM Cycle Time (highest CAS latency) SDRAM Access from Clock (highest CL) DIMM configuration type (non-parity, ECC) Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width Min Clock Delay Back to Back Random Address Burst Lengths Supported Number of banks on each SDRAM device CAS # Latency CS # Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 SDRAM Cycle Time (2nd highest CL) SDRAM Access from Clock (2nd highest CL) SDRAM Cycle Time (3rd highest CL) SDRAM Access from Clock (3rd highest CL) Minimum Row Precharge Time Minimum Row Active to Row Activate Minimum RAS to CAS Delay Minimum RAS Pulse Width Density of Each Bank on Module Command/Address Setup Time Command/Address Hold Time Data Signal Setup Time Data Signal Hold Time Superset Information SPD Data Revision Code Checksum for Bytes 0-62 Manufacturers JEDEC ID Code per JEP-108E Manufacturing Location Manufacturers Part Number 91-92 Revision Code Transcend Information Inc. 10 Standard Vendor Part Specification 128bytes 80 256bytes 08 SDRAM 04 A0~A11 0C A0~A8 09 1 bank 01 64bits 40 0 00 LVTTL3.3V 01 7.5ns 75 5.4ns 54 None 00 15.625us/Self Refresh 80 X16 10 None 00 1 clock 01 1,2,4,8 & Full page 8F 4 bank 04 3 04 0 clock 01 0 clock 01 Non Buffer 00 Prec All, Auto Prec, 0E R/W Burst 0 00 0 00 0 00 0 00 20ns 14 15ns 0F 20ns 14 45ns 2D 64MB 10 1.5ns 15 0.8ns 08 1.5ns 15 0.8ns 08 00 JEDEC 2 02 94 94 Transcend 7F, 4F T 54 TS8MLS64V6C 54 53 38 4D 4C 53 36 34 56 36 43 20 20 20 20 20 20 20 0 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V6C 93-94 95-98 99-125 126 127 128~ Manufacturing Date Assembly Serial Number Manufacturer Specific Data Intel Specification Frequency Intel Specification CAS# Latency/Clock Signal Support Unused Storage Locations Transcend Information Inc. 11 By Manufacturer By Manufacturer 100MHz CL=2 & 3 Clock=0,2 Open Variable Variable 0 64 C6 FF