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Processor Uncore Configuration Registers 4.2.12.30 RIRILV3OFFSET_3—RIR Range Rank Interleave 3 OFFSET Register RIRILV3OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 4.2.12.31 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 18Ch 18Ch 18Ch 18Ch Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT3 Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving). 15 RV 0h Reserved 14:2 RW-LB 0h RIR_OFFSET3 RIR[5:0].RANKOFFSET3[38:26] == rank interleave 3 offset, 64 MB granularity (processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8way interleave.) 1:0 RV 0h Reserved Description RIRILV4OFFSET_3—RIR Range Rank Interleave 4 OFFSET Register RIRILV4OFFSET_3 Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: Bus: 1 Device: 15 15 15 15 Function: Function: Function: Function: 2 3 4 5 Offset: Offset: Offset: Offset: 190h 190h 190h 190h Bit Attr Reset Value 31:20 RV 0h Reserved 19:16 RW-LB 0h RIR_RNK_TGT4 Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving). 15 RV 0h Reserved 14:2 RW-LB 0h RIR_OFFSET4 RIR[5:0].RANKOFFSET4[38:26] == rank interleave 4 offset, 64 MB granularity (processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8way interleave.) 1:0 RV 0h Reserved Datasheet, Volume 2 Description 395
