Download Intel Core 2760QM


Processor Uncore Configuration Registers
4.2.15.8
IOSAV_CH_DATA_CNTL—IOSAV Channel Data 
Control Register
This register controls the data flow. This register is read & write, but it is should
not be written while a sequence is active (doing this shall cause unpredictable results).
The RW-L field is locked by either NORMAL bit in MCMTR register or by IOSAV_DISABLE
bit in LT_IOSAV_MEMINIT_DIS register.
IOSAV_CH_DATA_CNTL
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
45Ch
45Ch
45Ch
45Ch
Bit
Attr
Reset
Value
31
RW-L
0b
DQ_LFSR_EN
1 = Data pattern is LFSR based
0 = Data pattern is from WDB
30:25
RV
0h
Reserved
23:16
RW-L
00h
CMPP
This pointer is used for reading from WDB data that is used for comparison on
read transactions.
15:8
RW-L
00h
WRP
This pointer is used for reading from WDB data that is used for write transactions.
00h
PAT_LEN
This field defines the length of the pattern in WDB in CL (8 * data transfers).
Actual pattern length is PAT_LEN + 1. PAT_LEN=n-1 means WDB entries 0 to n-1
are used for the IOSAV data pattern with pattern length of n. The effective range
of the PAT_LEN is {0..31}. A value greater than 31 is equivalent to truncated bit
4:0 value; that is, modulo of 32.
7:0
4.2.15.9
16
16
16
16
RW-L
Description
IOSAV_CH_DATA_CYC_MSK—IOSAV Channel Data Cycle 
Mask Register
This register controls the data flow. This register is read & write, but it is should
not be written while a sequence is active (doing this shall cause unpredictable results).
The RW-L field is locked by either the NORMAL bit in the MCMTR register or by
IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register.
IOSAV_CH_DATA_CYC_MSK
Bus: 1
Device: 16
Bus: 1
Device: 16
Bus: 1
Device: 16
Bus: 1
Device: 16
Bit
Attr
Reset
Value
31:11
RV
0h
10:8
RW-L
000b
7:0
RW-L
00h
Datasheet, Volume 2
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
460h
460h
460h
460h
Description
Reserved
MODE
Defines time-masking mode:
0h = No masking – check every cycle
1h = Mask all but one vector
2h = Mask all odd vectors, check all even vectors
3h = Mask all even vectors, check all odd vectors
The RW-L field is locked by either NORMAL bit in MCMTR register or by
IOSAV_DISABLE bit in LT_IOSAV_MEMINIT_DIS register.
ROW_ENABLE
This field defines the vector that is enabled if Mode is ’Mask all but one vector.
443