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Features
Table 7-17. Memory Device SMBus Addressing
Address
(Hex)
Upper
Address1
Device Select
R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
A2h/A3h
1010
0
0
1
X
A4h/A5h
1010
0
1
0
X
A6h/A7h
1010
0
1
1
X
A8h/A9h
1010
1
0
0
X
AAh/ABh
1010
1
0
1
X
ACh/ADh
1010
1
1
0
X
AEh/AFh
1010
1
1
1
X
NOTE:
1. This addressing scheme will support up to 8 processors on a single SMBus.
7.4.9
Managing Data in the PIROM
The PIROM consists of the following sections:
•
•
•
•
•
•
•
•
•
Header
Processor Data
Processor Core Data
Cache Data
Package Data
Part Number Data
Thermal Reference Data
Feature Data
Other Data
Details on each of these sections are described below.
Note:
7.4.9.1
Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not rely on this
model.
Header
To maintain backward compatibility, the Header defines the starting address for each subsequent
section of the PIROM. Software should check for the offset before reading data from a particular
section of the ROM.
Example: Code looking for the cache data of a processor would read offset 05h to find a value of
25h. 25h is the first address within the 'Cache Data' section of the PIROM.
Dual-Core Intel® Xeon® Processor 7000 Series Datasheet
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