Download Intel Pentium D 840

Electrical Specifications
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775_VR_CONFIG_05A and 775_VR_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD)
10.1 Design Guide For Desktop LGA775 Socket.
Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected
to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
These frequencies will operate properly in a system designed for 775_VR_CONFIG_05B processors. The power and ICC will be incrementally higher
in this configuration due to the improved loadline and resulting higher VCC.
ICC_MAX is based on the VCC Maximum loadline. Refer to Figure 2-1 and Figure 2-2 for details.
ICC_RESET is specified while PWRGOOD and RESET# are active.
The current specified is also for AutoHALT State.
ICC Stop-Grant and ICC Enhanced Halt are specified at VCC_MAX.
These parameters are based on design characterization and are not tested.
The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is
the same as the maximum ICC for the processor.
VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.
Baseboard bandwidth is limited to 20 MHz.
This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through
the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket to determine the total ITT drawn by the
system.
Table 2-4. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor
Voltage Deviation from VID Setting (V)1, 2, 3
Icc (A)
Maximum Voltage
1.30 mΩ
Typical Voltage
1.38 mΩ
Minimum Voltage
1.45 mΩ
0
0.000
-0.019
-0.038
5
-0.007
-0.026
-0.045
10
-0.013
-0.033
-0.053
15
-0.020
-0.040
-0.060
20
-0.026
-0.047
-0.067
25
-0.033
-0.053
-0.074
30
-0.039
-0.060
-0.082
35
-0.046
-0.067
-0.089
40
-0.052
-0.074
-0.096
45
-0.059
-0.081
-0.103
50
-0.065
-0.088
-0.111
55
-0.072
-0.095
-0.118
60
-0.078
-0.102
-0.125
65
-0.085
-0.108
-0.132
70
-0.091
-0.115
-0.140
75
-0.098
-0.122
-0.147
80
-0.101
-0.126
-0.151
85
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-0.111
-0.136
-0.161
90
-0.117
-0.143
-0.169
95
-0.124
-0.150
-0.176
100
-0.130
-0.157
-0.183
NOTES:
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Datasheet
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.5.3.
This table is intended to aid in reading discrete points on Figure 2-1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to
the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.
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