Download pro.point 10.8V Li-ION Specifications

LTC1760
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APPLICATIO S I FOR ATIO
A) Single Battery Configuration.
To limit the LTC1760 to a single battery, modify the battery
slot to be eliminated as follows:
5) Remove all components connected to COMP1, VSET,
ITH, ISET, ILIMIT and VLIMIT pins.
6) Short ILIMIT and VLIMIT to VSS.
1) Remove both FETs (Q5, Q6 or Q7, Q8) involved in the
charge path.
6) Remove R1, C1 but short CLP to DCIN. Replace RCL
with a short/trace connection.
2) Remove both FETS (Q3, Q4 or Q9, Q10) involved in
the discharge path.
7) Short CSP to CSN but leave the combination floating.
3) Remove the thermistor sensing resistors (R1A, R1B
or R2A, R2B).
4) Short the thermistor sense lines together at the IC.
5) Remove the diode (D2 or D3) as required.
6) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
8) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
F) No DC Path And No Charge Configuration.
To limit the LTC1760 to battery discharge functions only,
merge the previous two configurations with the following:
1) Remove CIN.
2) Remove resistors tied to DCDIV and ground DCDIV.
B) No Short-Circuit Protection Configuration.
1) Replace RSC with a short.
C) No LOPWR Protection.
1) Remove resistors R2 and R3 connected to LOPWR
and tie LOPWR to the VCC pin.
D) No DC Path Configuration.
To remove the DC input as part of the power path choices
to support the load:
1) Remove both FETs Q1 and Q2 involved in the DC
path.
2) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
E) No Charge Configuration.
To permanently disable the battery charger function:
1) Remove ALL FETs involved in the charge path (Q3,
Q4, Q9, Q10).
2) Remove switching FETs QTG, QBG, diode D1 and
inductor L1.
3) Remove diodes D2, D3, D4, capacitors C4, COUT and
Resistor R11 and RSENSE.
4) Reduce CIN capacitor to 0.1µF.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections. Shortest copper trace connections possible. These parts must
be on the same layer of copper. Vias must not be used to
make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a clean
FET drive. This includes IC supply pins that connect to the
switching FET source pins. The IC can be placed on the
opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of this
trace. Make the trace width the minimum amount needed
to support current—no copper fills or pours. Avoid running the connection using multiple layers in parallel.
Minimize capacitance from this node to any other trace or
plane.
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