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Signal Description
Table 2-4. SNC Signal List (Continued)
Signal
Type
Frequency
Description
®
Itanium 2 Processor Bus (continued)
DEP[15:0]#
I/O
AGTL+
400 MHz
Data Bus ECC
ECC coverage for 128 bits of data. SNC generates this ECC when
it drives data during the Data phase. SNC also checks ECC for
incoming data.
DRDY#
I/O
AGTL+
200 MHz
Data Ready
Indicates that data is valid on the data bus during any cycle
DRDY# is asserted. SNC asserts DRDY# for each valid data
transfer.
GSEQ#
O
AGTL+
200 MHz
Guaranteed Sequentially
SNC asserts this signal along with DEFER# to guarantee that the
chipset will maintain the order of writes.
HIT#
HITM#
I/O
AGTL+
I/O
AGTL+
200 MHz
200 MHz
Snoop Hit
SNC captures the value of HIT# for transactions that are deferred
and returns it using DHIT# during the Deferred Phase.
SNC asserts HIT# to initiate a HIT# or snoop stall for debug (HIT#
and HITM# asserted together). SNC does not drive HIT# during
normal operation.
Snoop Hit with Modified
SNC observes HITM# and when asserted drives TRDY# for
implicit writeback.
SNC asserts HITM# to initiate a snoop stall for debug (HIT# and
HITM# asserted together). SNC does not drive HITM# during
normal operation.
ID[9:0]#
O
AGTL+
200 MHz
Transaction Identifier
These are driven during the Deferred Phase and indicate the
transaction ID of the deferred transaction. On the second clock of
the deferred phase (IDS# +1), IDb[1:0]# carries the parity for the ID
signals. IDb[2]# renamed as DHIT# is asserted by SNC if the
snoop phase of the original transaction resulted in HIT#.
IDS#
O
AGTL+
200 MHz
Transaction Identifier Strobe
IDS# is asserted by SNC to indicate the first cycle of the deferred
phase.
INIT#
O
AGTL+
200 MHz
Initialization Signal
INIT# is asserted to initiate soft reset of the processors.
LOCK#
I
AGTL+
200 MHz
Bus Lock
Indicates atomicity of transactions. SNC will never assert LOCK#.
REQ[5:0]#
I/O
AGTL+
200 MHz
Request Command
Asserted during both clocks of the Request phase. During the first
clock, these signals carry enough information to initiate a snoop
request. In the second clock these signals carry additional
information to completely define the transaction type.
These are sampled and driven by SNC.
200 MHz
Request Command Parity
Parity protection on ADS# and REQ[5:0]# signals. RP# is driven by
SNC for its own transactions. RP# is also sampled by SNC to
check parity on the Request phase signals.
RS[2:0]#
O
AGTL+
200 MHz
Response Status
Indicates the types of response generated by SNC. Valid
responses are Hard Fail, Implicit Writeback, Normal, No Data,
Deferred and Retry.
RSP#
O
AGTL+
200 MHz
Response Status Parity
Parity protection on RS[2:0]#
SBSY#
I/O
AGTL+
RP#
I/O
AGTL+
200 MHz
Strobe Bus Busy
Indicates that Strobes are used by an agent. It is driven by an
agent transferring data when it owns the strobe bus.
SBSY# is driven and sampled by SNC.
2-10
Intel® E8870 Scalable Node Controller (SNC) Datasheet