Download Cypress Semiconductor ISR 37000 CPLD Specifications

Design Considerations for ISR Programming of Cypress CPLDs
10-kΩ resistor on the ISR* signal is required to keep the mux
input HIGH when the ISR cable is removed from the board to
keep the JTAGen input LOW. Remember that, if it is not necessary to use the dual-function pins in dual-function mode,
the mux can be removed and the JTAGen pin can be tied to
VCC or left connected to the JTAGen pin from the 10-pin connector.
ISR*
At this point the user should understand how to connect
FLASH370i and or Ultra37000 devices in an ISR chain and
how to bias the ISR interface for his programming and functional needs. There are some remaining minor functional differences between the two device families related to the placement of the bus-hold latches on the five JTAG interface pins,
which was addressed in the Device-Specific ISR Design Considerations section of this application note.
JTAGen
Ultra37000
Figure 23. JTAGen Incorrectly Driven by Ultra37000 I/O
ISR Programming
Cable Connector
JTAGen
ISRen
TDI
TDI
TDO
TDO
TCK
TCK
TMS
TMS
CY7C375i-125AC
vcc
ISR*
y
0
JTAGen
1
vcc
TDI
S
10 kΩ
Ultra37128P160
TDO
TCK
y
0
input1
TMS
1
S
JTAGen
TDI
Ultra37256P160
TDO
0
input2
S
TCK
y
TMS
1
Figure 24. Cascading Dual-Function Ultra37000 and FLASH370i Devices in the Same Chain
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