Download Watch-Dog DPN-8233 Product data
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UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog &$1$FWLYH >5HVHW256WDQGE\ 256OHHS25 1RUPDO&0& 25 &0& 9925 &0& 99957&@ W!WWRVLOHQFH 1RUPDO >&0& 99!25 &0& 99!957&@ 1RUPDO >&0& 99!25 &0& 99!957&@ 1RUPDO&0& >5HVHW256WDQGE\ 256OHHS25 1RUPDO&0& 25 &0& 9925 &0& 99957&@ WWWRVLOHQFH 1RUPDO >&0& 99!25 &0& 99!957&@ 1RUPDO&0& &$12IIOLQH%LDV WUDQVPLWWHURII UHFHLYHURII 5;'ZDNHXSLQW &$1+&$1/WHUPLQDWHG WR9IURP9%$7 WUDQVPLWWHURQ UHFHLYHURQ 5;'ELWVWUHDP &$1+&$1/WHUPLQDWHG WR9§9 1RUPDO &0& 99 &$1/LVWHQRQO\ WUDQVPLWWHURII UHFHLYHURQ 5;'ELWVWUHDP &$1+&$1/WHUPLQDWHG WR9IURP9%$7 >5HVHW256WDQGE\256OHHS25 1RUPDO&0& @ WWWRVLOHQFH IURPDOOPRGHV W!WWRVLOHQFH 1RUPDO&0& &$1EXVZDNHXS25 1RUPDO&0& 99 >5HVHW256WDQGE\256OHHS25 1RUPDO&0& @ W!WWRVLOHQFH 2II25 2YHUWHPS25 9%$79XYG&$1 &$12IIOLQH WUDQVPLWWHURII UHFHLYHURII 5;'ZDNHXSLQW &$1+&$1/WHUPLQDWHG WR*1' &$12II WUDQVPLWWHURII UHFHLYHURII 5;'ZDNHXSLQW &$1+&$1/IORDWLQJ OHDYLQJ2II2YHUWHPS 9%$7!9XYU&$1 DDD (1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND) Fig 5. CAN transceiver state machine (with FNMC = 0) 6.7.2 CAN standard wake-up If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), the UJA1167 will monitor the bus for a wake-up pattern. A filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be transmitted on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up filter and trigger a wake-up event (see Figure 6; note that additional pulses may occur between the recessive/dominant phases). The recessive and dominant phases must last at least twake(busrec) and twake(busdom), respectively. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 60