Download Archmeter PS1000 User guide

Arch Meter Corporation
PS1000
Ver1.2
XTLO
O
System Crystal output
SCLK
I/O
SPICS
SO
SI
O
O
I
SPI Clock input/output signal. The I/O selection depends on the SPI is
in master or slave mode. In the master mode, the maximum clock rate is
SYSCLK/4
SPI CS control signal, active low
SPI SO output
SPI SI input
FSX
DX
CLK
I/O
I/O
O
DR
FSR
O
O
SSP transmit frame sync signal
SSP transmit data signal
SSP CLK, the transmit and received clock. The maximum clock rate is
SYSCLK/4
SSP receive data signal
SSP receive frame sync signal
SCL
SDA
I/O
I/O
I2C clock
I2C Address/Data
VCM1
IBM
IBP
IAP
IAM
VAM
VAP
VCM2
O
I
I
I
I
I
I
O
Current Phase A/B ADC reference output(VCC3A/2)
Phase B Current input(-)
Phase B Current input(+)
Phase A Current input(+)
Phase A Current input(-)
Voltage input(-)
Voltage input(+)
Voltage ADC reference output(VCC3A/2)
VLCD
V1
V2
V3
COM3~0
SEG0~39
O
I
I
I
O
O
LCD bias power supply output
LCD bias input 1
LCD bias input 2
LCD bias input 3
LCD COM output (maximum driving current 200uA)
LCD Segment output (maximum driving current 20uA)
RST
EA
I
I
PSEN
ALE
MODE2-0
I/O
I/O
I
Chip Reset, active high
8051 MCU EA control signal
1: Internal ROM
0: External ROM
8051 PSEN control pin
8051 ALE control signal
Operation Mode selection
000 Normal Operation (1)
001 ICP Mode
010 External 51 Mode (1)
011 Normal Operation (2)
100 Memory Test Mode
101 External 51 Mode (2)
110 Analog Test Mode (Reserved)
111 Memory BIST Mode (Reserved)
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
I/O
I/O
I/O
I/O
I/O
I/O
PS1000Rev. 1.2 May 2006
8051 P0 I/O port bit 0 (mapped to the AD0)
8051 P0 I/O port bit 1 (mapped to the AD1)
8051 P0 I/O port bit 2 (mapped to the AD2)
8051 P0 I/O port bit 3 (mapped to the AD3)
8051 P0 I/O port bit 4 (mapped to the AD4)
8051 P0 I/O port bit 5 (mapped to the AD5)
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