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Writing Code for ROM
END
The code in Example 6-4 performs ROM/RAM remapping (if required), initializes stack pointers and interrupts for
each mode, and finally branches to __main in the C library (__main eventually calls main()). On reset, the ARM
core starts up in Supervisor (SVC) mode, in ARM state, with IRQ and FIQ disabled.
Example 6-4 init.s
AREA
Init, CODE, READONLY
; - Set up if ROM/RAM remapping required
;
GBLL ROM_RAM_REMAP
;ROM_RAM_REMAP
SETL {TRUE} ; change to {FALSE} if remapping not required
; - ensure no functions that use semihosting SWIs are linked from the C library
IMPORT __use_no_semihosting_swi
; - Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR
EQU
0x10
Mode_FIQ
EQU
0x11
Mode_IRQ
EQU
0x12
Mode_SVC
EQU
0x13
Mode_ABT
EQU
0x17
Mode_UNDEF
EQU
0x1B
Mode_SYS
EQU
0x1F ; available on ARM Arch v4 and later
I_Bit
EQU
0x80 ; when I bit is set, IRQ is disabled
F_Bit
EQU
0x40 ; when F bit is set, FIQ is disabled
; --- System memory locations
CM_ctl_reg
Remap_bit
EQU
EQU
0x1000000C
0x04
; Address of Core Module Control Register
; Bit 2 is remap bit of CM_ctl
; --- Amount of memory (in bytes) allocated for stacks
Len_FIQ_Stack
Len_IRQ_Stack
Len_ABT_Stack
Len_UND_Stack
Len_SVC_Stack
; Len_USR_Stack
EQU
EQU
EQU
EQU
EQU
EQU
0
256
0
0
1024
1024
; Add lengths >0 for FIQ_Stack, ABT_Stack, UNDEF_Stack if you need them
; offsets will be loaded as immediate values
; Offsets must be 8 byte aligned
Offset_FIQ_Stack
Offset_IRQ_Stack
Offset_ABT_Stack
Offset_UND_Stack
Offset_SVC_Stack
; Offset_USR_Stack
EQU
EQU
EQU
EQU
EQU
EQU
0
Offset_FIQ_Stack
Offset_IRQ_Stack
Offset_ABT_Stack
Offset_UND_Stack
Offset_SVC_Stack
+
+
+
+
+
Len_FIQ_Stack
Len_IRQ_Stack
Len_ABT_Stack
Len_UND_Stack
Len_SVC_Stack
ENTRY
; --- Perform ROM/RAM remapping, if required
IF :DEF: ROM_RAM_REMAP
; On reset, an aliased copy of ROM is at 0x0.
; Continue execution from 'real' ROM rather than aliased copy
LDR
pc, =Instruct_2
Instruct_2
; Remap by setting Remap bit of the CM_ctl register
LDR
r1, =CM_ctl_reg
LDR
r0, [r1]
ORR
r0, r0, #Remap_bit
STR
r0, [r1]
; RAM is now at 0x0.
; The exception vectors (in vectors.s) must be copied from ROM to the RAM
; The copying is done later by the C library code inside __main
ENDIF
Copyright ?1999 2001 ARM Limited
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