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Download Maxim DS33Z41 Specifications
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DS33Z41 Quad IMUX Ethernet Mapper 12 JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pinsL: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details about the Boundary Scan Architecture and the Test Access Port. Figure 12-1. JTAG Functional Block Diagram Boundary Scan Register Identification Register Mux Bypass Register Instruction Register Select Test Access Port Controller 10K 10K JTDI JTMS Tri-State 10K JTCLK JTRST 159 of 167 JTDO
