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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
13.9 AC Characteristics: Receive-Side
Table 13-14. AC Characteristics: Receive Side
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1, Figure 13-3, Figure 13-14, and Figure 13-15)
PARAMETER
RDCLKO Period
RDCLKO Pulse Width
RDCLKO Pulse Width
SYMBOL
CONDITIONS
MIN
TYP
MAX
488 (E1)
tLP
ns
648 (T1)
tLH
(Note 2)
200
0.5 tLP
tLL
(Note 2)
200
0.5 tLP
tLH
(Note 3)
150
0.5 tLP
tLL
(Note 3)
150
0.5 tLP
488 (E1)
648 (T1)
0.5 tCP
0.5 tCP
UNITS
ns
ns
ns
RDCLKI Period
tCP
RDCLKI Pulse Width
tCH
tCL
RSYSCLK Period
tSP
RSYSCLK Pulse Width
tSH
tSL
20
20
RSYNC Setup to RSYSCLK Falling
tSU
20
ns
RSYNC Pulse Width
tPW
50
ns
tSU
tHD
tR, tF
20
20
22
ns
ns
ns
tDD
50
ns
Delay RCLKO to RSERO, RDATA, RSIG
Valid
tD1
50
ns
Delay RCLKO to RCHCLK, RSYNC,
RCHBLK, RFSYNC
tD2
50
ns
Delay RSYSCLK to RSERO, RSIG Valid
tD3
22
ns
Delay RSYSCLK to RCHCLK, RCHBLK,
RMSYNC, RSYNC
tD4
22
ns
RPOSI/RNEGI Setup to RDCLKI Falling
RPOSI/RNEGI Hold from RDCLKI Falling
RSYSCLK, RDCLKI Rise and Fall Times
Delay RDCLKO to RPOSO, RNEGO
Valid
20
20
(Note 4)
648
(Note 5)
488
Note 1: Timing parameters in this table are guaranteed by design (GBD).
Note 2: Jitter attenuator enabled in the receive path.
Note 3: Jitter attenuator disabled or enabled in the transmit path.
Note 4: RSYSCLK = 1.544MHz.
Note 5: RSYSCLK = 2.048MHz.
327 of 344
ns
ns
ns
ns
0.5 tSP
0.5 tSP