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DatasheetDirect.com Your dedicated source for free downloadable datasheets. Over one million datasheets Optimized search function Rapid quote option Free unlimited downloads Visit www.datasheetdirect.com to get your free datasheets. This datasheet has been downloaded by http://www.datasheetdirect.com/ Intel® 815E Scalable Performance Board Development Kit Manual April 2001 Order Number: 273432-003 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® III processor and the 815e chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Other names and brands may be claimed as the property of others. Intel® 815E Scalable Performance Board Development Kit Manual Contents 1 About This Manual ..................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 2 Getting Started ..........................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 3 Content Overview.................................................................................................. 7 Text Conventions .................................................................................................. 7 Technical Support .................................................................................................9 1.3.1 Electronic Support Systems .................................................................9 Product Literature.................................................................................................. 9 Related Documents.............................................................................................10 Overview .............................................................................................................11 2.1.1 Baseboard Features ...........................................................................11 Included Hardware ..............................................................................................13 Software Key Features........................................................................................13 2.3.1 Embedded BIOS for the Intel® 815E Scalable Performance Board Development Kit ......................................................................14 2.3.2 Software .............................................................................................14 2.3.2.1 BlueCat* Linux ......................................................................14 2.3.2.2 Wind River’s VxWorks* Real-Time Operating System (RTOS) ....................................................................15 2.3.3 Information/Drivers CD.......................................................................17 Before You Begin ................................................................................................17 Setting up the Evaluation Board..........................................................................18 Configuring the BIOS ..........................................................................................20 Theory of Operation ................................................................................................21 3.1 3.2 3.3 3.4 Block Diagram .....................................................................................................21 Mechanical Design ..............................................................................................22 Thermal Management .........................................................................................22 System Operation................................................................................................22 3.4.1 Intel® Pentium® III Processor .............................................................22 3.4.2 Intel® Celeron™ Processor .................................................................23 3.4.3 Intel® 815E Chipset ............................................................................23 3.4.3.1 Graphics and Memory Controller Hub (GMCH)....................23 3.4.3.2 I/O Controller Hub (ICH2) .....................................................24 3.4.3.3 Firmware Hub (FWH)............................................................24 3.4.4 System Memory SDRAM ...................................................................25 3.4.5 Boot ROM...........................................................................................25 3.4.6 System I/O..........................................................................................25 3.4.6.1 Floppy Disk Drive Support ....................................................26 3.4.6.2 IDE Support ..........................................................................26 3.4.6.3 RS-232 Serial Ports ..............................................................26 3.4.6.4 IEEE 1284 Parallel Port ........................................................26 3.4.6.5 USB Ports .............................................................................26 3.4.6.6 VGA Connector.....................................................................26 3.4.6.7 Audio Subsystem..................................................................27 3.4.6.8 Game Port Connector...........................................................27 3.4.6.9 Keyboard/Mouse...................................................................27 Intel® 815E Scalable Performance Board Development Kit Manual 3 3.4.7 3.5 4 Hardware Reference ............................................................................................... 31 4.1 4.2 4.3 4.4 4.5 5 Thermal Management ......................................................................................... 31 Post Code Debugging ......................................................................................... 31 Connector Pinouts............................................................................................... 32 4.3.1 ATX Power Connector........................................................................ 34 4.3.2 Dual Stacked USB Connector ............................................................ 34 4.3.3 PS/2-Style Mouse and Keyboard Connectors.................................... 35 4.3.4 VGA Port ............................................................................................ 35 4.3.5 Parallel Port........................................................................................ 36 4.3.6 Serial Ports......................................................................................... 36 4.3.7 Audio Connectors............................................................................... 37 4.3.8 Wake On LAN (WOL)......................................................................... 38 4.3.9 Front Panel I/O Connectors................................................................ 38 4.3.10 IDE Connector.................................................................................... 38 4.3.11 Floppy Drive Connector...................................................................... 39 4.3.12 32-Bit PCI Slot Connector .................................................................. 40 4.3.13 4.5.11 AGP Connector ....................................................................... 41 4.3.14 CNR Connector .................................................................................. 43 Jumpers .............................................................................................................. 45 4.4.1 PN1 and PN2 Headers....................................................................... 45 4.4.1.1 Power LED (PN1: Pins 1—3) ............................................... 45 4.4.1.2 Keylock (PN1: Pins 4 and 5)................................................. 45 4.4.1.3 HDD-LED (PN1: Pins 7 and 8) ............................................. 45 4.4.1.4 Power (PN1: Pins 10 and 11) ............................................... 45 4.4.1.5 SMI (PN1: Pins 13 and 14) ................................................... 45 4.4.1.6 Reset (PN2: Pins 1 and 2) .................................................... 45 4.4.1.7 Speaker (PN2: Pins 4—7) .................................................... 45 4.4.1.8 SP_LED (PN2: Pins 9 and 10) ............................................. 45 4.4.1.9 Reserve (PN2: Pins 12—14) ................................................ 45 4.4.2 CMOS (JP1) ....................................................................................... 46 4.4.3 JP3 Header ........................................................................................ 46 4.4.4 CNR USB Settings (JP4 and USB2) .................................................. 46 4.4.5 AGP USB Settings (JP5 and USB2) .................................................. 47 Processor DIP Switch Settings (SW1) ................................................................ 47 BIOS Quick Reference ........................................................................................... 49 5.1 5.2 5.3 5.4 4 Expansion Connectors ....................................................................... 27 3.4.7.1 AGP Connector .................................................................... 27 3.4.7.2 32-bit/33-MHz PCI Connectors............................................. 28 3.4.7.3 CNR Connectors .................................................................. 28 3.4.7.4 V-Bus Connector .................................................................. 28 3.4.8 Post Code Debugger.......................................................................... 28 3.4.9 Clock Generation................................................................................ 28 3.4.9.1 System Clocks ...................................................................... 28 3.4.10 Power Supply Requirements.............................................................. 29 Battery Requirements ......................................................................................... 29 Overview ............................................................................................................. 49 Power-On Self-Test (POST) ............................................................................... 49 The BIOS User Interface..................................................................................... 49 Setup Screen System ......................................................................................... 52 Intel® 815E Scalable Performance Board Development Kit Manual 5.4.1 5.4.2 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 Basic CMOS Configuration Screen ....................................................52 Configuring Drive Assignments ..........................................................53 5.4.2.1 Configuring Floppy Drive Types ...........................................53 5.4.3 Configuring IDE Drive Types ..............................................................54 Configuring Boot Actions.....................................................................................55 Custom Configuration Setup Screen...................................................................55 Shadow Configuration Setup Screen ..................................................................56 Standard Diagnostics Routines Setup Screen ....................................................57 Start System BIOS Debugger Setup Screen.......................................................57 Start RS232 Manufacturing Link Setup Screen...................................................58 Manufacturing Mode............................................................................................58 5.11.1 Console Redirection ...........................................................................58 5.11.2 CE-Ready Windows CE Loader .........................................................59 5.11.3 Integrated BIOS Debugger .................................................................59 Embedded BIOS POST Codes ...........................................................................61 Embedded BIOS Beep Codes.............................................................................64 A Bill of Materials .........................................................................................................65 B Schematics .................................................................................................................77 Index ..............................................................................................................................111 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Block Diagram .....................................................................................................21 Back Panel I/O Connectors .................................................................................26 Baseboard Layout Diagram.................................................................................32 Baseboard Connector Orientation.......................................................................33 PN1, PN2 Diagram..............................................................................................46 BIOS POST Pre-Boot Environment.....................................................................50 Graphical POST ..................................................................................................51 Embedded BIOS Setup Screen Menu.................................................................52 Embedded BIOS Basic Setup Screen.................................................................53 Embedded BIOS Custom Setup Screen .............................................................56 Embedded BIOS Shadow Setup Screen.............................................................56 Standard Diagnostic Routines Setup Screen ......................................................57 Start RS232 Manufacturing Link Setup Screen...................................................58 CE-Ready Boot Feature ......................................................................................59 Integrated BIOS Debugger Running Over a Remote Terminal ...........................60 Intel® 815E Scalable Performance Board Development Kit Manual 5 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Related Documents............................................................................................. 10 Power Connector (ATXPR1) ............................................................................... 34 USB Connector Pinout (USB1) ........................................................................... 34 PS/2-Style Mouse and Keyboard Pinout (U1).................................................... 35 VGA Connector Pinout (VGA)............................................................................. 35 Parallel Port Connector Pinout (LPT1)................................................................ 36 Serial Port Connector Pinout (COM1 and COM2) .............................................. 36 Audio Line-Out Connector Pinouts...................................................................... 37 Audio Line-In Connector Pinouts ........................................................................ 37 Audio Mic-In Connector Pinouts.......................................................................... 37 MIDI/Game Port Connector Pinouts.................................................................... 37 Wake-ON-LAN Connector Pinouts (WOL1, not populated) ................................ 38 Front Panel I/O Connectors ................................................................................ 38 IDE Connector Pinouts for IDE1 and IDE2 ......................................................... 38 Floppy Drive Connector Pinouts (FDC1)............................................................. 39 32-Bit PCI Slot Connector Pinouts ...................................................................... 40 AGP Connector Pinouts ...................................................................................... 41 Pin Assignment for the Type A CNR Connector, using the 8-pin LAN Interface ...................................................................................................... 43 Pin Assignment for the Type B CNR Connector, using the 17-pin LAN Interface ...................................................................................................... 44 Processor DIP Switch Settings ........................................................................... 47 IDE0-IDE3 Drive Assignments ............................................................................ 54 Bill of Materials.................................................................................................... 65 Key Components Bill of Materials ....................................................................... 72 19 20 21 22 23 Revision History 6 Revision Date Description 003 4/01 Kits upgraded to ship with 850 MHz Celeron processor (replacing 566 MHz processor). Baseboard BOM format changes (NO part changes); key components BOM expanded to include all kit components (excluding documentation, mounting hardware, etc.). 002 1/01 minor corrections, typos fixed 001 10/00 First publication of this document. Intel® 815E Scalable Performance Board Development Kit Manual About This Manual 1 This manual tells you how to set up and use the evaluation board and processor assembly included in your Intel® 815E Scalable Performance Board Development Kit. 1.1 Content Overview Chapter 1, “About This Manual” — This chapter contains a description of conventions used in this manual. The last few sections tell you how to obtain literature and contact customer support. Chapter 2, “Getting Started”— Provides complete instructions on how to configure the evaluation board and processor assembly by setting jumpers, connecting peripherals, providing power, and configuring the BIOS. Chapter 3, “Theory of Operation” — This chapter provides information on the system design. Chapter 4, “Hardware Reference” — This chapter provides a description of jumper settings and functions, and pinout information for each connector. Chapter 5, “BIOS Quick Reference” — This chapter describes how to configure the BIOS for your system configuration. A summary of all BIOS menu options is provided. Appendix A, “Bill of Materials” — This appendix contains the bill of materials for the evaluation board. Appendix B, “Schematics” — This appendix contains schematics for selected connectors and subsystems for the evaluation board. 1.2 Text Conventions The following notations may be used throughout this manual. # The pound symbol (#) appended to a signal name indicates that the signal is active low. Variables Variables are shown in italics. Variables must be replaced with correct values. Instructions Instruction mnemonics are shown in uppercase. When you are programming, instructions are not case-sensitive. You may use either upper- or lowercase. Intel® 815E Scalable Performance Board Development Kit Manual 7 About This Manual Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FFH.) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.) Units of Measure The following abbreviations are used to represent units of measure: A Gbyte Kbyte KΩ mA Mbyte MHz ms mW ns pF W V µA µF µs µW Signal Names 8 amps, amperes gigabytes kilobytes kilo-ohms milliamps, milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps, microamperes microfarads microseconds microwatts Signal names are shown in uppercase. When several signals share a common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0). Intel® 815E Scalable Performance Board Development Kit Manual About This Manual 1.3 Technical Support 1.3.1 Electronic Support Systems Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it.Telephone Technical Support In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S. and Canada, please contact your local distributor. 1.4 1-800-628-8686 U.S. and Canada 916-356-7599 U.S. and Canada 916-356-6100 (fax) U.S. and Canada Product Literature You can order product literature from the following Intel literature centers. 1-800-548-4725 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) Intel® 815E Scalable Performance Board Development Kit Manual 9 About This Manual 1.5 Table 1. Related Documents Related Documents Document Title Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.0B GHz datasheet Order Number 245264 ® ® 244453 ® ® 273325 Intel Pentium III Processor Specification Update Intel Pentium III Processor Thermal Design Guide ® Intel Celeron™ Processor up to 850 MHz datasheet 243658 Intel® Celeron™ Processor Specification Update 243748 Intel® 815E Chipset Platform Design Guide 298234 ® Intel 815 Series Chipsets: 82815 Graphics Memory Controller Hub (GMCH) Datasheet 290688 Intel® 82801BA I/O Controller Hub 2 (ICH2) Datasheet 290687 ® 10 Intel 82802AB/82802AC Firmware Hub (FWH) 290658 Intel® 82802 Firmware Hub: Random Number Generator - Programmer’s Reference Manual 298029 Intel® 815 Chipset: Graphics Controller Programmer’s Reference Manual 298237 P6 Family of Processors Hardware Developer’s Manual 244001 Intel Architecture Software Developer’s Manual, Volume1: Basic Architecture 243190 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference Manual 243191 Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide 243192 Intel Processor Serial Number application note 245125 Intel® 815E Scalable Performance Board Development Kit Manual Getting Started 2 This chapter identifies the evaluation kit’s key components, features and specifications. It also tells you how to set up the board for operation. 2.1 Overview The evaluation board consists of a baseboard (with one Intel® Pentium® III processor populated), 815E chipset, and other system board components and peripheral connectors. Note: 2.1.1 The evaluation board is shipped as an open system allowing for maximum flexibility in changing hardware configuration and peripherals. Since the board is not in a protective chassis, take extra precaution when handling and operating the system. Baseboard Features Note: ABIT manufactured the Intel® 815E Scalable Performance Board in compliance with Rev. 0.93 of the Intel® 815E Chipset Platform Design Guidelines. The evaluation board features are summarized below: CPU • Supports both Intel® CeleronTM Processors (566 MHz and above) and Intel® Pentium® III processors (up to 1 GHz); both in the flip chip-pin grid array (FC-PGA) package. • Supports a 66, 100, or 133 MHz processor system bus (PSB). Intel 815E Chipset • • • • • 82815 Graphics and Memory Controller Hub (GMCH) 82801BA I/O Controller Hub 2 (ICH2) 82802AC Firmware Hub (FWH) Supports Ultra ATA 100/66/33 IDE protocol Supports AGP 2.0 including 4x AGP data transfers Memory Support • 100/133 MHz system memory interface • Three 168-pin DIMM sockets support SDRAM (3.3 V, non-ECC) modules • Supports 8-Mbyte to 512-Mbyte using 16 Mbit/64 Mbit/128 Mbit/256 Mbit technology Intel® 815E Scalable Performance Board Development Kit Manual 11 Getting Started Flash System BIOS ROM • General Software system BIOS Power Supply/Management • Standard ATX power supply connector • SMRAM space remapping to A0000H (128 Kbyte) • Optional Extended SMRAM space above 256 Mbyte, additional 512 Kbyte/1 Mbyte TSEG from top of memory, cacheable • Stop clock grant and halt special cycle translation from the host to the hub interface • APIC buffer management Accelerated Graphics Port (AGP) Support • AGP Interface Specification Rev 2.0 compliant • Backward compatible with the AGP 1.0 • Single AGP 1X, 2X, 4X, 3.3 V/1.5 V device support System I/O • • • • • • • • • • One floppy connector supporting up to 2.88 Mbytes, and three-mode floppy drives Two Ultra ATA 100/66/33 IDE connectors supporting up to four IDE devices Built-in standard/EPP/ECP parallel port connector Two built-in 16550 fast UART compatible serial port connectors Two built-in Universal Serial Bus (USB) connectors Built-in PS/2-style keyboard and PS/2 mouse (6-pin mini-DIN) connectors One built-in VGA connector Built-in audio connectors (Line-in, Line-out, MIC-in) with Yamaha Audio CODEC One built-in game port Built-in audio line-in headers (CD1, CD2, and AUX1) Peripheral Connectors • • • • Three PCI expansion slots One Communication Network Riser (CNR) slot One AGP slot ABIT V-Bus* connector accepts expansion card for video output capability (TV-Out) Miscellaneous Features • Micro ATX form factor • Two built-in SMBus headers • Built-In standard IrDA TX/RX header 12 Intel® 815E Scalable Performance Board Development Kit Manual Getting Started • • • • • 2.2 Built-in Wake On LAN (WOL) header Three built-in FAN power connectors (FAN1, FAN2 and FAN3) Power/Reset jumpers Jumper to select PSB speed (66, 100, or 133 MHz) Jumper to clear CMOS Included Hardware 2.3 • • • • • • • Evaluation board (baseboard) with battery • • • • 80-pin ATA/66 IDE cable for the hard disk drive Intel N82802AC8 Firmware Hub One 866 MHz Intel® Pentium® III Processor with a 133 MHz PSB One 850 MHz Intel® Celeron™ Processor with a 100 MHz PSB One fansink thermal solution One 128-Mbyte PC133 SDRAM (168-pin) Western Digital ATA66 hard disk drive pre-loaded with an evaluation copy of BlueCat* Linux from LynuxWorks* Comm port cable Floppy drive cable 82559 fast ethernet controller card Software Key Features The software in the kit was chosen to facilitate development of real-time applications based on the components used in the evaluation board. The software tools included in your kit are described in this section. Note: Software in the kit is provided free by the vendor and is only licensed for evaluation purposes. Refer to the documentation in your evaluation kit for further details on any terms and conditions that may be applicable to the granted licenses. Customers using the tools that work with Microsoft* products must license those products.Any targets created by those tools should also have appropriate licenses. Software included in the kit is subject to change. Refer to http://developer.intel.com/design/intarch/devkits for details on additional software from other third-party vendors. Intel® 815E Scalable Performance Board Development Kit Manual 13 Getting Started 2.3.1 Embedded BIOS for the Intel® 815E Scalable Performance Board Development Kit The Intel® 815E Scalable Performance Board Development Kit ships pre-installed with Embedded BIOS* pre-boot firmware from General Software. Embedded BIOS provides an industry-standard BIOS platform to run any standard operating system, including DOS*, Windows* NT, NT Embedded*, Windows 95/98, Windows CE, QNX*, VxWorks*, and Linux* among others. The Embedded BIOS Application Kit (available through General Software) includes complete source code, a reference manual, and a Windows-based expert system, BIOStart*, to enable easy and rapid configuration of customized firmware for your Intel* 815E Scalable Performance Board Development Kit. The following features of Embedded BIOS have been enabled in the Intel® 815E Scalable Performance Board Development Kit: • • • • • • • • • • • • • SDRAM detection, configuration, and initialization Intel® 815E chipset configuration Firmware Hub Post codes displayed to port 80H Two serial ports, one EPP/ECP parallel port PCI bus and device enumeration and configuration AGP configuration and initialization SMC LPC Super I/O programming Pentium® III processor microcode update Integrated debugger Burn-in diagnostics Console redirection Manufacturing mode 2.3.2 Software 2.3.2.1 BlueCat* Linux The drive comes pre-loaded with BlueCat Linux. Some of the features of the BlueCat Linux include: • A development environment and an operating system for embedded deployment that lets developers combine specialized, custom-developed software and hardware with off-the-shelf, third-party Linux applications. • Configuration to accurately match the requirements of embedded development from small devices to large-scale multi-processor systems. BlueCat Linux includes a royalty-free, open source Linux distribution, enhanced with LynuxWorks’ cross-development and embedding tools that improve quality and reduce development time. • Stabilization to ensure that a consistent development and deployment environment is available for the complete lifecycle of an embedded product 14 Intel® 815E Scalable Performance Board Development Kit Manual Getting Started • A selected subset of the standard Linux distribution tailored for embedded development and deployment, with LynuxWorks cross-development and embedding tools. Components are selected to ensure functionality, reliability, and maintainability, both on the host and target side. BlueCat Linux is configurable to meet varied requirements for kernel size, hardware configurations, boot method, and other embedded requirements. It uses the Red Hat Package Manager (RPM) to allow customized installations on the development system. 2.3.2.2 Wind River’s VxWorks* Real-Time Operating System (RTOS) wind microkernel • Efficient task management — Multitasking, unlimited number of tasks — Preemptive and round-robin scheduling — Fast, deterministic context switching — 256 priority levels • Fast, flexible intertask communications — Binary, counting and mutual exclusion semaphores with priority inheritance — Message queues — POSIX pipes, counting semaphores, message queues, signals and scheduling — Control sockets — Shared memory • • • • • • High scalability Incremental linking and loading of components Fast, efficient interrupt and exception handling Optimized floating-point support Dynamic memory management System clock and timing facilities Networking support • • • • • • • • • BSD 4.4 TCP/IP networking IP, IGMP, CIDR, TCP, UDP, ARP RIP v.1/v.2 Standard Berkeley sockets, zbufs (a.k.a., zero-copy sockets) SLIP, CSLIP, PPP BOOTP, DNS, DHCP, TFTP NFS, ONC RPC FTP, rlogin, rsh, telnet SNTP Intel® 815E Scalable Performance Board Development Kit Manual 15 Getting Started • WindNet SNMP v.1/v.2c with MIB compiler—optional • WindNet OSPF v.2—optional Fast, flexible I/O and local file system • • • • • • SCSI support MS-DOS compatible file system Raw disk file system TrueFFS flash file system—optional ISO 9660 CD-ROM file system PCMCIA support Target Development Features • Full ANSI C compliance and enhanced C++ features for exception handling and template support • • • • • • • • • • Extensive POSIX 1003.1, .1b compatibility Interactive C interpreter target shell Symbolic debugging and disassembly Powerful performance monitoring Extensive kernel, task and system information utilities Dynamic linking loader Libraries of over 1800 utility routines Flexible booting from ROM, local disk, or over the network Highly scalable design allows for a wide range of applications System-level debugging via Ethernet, serial line, ICE, or ROM emulator Supported VxWorks 5.x Targets • • • • • • • • • • • • 16 PowerPC 68K, CPU 32 ColdFire MCORE 80x86 and Pentium i960 ARM and StrongARM MIPS SH SPARC NEX V8xx M32 R/D Intel® 815E Scalable Performance Board Development Kit Manual Getting Started • RAD6000 • ST 20 • TriCore 2.3.3 Information/Drivers CD ABIT, the manufacturer of the baseboard, has provided a CD that contains drivers for the standard versions of the Windows operating systems (Windows 95/98/NT/2000). The CD includes drivers for on-board audio, on-board video and Intel® ATA/66. In addition, there are a few other utilities provided that may be useful. For updated drivers, refer to: http://developer.intel.com/design/chipsets/815e/index.htm 2.4 Before You Begin Before you set up and configure your evaluation board, you may want to gather some additional hardware and software. VGA Monitor: You can use any standard VGA or multi-resolution monitor. The setup instructions in this chapter assume that you are using a standard VGA monitor. Keyboard: You need a keyboard with a PS/2-style connector or adapter. Mouse: Optional. You can use a mouse with a PS/2-style connector or adapter. Hard Drives andFloppy Drives: You can connect up to four IDE drives and two floppy drives to the evaluation board. Two devices (master and slave) can be attached to each IDE connector. Only one hard drive is included in your kit, so you will need to provide the cables for any additional drives. You may have all these storage devices attached to the board at the same time. Video Adapter: You can use the integrated video adapter supplied with your kit, or you can choose to install a PCI or AGP video adapter. It is your responsibility to install the correct driver software for any video adapters other than the one provided. Check the BIOS for the proper video settings (AGP/onboard or PCI). Network Adapter: A network interface card is included in the evaluation kit. You may use a different network card other than the card included in the kit; you are responsible for installing the correct drivers for such a network card. The evaluation board supports all standard PCI-compatible network cards. You must supply a network cable to connect to the LAN connector or any other network card you chose to install. Power Supply: You must use a standard ATX power supply. Other Devices and Adapters: The evaluation board functions much like a standard desktop computer motherboard. Most PC compatible peripherals can be attached and configured to work with the evaluation board. For example, you may want to install a sound card or an AGP graphics card. Intel® 815E Scalable Performance Board Development Kit Manual 17 Getting Started 2.5 Setting up the Evaluation Board Once you have gathered the hardware described in section Section 2.4, follow the steps below to set up your evaluation board. This manual assumes you are familiar with the basic concepts involved with installing and configuring hardware for a personal computer system. Refer to Figure 3 on page 32 for locations of connectors, jumpers, etc.When installing drives/devices on the baseboard, refer to Figure 4 on page 33 for the correct orientation of the connecting cable. Note: The location of pin1 on the COM2 header is INCORRECT in the ABIT Brief Installation Guide ver. 1.00 (included on the ABIT drivers CD). It has been corrected in this manual. 1. Create a safe work environment. Make sure you are in a static-free environment before removing any components from their anti-static packaging. The evaluation board is susceptible to electrostatic discharge damage, and such damage may cause product failure or unpredictable operation. 2. Inspect the contents of your kit. Check for damage that may have occurred during shipment. Contact your sales representative if any items are missing or damaged. Caution: Note: Connecting the wrong cable or reversing the cable can damage the evaluation board and may damage the device being connected. Since the board is not in a protective chassis, use caution when connecting cables to this product. The evaluation board is a standard micro-ATX form factor. An ATX chassis may be used if a protected environment is desired. 3. Check the jumper settings. JP1 is used to clear the CMOS memory (pin 2 and 3). Make sure this jumper is set for normal operation (jumper pins 1 and 2). Refer to Section 4.4.2, “CMOS (JP1)” on page 46. 4. Check the dip switch settings. Make sure the board’s DIP switch is configured to the correct PSB. SW1 DIP switch settings are shown in Table 20 on page 47. 5. Make sure the following hardware is populated on your evaluation board: — One 866 MHz Intel® Pentium® III processor — One 128-Mbyte PC133 SDRAM DIMM (168-pin) — One fan (thermal solution) — One network interface card 6. Install the IDE hard disk drive included in your kit: The evaluation board supports Primary and Secondary IDE interfaces that can each host one or two devices (master/slave). When you are using multiple devices, such as a hard disk and a CD-ROM drive, make sure the hard disk drive has a jumper in the master position and the CDROM has a jumper in the slave position. When using a single IDE device with the evaluation board, ensure that the jumpers are set correctly for single drive operation. For jumper settings for different configurations, consult the drive’s documentation. — Connect the hard drive’s IDE cable connector to the IDE1 connector on the evaluation board. 18 Intel® 815E Scalable Performance Board Development Kit Manual Getting Started — Connect the other end of the cable to the hard disk drive. — Connect a power cable to the hard drive. Caution: Make sure the tracer on the ribbon cable is aligned with pin 1 on both the hard disk and the IDE connector header. Connecting the cable backwards can damage the evaluation board or the hard disk. 7. Connect any additional storage devices to the evaluation board. Note: The hard disk is already formatted and is pre-loaded with a customized target image of BlueCat Linux by LynuxWorks. 8. Connect a Floppy drive (optional). — Insert a floppy cable into FDC1 (be sure to orient pin 1 correctly). — Connect the other end of the ribbon cable to the floppy drive. — Connect a power cable to the floppy drive. 9. Connect the keyboard and mouse. Connect a PS/2-style mouse and keyboard (see Figure 3 on page 32 for connector locations). Note: U1 (on the baseboard) is a stacked PS/2 connector. The bottom connector is for the keyboard and the top is for the mouse. 10. Connect the Ethernet adapter provided in your kit (optional). 11. Connect the audio speakers (optional). For audio, connect the audio speakers to the on-board line out connector. 12. Connect the power supply. Connect an ATX power supply to the evaluation board. Make sure the power supply is not plugged into the wall (turned off). Insert the board connector of the power supply cord into the ATXPR1 power supply header on the evaluation board. After connecting the power supply board connector to the ATXPR1 header, plug the power supply cord into the wall. 13. Power up the board. Power and reset are implemented on the evaluation board through jumpers located on PN1 and PN2. Power Jumper: The power jumper consists of pins 10 and 11 on PN1. (See Figure 5 on page 46.) To power on the evaluation board, briefly short pins 10 and 11, then, release the short. (To power off, short pins 10 and 11 for about five seconds, until the power shuts off.) Reset Jumper: The reset jumper consists of pins 1 and 2 on PN2. (See Figure 5 on page 46.) To reset the evaluation board, short pins 1 and 2 until the board resets, and then release the short. Turn on the power to the monitor and evaluation board. Ensure that the fansink on the processor is operating. Intel® 815E Scalable Performance Board Development Kit Manual 19 Getting Started 2.6 Configuring the BIOS General Software’s BIOS is pre-loaded on the evaluation board. You will need to make changes to the BIOS to enable hard disks, floppy disks and other supported features. You can use the Setup program to modify BIOS settings and control the special features of the system. Setup options are configured through a menu-driven user interface. Chapter 5, “BIOS Quick Reference” contains a description of BIOS options. BIOS updates may periodically be posted to Intel’s Developers’ Web site at: http://developer.intel.com/design/intarch/devkits/ 20 Intel® 815E Scalable Performance Board Development Kit Manual 3 Theory of Operation 3.1 Block Diagram Figure 1. Block Diagram 370-Pin Socket Processor VRM Clock DATA CTRL ADDR Termination GTL Bus DATA CTRL ADDR AGP Connector 3 DIMM Modules GMCH Digital Video Out Device USB Port 1 USB Port 2 USB Port 3 USB Port 4 PCI ADDR/DATA USB PCI CONN 3 PCI CTRL ICH2 PCI CONN 2 UDMA/100 PCI CONN 1 IDE Primary IDE Secondary CNR Connector AC'97 Link Firmware Hub Audio Codec SIO Parallel Serial 2 Serial 1 Keyboard Mouse Game Port Floppy A8255-01 Intel® 815E Scalable Performance Board Development Kit Manual 21 Theory of Operation 3.2 Mechanical Design The evaluation board conforms to the micro-ATX form factor. For extra protection in a development environment, you may want to install the evaluation board in an ATX chassis. The evaluation board has three 32 bit/33 MHz PCI connectors, one AGP connector, one CNR connector, three SDRAM DIMM connectors, and one ABIT V-Bus connector. The system I/O connectors are in the rear of the board in the defined micro-ATX I/O window. 3.3 Thermal Management The objective of thermal management is to ensure that the temperature of each component is maintained within specified functional limits. The functional temperature limit is the range within which the electrical circuits can be expected to meet their specified performance requirements. Operation outside the functional limit can degrade system performance and cause reliability problems. The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor using metal clips. This thermal solution has been tested in an open air environment at room temperature and is sufficient for evaluation purposes. The designer must ensure that adequate thermal management is provided for any customer-derived designs. 3.4 System Operation The Intel® 815E Scalable Performance Board Development Kit is designed to support Intel® Celeron™ processors (566 MHz and above) and Intel® Pentium® III processors up to 1 GHz in the flip chip-grid array (FC-PGA) package. The 815E chipset includes the GMCH, ICH2, and the FWH. 3.4.1 Intel® Pentium® III Processor The Intel® Pentium® III processor is a member of the P6 family in the Intel® IA-32 processor line. Like the Intel® Pentium® II processor, the Intel® Pentium® III processor implements the Dynamic Execution microarchitecture — a unique combination of multiple branch prediction, data flow analysis, and speculative execution. Intel® Pentium® III processor features include the following: • • • • Dynamic Execution technology Includes Intel MMX media enhancement technology Intel streaming SIMD extensions Incorporates separate 16 Kbyte level-one caches (32 Kbytes total); one for instructions and one for data • 256 Kbytes integrated, full-speed level two cache with error correcting code (ECC) • 8-way level two cache associativity, which provides improved cache-hit rate on read/store operations • Double quad word-wide (256 bit) cache data bus, which provides extremely high throughput on read/store operations 22 Intel® 815E Scalable Performance Board Development Kit Manual Theory of Operation • Support for 66 MHz, 100 MHz and 133 MHz processor system bus frequencies • Intel® processor serial number 3.4.2 Intel® Celeron™ Processor The Intel® Celeron™ processor family delivers quality, reliability, and compatibility while offering good performance for today’s most widely-used applications. Intel® Celeron™ processor features include: • • • • Dynamic Execution technology Includes Intel MMX* media enhancement technology Intel streaming SIMD extensions Incorporates separate 16 Kbyte level-one caches (32 Kbytes total); one for instructions and one for data • Incorporates a 128 Kbyte unified, non-blocking, level-two cache that improves performance by reducing the average memory access time and providing fast access to recently used instructions and data • 66/100 MHz Intel® P6 micro-architecture’s multi-transaction system bus that supports multiple outstanding transactions to increase bandwidth availability • A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit formats specified in IEEE standard 754, as well as an 80-bit format • Parity-protected address/request and response system bus signals with a retry mechanism for high data integrity and reliability 3.4.3 Intel® 815E Chipset 3.4.3.1 Graphics and Memory Controller Hub (GMCH) The GMCH provides the processor interface (optimized for Intel® Pentium® III processors and Intel® Celeron™ processors), DRAM interface, hub interface and an AGP interface or internal graphics. It provides flexibility and scalability in graphics and memory subsystem performance. GMCH features: • • • • • 544 BGA package 66, 100, or 133 MHz Processor System Bus 32-bit host bus addressing Four deep in-order queue Processor support — Celeron™ processor (128 Kbytes) in 370-pin FC-PGA package — Pentium® III processor (256 Kbytes) in 370-pin FC-PGA package Intel® 815E Scalable Performance Board Development Kit Manual 23 Theory of Operation • System DRAM controller — Three DIMM slots — 100/133 MHz clock • Accelerated hub architecture • Digital video out port • AGP 1X/2X/4X port 3.4.3.2 I/O Controller Hub (ICH2) The Intel 82801BA I/O Controller Hub (ICH2) is a highly integrated multifunctional I/O controller hub that provides the interface to the PCI bus and integrates many of the functions needed in today’s PC platforms. The ICH2 communicates with the host controller over a dedicated hub interface. ICH2 Features: • • • • • • • • • • • • • • • • 3.4.3.3 PCI 2.2 with six PCI REQ/GNT pairs Eight PCI interrupts AC’97 2.1 with six channel audio support LPC interface Wake-On-LAN support System management 21 GPIO signals Interrupt controller 82C54-based timer ACPI compliant RTC 360 eBGA package Four IDE @ ATA 100 max Two USB 1.1 controllers providing four ports Enhanced SMBus with slave interface Integrated MAC Firmware Hub (FWH) The Firmware Hub (FWH) stores system BIOS and video BIOS, as well as an Intel® Random Number Generator (RNG). The Intel RNG provides truly random numbers to enable stronger encryption, digital signing and security protocols. The FWH is key to enabling future security and manageability infrastructures. FWH Features: • 32-pin PLCC package • 8-Mbit flash memory 24 Intel® 815E Scalable Performance Board Development Kit Manual Theory of Operation • • • • • 3.4.4 Symmetrically-blocked flash memory array (64 Kbyte) Pin and register-based block locking Integrated hardware RNG Single-byte read/write Five GPIs System Memory SDRAM Memory Features: • Three 168-pin SDRAM DIMM sockets • Supports 8 Mbyte to 512 Mbyte using 16 Mbit/64 Mbit/128 Mbit/256 Mbit technology • Supports 100/133 MHz system memory bus 3.4.5 Boot ROM The system boot ROM installed at U23 is the Intel® FWH, N82802AC8 device. The FWH is socketed and is addressable on the LPC bus off of the ICH2. 3.4.6 System I/O The evaluation board contains the following I/O devices. • • • • • • • • • • Single floppy controller support Primary and secondary IDE interface (supports four drives) Two serial ports One parallel port Two USB ports VGA connector AC’97 specification compliant audio Line Out, Line IN, and MIC IN connectors MIDI/game port PS/2-style keyboard and mouse ports Intel® 815E Scalable Performance Board Development Kit Manual 25 Theory of Operation Figure 2. Back Panel I/O Connectors LPT Port Connector Mouse Game Port USB Keyboard COM1 t VGA e Lin Ou n eI Lin C MI In A8332-01 3.4.6.1 Floppy Disk Drive Support One 34-pin floppy connector is provided on the evaluation board. 3.4.6.2 IDE Support The evaluation board supports both a primary and secondary IDE interface via two 40-pin IDE connectors. IDE1 is the primary interface and IDE2 is the secondary interface. 3.4.6.3 RS-232 Serial Ports The evaluation board provides one built-in serial port (COM1) and a header for an additional serial port (COM2). COM1 is attached to the back panel I/O connector. COM2 is a header that connects to a serial port cable to provide the additional serial port. 3.4.6.4 IEEE 1284 Parallel Port One 25-pin DSUB IEEE 1284 parallel port is provided (LPT1). 3.4.6.5 USB Ports The evaluation board provides two USB connectors (USB1). 3.4.6.6 VGA Connector This connector is a 15-pin DSUB female connector for output to a monitor. 26 Intel® 815E Scalable Performance Board Development Kit Manual Theory of Operation 3.4.6.7 Audio Subsystem The evaluation board has an integrated (on-board) AC’97 compliant subsystem. Audio Subsystem Features: • Line input (back panel) • Line output (back panel) • Microphone input (back panel) 3.4.6.8 Game Port Connector The game port connector is a standard 15-pin DSUB connector for attaching a joystick, game pad or other MIDI device. 3.4.6.9 Keyboard/Mouse The keyboard and mouse connectors (U1) are PS/2 style, 6-pin stacked miniature DSUB connectors. The top connector is for the mouse and the bottom connector is for the keyboard. 3.4.7 Expansion Connectors The evaluation board contains the following expansion connectors: • • • • 3.4.7.1 One AGP 4x slot Three PCI 32/33 slots One CNR slot One V-Bus connector AGP Connector AGP support is provided through the 82815 GMCH. One industry standard AGP connector (AGP1) is provided on the evaluation board. The AGP connector can accept a Graphics Performance Adapter (GPA) to enhance system graphics performance by providing dedicated display cache for internal graphics. AGP Features: • AGP 1X, 2X, and 4X transfer rates • Differential strobes for more accurate timing Dual mode buffers allow the use of 1.5 V and 3.3 V compliant devices. AGP add-in cards must comply with the Rev. 2.0 Accelerated Graphics Port Specification. Intel® 815E Scalable Performance Board Development Kit Manual 27 Theory of Operation 3.4.7.2 32-bit/33-MHz PCI Connectors Three industry standard 32-bit/33-MHz PCI connectors (PCI1, PCI2, and PCI3) are provided on the evaluation board. 3.4.7.3 CNR Connectors One CNR connector is included on the board. Intel® has not validated this feature. 3.4.7.4 V-Bus Connector A V-BUS TV-out adapter can be installed in this connector (VL1), which has general video output and S-Video out for display on a TV monitor. Intel has not validated this feature. Contact ABIT* for more information. 3.4.8 Post Code Debugger An on-board Post-Code Debugger is not implemented on the evaluation board. However, post code debugging can be accomplished through the use of a port 080H expansion card. 3.4.9 Clock Generation The clock synthesizer on the baseboard generates and distributes the clocks used by the entire system. 3.4.9.1 System Clocks The CK Intel® 815E Chipset: 3 DIMM Clock Synthesizer is the primary source of clock generation for most of the clocks on the baseboard. The following clock groups are found on the Intel® 815E Scalable Performance Board Development Kit: 28 CPU 66 MHz/100 MHz/133 MHz PCI 33 MHz SDRAM 100 MHz/133 MHz 3V66 66 MHz (3.3 V) USB 48 MHz DOT 48 MHz REF 14.31818 MHz APIC 33 MHz Intel® 815E Scalable Performance Board Development Kit Manual Theory of Operation 3.4.10 Power Supply Requirements The Intel® 815E Scalable Performance Board uses a standard ATX power supply. 3.5 Battery Requirements A type 2032, socketed, 3 V lithium coin cell battery is used on this evaluation board. The battery has a shelf life of greater than three years. Intel® 815E Scalable Performance Board Development Kit Manual 29 Hardware Reference 4 This section provides reference information on the hardware, including connector pinout information and jumper settings. 4.1 Thermal Management The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor using metal clips. This thermal solution has been tested in an open-air environment at room temperature and is sufficient for evaluation purposes. The designer must ensure that adequate thermal management is provided for any customer-derived designs. For additional thermal design information refer to the following documents: • Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.0B GHz Datasheet (order number 245264) • Intel® Pentium® III Processor Thermal Design Guide (order number 273325) • Intel® Celeron™ Processor up to 850 MHz datasheet (order number 243658) • Intel® Celeron™ Processor Thermal Design Guide (order number 273421) 4.2 Post Code Debugging The evaluation board does not have an on-board post code display. However, post code debugging can be accomplished through the use of a Port 080H expansion card. These cards are available from various vendors. One such vendor is PC Engines (www.pcengines.com). Intel® 815E Scalable Performance Board Development Kit Manual 31 Hardware Reference 4.3 Connector Pinouts Figure 3. Baseboard Layout Diagram Game Port Parallel Serial VGA Stacked USB1 CD1 CD2 Winbond W83627HF AUX1 Mouse/ Keyboard VL1 COM2 ATXPR1 AGP1 SMB2 IR1 FAN2 J3 CNRSLOT1 PCI1 PCI2 PCI3 FW82801 JP1 Panasonic CR2032 CCMOS SMB1 3V PGA370 WOL1 FAN1 DIMM3 FW82801 DIMM1 DIMM2 FWH SW1 IDE1 IDE2 FDC1 ICS JP5 J2 SP1 S1 JP4 PN1 FAN3 USB2 PN2 A8333-01 32 Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference Figure 4. Baseboard Connector Orientation Pin 1 CD1 CD2 Pin 1 Pin 1 AUX1 Pin 1 Pin 1 VL1 COM2 ATXPR1 SMB2 IR1 Pin 1 FAN2 Pin 1 J3 Pin 1 CCMOS SMB1 JP1 Pin 1 WOL1 FAN1 IDE1 JP5 Pin 1 IDE2 Pin 1 FDC1 J2 S1 JP4 USB2 FAN3 PN1 PN2 A8337-01 Intel® 815E Scalable Performance Board Development Kit Manual 33 Hardware Reference 4.3.1 ATX Power Connector Table 2 shows the signals assigned to the ATX style power connector. Table 2. 4.3.2 Power Connector (ATXPR1) Pin Name Function 1 3.3 V 3.3 V 2 3.3 V 3.3 V 3 GND Ground 4 +5V +5 V VCC 5 GND Ground 6 +5 V +5 V VCC 7 GND Ground 8 PWRGD Power Good 9 5VSB Standby 5 V 10 +12 V +12 V 11 3.3 V 3.3 V 12 -12 V -12 V 13 GND Ground 14 PS_ON# Soft-off control 15 GND Ground 16 GND Ground 17 GND Ground 18 -5 V -5 V 19 +5 V +5 V VCC 20 +5 V +5 V VCC Dual Stacked USB Connector Table 3 shows the signals assigned to the dual stacked USB connector (USB1). Table 3. USB Connector Pinout (USB1) Pin 1,5 34 Signal Name Power (fused) 2,6 USBP0# [USBP1#] 3,7 USBP0 [USBP1] 4,8 GND Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference 4.3.3 PS/2-Style Mouse and Keyboard Connectors Table 4 shows the signals assigned to the keyboard and mouse connector (U1). The mouse port is on the top and the keyboard port is on the bottom. Table 4. PS/2-Style Mouse and Keyboard Pinout (U1) Pin 4.3.4 Table 5. Signal Name 1 Data 2 No Connect 3 GND 4 +5 V (fused) 5 Clock 6 No Connect VGA Port VGA Connector Pinout (VGA) Pin Signal 1 RED 2 GREEN 3 BLUE 4 N/C 5 GND 6 ANALOG GND 7 ANALOG GND 8 ANALOG GND 9 N/C 10 GND 11 N/C 12 N/C 13 H SYNC 14 V SYNC 15 N/C Intel® 815E Scalable Performance Board Development Kit Manual 35 Hardware Reference 4.3.5 Parallel Port Table 6 shows the signals assigned to the parallel port connector (LPT1). Table 6. 4.3.6 Parallel Port Connector Pinout (LPT1) Pin Signal Name Pin Signal Name 1 Strobe# 14 Auto Feed# 2 Data Bit 0 15 Fault# 3 Data Bit 1 16 INIT# 4 Data Bit 2 17 SLC IN# 5 Data Bit 3 18 GND 6 Data Bit 4 19 GND 7 Data Bit 5 20 GND 8 Data Bit 6 21 GND 9 Data Bit 7 22 GND 10 ACK# 23 GND 11 Busy 24 GND 12 Paper end 25 GND 13 SLCT Serial Ports Table 7 shows the signals assigned to the serial port connectors (COM1 and COM2). COM1 is attached to the back panel I/O connector. COM2 is a serial COM port. If you have a serial port bracket, it can be connected to COM2 for one additional serial port. Table 7. Serial Port Connector Pinout (COM1 and COM2) Pin 36 Signal Name 1 DCD 2 Serial In (SIN) 3 Serial Out (SOUT) 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 RI Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference 4.3.7 Audio Connectors Refer to Figure 2 on page 26 for the connectors referenced in this section. Table 8 shows the signals assigned to the audio line-out connector. Table 8. Audio Line-Out Connector Pinouts Pin Signal Name Sleeve GND Tip Audio Left Out Ring Audio Right Out Table 9 shows the signals assigned to the audio line-in connector. Table 9. Audio Line-In Connector Pinouts Pin Signal Name Sleeve GND Tip Audio Left In Ring Audio Right In Table 10 shows the signal assigned to the audio mic-in connector. Table 10. Audio Mic-In Connector Pinouts Pin Signal Name Sleeve GND Tip Mono In Ring Mic bias voltage Table 11 shows the signals assigned to the MIDI/game port connector. Table 11. MIDI/Game Port Connector Pinouts Pin Signal Name Pin Signal Name 1 2 +5 V (fused) 9 +5 V (fused) GP4 10 GP6 3 GP0 11 GP2 4 GND 12 MIDI-OUTR 5 GND 13 GP3 6 GP1 14 GP7 7 GP5 15 MIDI-INR 8 +5 V (fused) 16 NC Intel® 815E Scalable Performance Board Development Kit Manual 37 Hardware Reference 4.3.8 Wake On LAN (WOL) Table 12 shows the signals assigned to the Wake-ON-LAN (WOL) connector (WOL1). Table 12. Wake-ON-LAN Connector Pinouts (WOL1, not populated) 4.3.9 Pin Signal Name 1 5 VSB 2 Ground 3 WOL Front Panel I/O Connectors Table 13 shows the signals assigned to the front panel I/O connectors (PN1 and PN2). Table 13. Front Panel I/O Connectors PN1 4.3.10 PN2 Pin Signal Name Pin Signal Name 1 Power LED 1 Reset 2 Power LED 2 Reset 3 Power LED 3 No Pin 4 Keylock 4 Speaker 5 Keylock 5 Speaker 6 No Pin 6 Speaker 7 HDD LED 7 Speaker 8 HDD LED 8 No Pin 9 No Pin 9 SP LED 10 Power ON 10 SP LED 11 Power ON 11 No Pin 12 No Pin 12 Reserve 13 SMI 13 Reserve 14 SMI 14 Reserve IDE Connector Table 14 shows the signals assigned to the IDE connectors (IDE1 and IDE2). Table 14. IDE Connector Pinouts for IDE1 and IDE2 (Sheet 1 of 2) 38 Pin Signal Name Pin Signal Name 1 Reset IDE 21 DRQ3 2 Ground 22 Ground 3 Host Data 7 23 I/O Write# Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference Table 14. IDE Connector Pinouts for IDE1 and IDE2 (Sheet 2 of 2) Pin 4.3.11 Signal Name Pin Signal Name 4 Host Data 8 24 Ground 5 Host Data 6 25 I/O Read# 6 Host Data 9 26 Ground 7 Host Data 5 27 IOCHRDY 8 Host Data 10 28 BALE 9 Host Data 4 29 DACK3# 10 Host Data 11 30 Ground 11 Host Data 3 31 IRQ14 12 Host Data 12 32 IOCS16# 13 Host Data 2 33 Addr1 14 Host Data 13 34 Ground 15 Host Data 1 35 Addr 0 16 Host Data 14 36 Addr 2 17 Host Data 0 37 Chip Select 0# 18 Host Data 15 38 Chip Select 1# 19 Ground 39 Activity 20 Key 40 Ground Floppy Drive Connector Table 15 shows the signals assigned to the floppy drive connector (FDC1). Table 15. Floppy Drive Connector Pinouts (FDC1) (Sheet 1 of 2) Pin Signal Name Pin Signal Name 1 Ground 2 FDHDIN 3 Ground 4 Reserved 5 Key 6 FDEDIN 7 Ground 8 Index 9 Ground 10 Motor Enable A# 11 Ground 12 Drive Select B# 13 Ground 14 Drive Select A# 15 Ground 16 Motor Enable B# 17 Ground 18 DIR# 19 Ground 20 STEP# 21 Ground 22 Write Data# 23 Ground 24 Write Gate# 25 Ground 26 Track 00# 27 Ground 28 Write Protect# Intel® 815E Scalable Performance Board Development Kit Manual 39 Hardware Reference Table 15. Floppy Drive Connector Pinouts (FDC1) (Sheet 2 of 2) Pin 4.3.12 Signal Name Pin Signal Name 29 Ground 30 Read Data# 31 Ground 32 Side 1 Select# 33 Ground 34 Diskette Change# 32-Bit PCI Slot Connector Table 16 shows the signals assigned to the 32-Bit PCI slot connectors (PCI1, PCI2, and PCI3). Table 16. 32-Bit PCI Slot Connector Pinouts (Sheet 1 of 2) Pin 40 Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 VCC B1 -12 V A32 AD16 B32 AD17 A2 + 12 V B2 GND A33 3.3 V B33 CBE2# A3 VCC B3 GND A34 FRAME# B34 GND A4 VCC B4 No Connect A35 GND B35 IRDY# A5 VCC B5 VCC A36 TRDY# B36 3.3 V A6 PIRQ1# B6 VCC A37 GND B37 DEVSEL# A7 PIRQ3# B7 PIRQ2# A38 STOP# B38 GND A8 VCC B8 PIRQ0 A39 3.3 V B39 LOCK# A9 No Connect B9 PRSNT1B # A40 SDONE B40 PERR# A10 VCC B10 No Connect A41 SBO# B41 3.3V A11 No Connect B11 PRSNT2B # A42 GND B42 SERR# A12 GND B12 GND A43 PAR B43 3.3 V A13 GND B13 GND A44 AD15 B44 CBE1# A45 3.3V B45 AD14 A14 No Connect B14 No Connect A15 RST# B15 GND A46 AD13 B46 GND A16 VCC B16 PCLK3 A47 AD11 B47 AD12 A17 GNT1# B17 GND A48 GND B48 AD10 A18 GND B18 REQ# A49 AD9 B49 GND A19 Reserved B19 VCC A50 KEY B50 KEY A20 AD30 B20 AD31 A51 KEY B51 KEY A21 3.3 V B21 AD29 A52 CBEO# B52 AD8 A22 AD28 B22 GND A53 3.3 V B53 AD7 A23 AD26 B23 AD27 A54 AD6 B54 3.3 V A24 GND B24 AD25 A55 AD4 B55 AD5 Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference Table 16. 32-Bit PCI Slot Connector Pinouts (Sheet 2 of 2) Pin A25 4.3.13 Signal Name AD24 Signal Name Pin B25 Signal Name Pin 3.3 V A56 Pin GND B56 Signal Name AD3 A26 IDSEL B26 CBE3# A57 AD2 B57 GND A27 3.3 V B27 AD23 A58 AD0 B58 AD1 A28 AD22 B28 GND A59 VCC B59 VCC A29 AD20 B29 AD21 A60 REQ64# B60 ACK64# A30 GND B30 AD19 A61 VCC B61 VCC A31 AD18 B31 3.3 V A62 VCC B62 VCC 4.5.11 AGP Connector Table 17 shows the signals assigned to the AGP connector (AGP1). Table 17. AGP Connector Pinouts (Sheet 1 of 2) Pin Signal Pin Signal 1 12 V OVRCNT# 34 3.3 Vddq 3.3 Vddq 2 TYPEDET# 5.0V 35 AD22 AD21 3 Reserved 5.0V 36 AD20 AD19 4 USB- USB+ 37 GND GND 5 GND GND 38 AD18 AD17 6 INTA# INTB# 39 AD16 C/BE2# 7 RST# CLK 40 3.3 Vddq 3.3 Vddq 8 GNT# REQ# 41 FRAME# IRDY# 9 3.3 VCC 3.3 VCC 42 Reserved 3.3 Vaux 10 ST1 ST0 43 GND GND 11 Reserved ST2 44 Reserved Reserved 12 PIPE# RBF# 45 3.3 VCC 3.3 VCC 13 GND GND 46 TRDY# DEVSEL# 14 Reserved Reserved 47 STOP# 3.3 Vddq 15 SBA1 SBA0 48 PME# PERR# 16 3.3 VCC 3.3 VCC 49 GND GND 17 SBA3 SBA2 50 PAR SERR# 18 Reserved SB_STB 51 AD15 C/BE1# 19 GND GND 52 3.3 Vddq 3.3 Vddq 20 SBA5 SBA4 53 AD13 AD14 21 SBA7 SBA6 54 AD11 AD12 22 KEY KEY 55 GND GND Intel® 815E Scalable Performance Board Development Kit Manual 41 Hardware Reference Table 17. AGP Connector Pinouts (Sheet 2 of 2) Pin Signal Pin Signal 23 KEY KEY 56 AD9 AD10 24 KEY KEY 57 C/BE0# AD8 25 KEY KEY 58 3.3 Vddq 3.3 Vddq 26 AD30 AD31 59 Reserved AD_STB0 27 AD28 AD29 60 AD6 AD7 28 3.3 VCC 3.3 VCC 61 GND GND 29 AD26 AD27 62 AD4 AD5 30 AD24 AD25 63 AD2 AD3 31 GND GND 64 3.3 Vddq 3.3 Vddq 32 Reserved AD_STB1 65 AD0 AD1 33 C/BE3# AD23 66 Reserved Reserved NOTES: 1. Reserved pins are only for future use by the AGP interface specification. 2. IDSEL# is not a pin on the AGP connector. AGP graphics components should connect the AD16 signal to the 3.3 V IDSEL# function internal to the component. 3. All 3.3 V cards leave the TYPEDET signal open. All 1.5 V cards tie this signal hard to ground. 42 Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference 4.3.14 CNR Connector Table 18 and Table 19 shows the signals assigned to the Type A and Type B CNR connectors (CNRSLOT1). Table 18. Pin Assignment for the Type A CNR Connector, using the 8-pin LAN Interface Pin Signal Name Signal Name Pin B1 RESERVED RESERVED A1 B2 RESERVED RESERVED A2 B3 RESERVED GND A3 B4 GND RESERVED A4 B5 RESERVED RESERVED A5 B6 RESERVED GND A6 B7 GND LAN_TXD2 A7 B8 LAN_TXD1 LAN_TXD0 A8 B9 LAN_RSTSYNC GND A9 B10 GND LAN_CLK A10 B11 LAN_RXD2 LAN_RXD1 A11 B12 LAN_RXD0 RESERVED A12 B13 GND USB+ A13 B14 RESERVED GND A14 B15 +5 Vdual USB- A15 B16 USB_OC# +12 V A16 B17 GND GND A17 B18 -12 V +3.3 Vdual A18 B19 +3.3VD +5VD A19 KEY B20 GND GND A20 B21 EE_DOUT EE_DIN A21 B22 EE_SHCLK EE_CS A22 B23 GND SMB_A1 A23 B24 SMB_A0 SMB_A2 A24 B25 SMB_SCL SMB_SDA A25 B26 CDC_DN_ENAB# AC97_RESET# A26 B27 GND RESERVED A27 B28 AC97_SYNC AC97_SDATA_IN1 A28 B29 AC97_SDATA_OUT AC97_SDATA_IN0 A29 B30 AC97_BITCLK GND A30 Intel® 815E Scalable Performance Board Development Kit Manual 43 Hardware Reference Table 19. Pin Assignment for the Type B CNR Connector, using the 17-pin LAN Interface Pin Signal Name Signal Name Pin B1 MII_MDIO MII_MDC A1 B2 MII_COL MII_CRS A2 B3 MII_TXC GND A3 B4 GND MII_RXDV A4 B5 MII_RXERR MII_RXC A5 B6 MII_TXD3 GND A6 B7 GND MII_TXD2 A7 B8 MII_TXD1 MII_TXD0 A8 B9 MII_TXEN GND A9 B10 GND RESERVED A10 B11 MII_RXD2 MII_RXD1 A11 B12 MII_RXD0 MII_RXD3 A12 B13 GND USB+ A13 B14 RESERVED GND A14 B15 +5Vdual USB- A15 B16 USB_OC# +12 V A16 B17 GND GND A17 B18 -12V +3.3Vdual A18 B19 +3.3 V +5VD A19 KEY 44 B20 GND GND A20 B21 EE_DOUT EE_DIN A21 B22 EE_SHCLK EE_CS A22 B23 GND SMB_A1 A23 B24 SMB_A0 SMB_A2 A24 B25 SMB_SCL SMB_SDA A25 B26 CDC_DN_ENAB# AC97_RESET# A26 B27 GND RESERVED A27 B28 AC97_SYNC AC97_SDATA_IN1 A28 B29 AC97_SDATA_OUT AC97_SDATA_IN0 A29 B30 AC97_BITCLK GND A30 Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference 4.4 Jumpers 4.4.1 PN1 and PN2 Headers These headers provide the signals to the LED, power/reset button and speaker that are usually connected to the chassis when the system is mounted in a chassis. 4.4.1.1 Power LED (PN1: Pins 1—3) An LED designed for the front panel of a chassis can be connected to these pins to show the poweron status. 4.4.1.2 Keylock (PN1: Pins 4 and 5) On these pins you can connect a physical lock designed for a chassis, which allows you to lock your chassis with a key, so that the system cannot be turned on. 4.4.1.3 HDD-LED (PN1: Pins 7 and 8) An LED can be attached to these pins. It shows hard disk drive activity. 4.4.1.4 Power (PN1: Pins 10 and 11) Power is implemented on the evaluation board by pins 10 and 11 located on PN1. To power-on the evaluation board, short pins 10 and 11 until the board powers on and then release the short. To turn off the board, hold the jumper on pins 10 and 11 for four seconds. 4.4.1.5 SMI (PN1: Pins 13 and 14) This is the hardware suspend header. Because power management is not supported on this system, these pins should remain open (unconnected). 4.4.1.6 Reset (PN2: Pins 1 and 2) Reset is implemented on the evaluation board by pins 1 and 2 located on PN2. To reset the evaluation board, short pins 1 and 2 until the board resets and then release the short. 4.4.1.7 Speaker (PN2: Pins 4—7) This is the header for connecting an internal PC speaker. 4.4.1.8 SP_LED (PN2: Pins 9 and 10) An LED may be connected here to show the suspend state status. Because power management is not supported on this system, these pins should remain open (unconnected). 4.4.1.9 Reserve (PN2: Pins 12—14) These pins are reserved. Do not use. Intel® 815E Scalable Performance Board Development Kit Manual 45 Hardware Reference Figure 5. PN1, PN2 Diagram 4.4.2 CMOS (JP1) JP1 controls the power to the battery backed-up CMOS memory. This CMOS memory stores system information required by the BIOS during startup. For normal operation, jumper pins 1 and 2. To clear the CMOS RAM, perform the following steps: 1. Shut down the system. 2. Disconnect the power supply (ATXPR1). 3. Remove jumper from pins 1 and 2. Short pins 2 and 3 (clear CMOS). 4. Wait 10 seconds. 5. Replace the jumper on pins 1 and 2 (normal operation). 6. Reconnect the power supply (ATXPR1). 7. Boot the system and enter the BIOS setup screen to reconfigure the system. 4.4.3 Short Pins 1 and 2 Normal Operation (default) Short Pins 2 and 3 Clear saved CMOS data JP3 Header A header that allows you to connect an additional thermistor to detect the temperature at a location on the board you select. 4.4.4 CNR USB Settings (JP4 and USB2) When using CNR’s USB, these are the settings for JP4 and USB2. • Place the jumpers across JP4 pin 3 with USB2 pin 5 • Place the jumpers across JP4 pin 4 shorted with USB2 pin 7 46 Intel® 815E Scalable Performance Board Development Kit Manual Hardware Reference JP5 1 2 3 4 5 2 4 6 8 10 1 3 5 7 9 1 2 3 4 5 USB2 JP4 4.4.5 AGP USB Settings (JP5 and USB2) When using AGP’s USB, these are the settings for JP5 and USB2. • Place the jumpers across JP5 pin 3 with USB2 pin 6 • Place the jumpers across JP5 pin 4 with USB2 pin 8 JP5 1 2 3 4 5 2 4 6 8 10 1 3 5 7 9 1 2 3 4 5 USB2 JP4 4.5 Processor DIP Switch Settings (SW1) Processor settings, including PSB frequency selection, are implemented on the board by a DIP Switch (SW1). Table 20. Processor DIP Switch Settings (Sheet 1 of 2) Switch On/Off Description 1:ON 2:ON Use CPU Default Frequency Setting 1:OFF 2:ON Reserved 1:OFF 2:OFF Use SW1: 3-4 Frequency Setting 1:ON 2:OFF Reserved 3:ON 4:ON 66 MHz 3:OFF 4:ON 100MHz 3:OFF 4:OFF 133 MHz 3:ON 4:OFF No Define ON Use CPU Frequency Strap in ICH2 Register OFF Force CPU Frequency Strap to Safe Mod (1111) ON No Reboot on 2nd Watchdog Timeout OFF Reboot on 2nd Watchdog Timeout Default Default 1-2 3-4 Default 5 Default 6 Default NOTE: If you want to use SW1: 3-4 to set CPU frequency, SW1: 1-2 must be set at off. Intel® 815E Scalable Performance Board Development Kit Manual 47 Hardware Reference Table 20. Processor DIP Switch Settings (Sheet 2 of 2) Switch On/Off Description Default ON Use Onboard Codec OFF Disable Onboard Codec Default -- Reserved Default Off 7 8 NOTE: If you want to use SW1: 3-4 to set CPU frequency, SW1: 1-2 must be set at off. 48 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference 5 The evaluation board is licensed with a single copy of Embedded BIOS and Embedded DOS software from General Software, Inc.1 This software is provided for demonstration purposes only and must be licensed directly from General Software, Inc. for integration with new designs. General Software may be reached at (800) 850-5755, on the Web at http://www.gensw.com, or via e-mail at [email protected]. BIOS updates may periodically be posted to the Intel Developers’ Web site at http:// developer.intel.com/. 5.1 Overview The system’s pre-boot environment is managed with an adaptation of Embedded BIOS from General Software. The pre-boot environment includes POST, Setup Screen System, Manufacturing Mode, Console Redirection, Windows CE Loader (CE Ready), and Integrated BIOS Debugger. A REFLASH tool is also available to update the BIOS image with new builds of Embedded BIOS that may be obtained from General Software. Before using the system, please read the following to properly configure CMOS settings, and learn how to use the embedded features of the pre-boot firmware, Embedded BIOS. The last two sections of this chapter provide the BIOS POST Codes and Beep codes. 5.2 Power-On Self-Test (POST) When the system is powered on, Embedded BIOS tests and initializes the hardware and programs the chipset and other peripheral components. During this time, POST progress codes are written by the system BIOS to I/O port 80H, allowing the user to monitor the progress with a special monitor. “Embedded BIOS POST Codes” on page 61 lists the POST codes and their meanings. During early POST, no video is available to display error messages if a critical error is encountered; therefore, POST uses beeps on the speaker to indicate the failure of a critical system component during this time. Consult “Embedded BIOS Beep Codes” on page 64 for a list of beep codes used by the system’s BIOS. 5.3 The BIOS User Interface The system BIOS can use the standard keyboard and video device, or use console redirection to demonstrate headless operation. For headless operation, remove the standard keyboard and screen devices and the system will boot unattended. If an RS232 cable is attached to COM1, a PC/ATstyle character-based POST is available from HyperTerminal, PROCOMM, or any other terminal emulator software that supports VT100 emulation. 1. General Software™, the GS Logo, Embedded BIOS™, BIOStart™, CE-Ready™, and Embedded DOS™ are trademarks or registered trademarks of General Software, Inc. Intel® 815E Scalable Performance Board Development Kit Manual 49 BIOS Quick Reference When a keyboard and video device are attached, the system can display either a traditional character-based PC BIOS display with memory count-up, or it can display a graphical POST with splash screen and progress icons. Both POST screens accept a <DEL> key-press to enter the setup screen, and both display boot-time progress activity. The graphical display shows the status of file system devices and even OEM-defined devices (when the OEM adapts the BIOS to a particular OEM platform), but omits character-based PCI resource display. The text-based POST displays the memory count-up and the PCI resource assignment table. Figure 6 shows the format of the text-based POST display. The display is very similar if console redirection through a COM port is used instead. Figure 6. BIOS POST Pre-Boot Environment Figure 7 shows the graphical version of POST. The BIOS decompresses the main image and can display multiple overlaid graphics at various points in POST. The OEM can define the entire sequence and control the timing of the system for an embedded application, and can arrange to have different graphics displayed on each successive boot of the system. This feature is ideal for embedded systems that must show evidence of operation during startup, while the application loads underneath the splash screen. Once the application begins writing to the screen, the splash screen relinquishes control, providing a seamless graphical progression for the end user. 50 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference Figure 7. Graphical POST When the system is powered on for the first time, you’ll need to configure the system through the Setup Screen System (described later) before peripherals, such as disk drives, are recognized by the BIOS. The information is written to battery-backed CMOS RAM on the board’s real time clock. Should the board’s battery fail, this information will be lost and the board will need to be reconfigured. The Basic Setup Screen provides an option to disable the graphical POST and switch to the legacy text-based version. This feature may not permanently disable the graphical POST if the BIOS adaptation calls for reverting to the graphical form after so many boots. If you find that the graphical POST comes back after several boots, it is because this option is enabled for this platform. The OEM can use the Embedded BIOS Adaptation Kit to control whether setup can be used to dictate the policy, and whether it is permanent or temporary. Intel® 815E Scalable Performance Board Development Kit Manual 51 BIOS Quick Reference 5.4 Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be invoked from POST by pressing the <DEL> key if the main keyboard is being used, or by pressing Ctrl+C if the console is being redirected to a terminal program. Figure 8. Embedded BIOS Setup Screen Menu Once in the Setup Screen System (Figure 8), the user can navigate with the UP and DOWN arrow keys from the main console, or use the Ctrl+E and Ctrl+X keys from the remote terminal program to accomplish the same thing. TAB and ENTER are used to advance to the next field, and ‘+’ and ‘’ keys cycle through values, such as those in the Basic Setup Screen, or the Diagnostics Setup Screen. 5.4.1 Basic CMOS Configuration Screen The system’s drive types, boot activities, and POST optimizations are configured from the Basic Setup Screen (Figure 9). In order to use disk drives with your system, you must select appropriate assignments of drive types in the left-hand column. Then, if you are using true floppy and IDE drives (not memory disks that emulate these drives), you need to configure the drive types themselves in the Floppy Drive Types and IDE Drive Geometry sections. Finally, you’ll need to configure the boot sequence in the middle of the screen. Once these selections have been made, your system is ready to use. 52 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference Figure 9. Embedded BIOS Basic Setup Screen 5.4.2 Configuring Drive Assignments Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and Ide3), and memory disks when configured (Flash0, ROM0, RAM0, etc.). Figure 9 shows how the first floppy drive (Floppy0) is assigned to drive A: in the system, and then how the first IDE drive (Ide0) is assigned to drive C: in the system. To switch two floppy or two hard disks around, map Floppy0 to B: and Floppy1 to A:, and for hard disks map Ide0 to D: and Ide1 to C:. Caution: Take care to not skip drive A: when making floppy disk assignments, as well as drive C: when making hard disk assignments. The first floppy should be A:, and the first hard drive should be C:. Also, do not assign the same file system to more than one drive letter. Thus, Floppy0 should not be used for both A: and B:. The BIOS permits this to allow embedded devices to alias drives, but desktop operating systems may not be able to maintain cache coherency with such a mapping in place. A special field in this section entitled “Boot Method: (Windows CE/Boot Sector)” is used to configure the CE Ready feature of the BIOS. For normal booting (DOS, Windows NT, etc.), select “Boot Sector” or “Unused”. 5.4.2.1 Configuring Floppy Drive Types If true floppy drive file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the floppy drives themselves must be configured in this section. Floppy0 refers to the first floppy disk drive on the drive ribbon cable (normally drive A:), and Floppy1 refers to the second drive (drive B:). Intel® 815E Scalable Performance Board Development Kit Manual 53 BIOS Quick Reference 5.4.3 Configuring IDE Drive Types If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the IDE drives themselves must be configured in this section. The following table shows the drive assignments for Ide0-Ide3: Table 21. IDE0-IDE3 Drive Assignments File System Name Controller Master/Slave Ide0 Primary (1f0h) Master Ide1 Primary (1f0h) Slave Ide2 Secondary (170h) Master Ide3 Secondary (170h) Slave To use the primary master IDE drive in your system (the typical case), configure Ide0 in this section, and map Ide0 to drive C: in the Configuring Drive Assignments section. The IDE Drive Types section lets you select the type for each of the four IDE drives: None, User, Physical, LBA, or CHS. 54 User This type allows the user to select the maximum cylinders, heads, and sectors per track associated with the IDE drive. This method is now rarely used since LBA is in common use. Physical This type instructs the BIOS to query the drive’s geometry from the controller on each POST. No translation on the drive’s geometry is performed, so this type is limited to drives of 512 Mbytes or less. Commonly, this is used with embedded ATA PC Cards. LBA This type instructs the BIOS to query the drive’s geometry from the controller on each POST, but then translate the geometry according to the industrystandard LBA convention. This supports up to 16-Gbyte drives. Use this method for all new drives. CHS This type instructs the BIOS to query the drive’s geometry from the controller on each POST, but then translates the geometry according to the Phoenix CHS convention. Using this type on a drive previously formatted with LBA or physical geometry might show data as being missing or corrupted. Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference 5.5 Configuring Boot Actions Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the entire system has been initialized, POST executes these steps in order until an operating system successfully loads. In addition, other pre-boot features can be run before, after, or between operating system load attempts. The following actions can be used: 5.6 Drive A: - K: Boot operating system from specified drive. If “Loader” is set to “BootRecord” or “Unused”, then the standard boot record will be invoked, causing DOS, Windows 95/98, Windows NT, or other industry-standard operating systems to load. If “Boot Method” is set to “Windows CE”, then the boot drive’s boot record will not be used, and instead the BIOS will attempt to load and execute the Windows CE Kernel file, NK.BIN, from the root directory of each boot device. Debugger Launch the Integrated BIOS Debugger. To return to the boot process from the debugger environment, type “G” at the debugger prompt and press ENTER. MFGMODE Initiate Manufacturing Mode, allowing the system to be configured remotely via an RS232 connect to a host computer. WindowsCE Execute a ROM-resident copy of Windows CE, if available. This feature is not applicable unless properly configured by the OEM in the BIOS adaptation. DOS in ROM Execute a ROM-resident copy of DOS, if available. This feature is not applicable unless an XIP copy of DOS, such as Embedded DOS-ROM, has been stored in the BIOS boot ROM. Copies of Embedded DOS-ROM may be obtained from General Software. None No action; POST proceeds to the next activity in the sequence. Custom Configuration Setup Screen The system’s hardware-specific features are configured with the Custom Setup Screen (Figure 10). All features are straightforward except for the Redirect Debugger I/O option, which is an extra embedded feature that allows the user to select whether the Integrated BIOS Debugger should use standard keyboard and video or RS232 console redirection for interaction with the user. If no video is available, the debugger is always redirected. Intel® 815E Scalable Performance Board Development Kit Manual 55 BIOS Quick Reference Figure 10. Embedded BIOS Custom Setup Screen 5.7 Shadow Configuration Setup Screen The system’s Shadow Configuration Setup Screen (Figure 11) allows the selective enabling and disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM, which is shadowed as a unit. Normally, shadowing should be enabled at C000/C400 (to enhance VGA ROM BIOS performance), and then E000-F000 should be shadowed to maximize system ROM BIOS performance. Figure 11. Embedded BIOS Shadow Setup Screen 56 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference 5.8 Standard Diagnostics Routines Setup Screen Embedded systems may require automated burn-in testing in the development cycle. This facility is provided directly in the system BIOS through the Standard Diagnostics Routines Setup Screen (Figure 12). To use the system, selectively enable or disable features to be tested, and then enable the “Tests Begin on ESC?” option to cause the system test suite to be invoked. To repeat the system test battery continuously, you should also enable the “Continuous Testing” option. When continuous testing is started, the system will continue until an error is encountered. Caution: The disk I/O diagnostics perform write operations on those drives; therefore, only spare drives should be used that do not contain data that could be harmed by the test. Caution: The keyboard test may fail when the hardware is operating within reasonable limits. This is because although the device may produce occasional errors, the BIOS retries operations when failures occur during normal operation of the system. Figure 12. Standard Diagnostic Routines Setup Screen 5.9 Start System BIOS Debugger Setup Screen The Embedded BIOS Integrated Debugger may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, the debugger will display the debugger prompt: EB43DBG: and await debugger commands. To return back to the Setup Screen main menu, type the following command, which instructs the debugger to “go”: EB43DBG: G <ENTER> Intel® 815E Scalable Performance Board Development Kit Manual 57 BIOS Quick Reference 5.10 Start RS232 Manufacturing Link Setup Screen The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the console of the system (Figure 13). The host can resume operation of the system and give control back to the system Setup Screen system with special control software. Figure 13. Start RS232 Manufacturing Link Setup Screen 5.11 Manufacturing Mode The system’s BIOS provides a special mode, called Manufacturing Mode, that allows the target to be controlled by a host computer such as a laptop or desktop PC. Running special software supplied by General Software, the host can access the target’s drives and manage the file systems on the target, reprogram flash memories, and test target hardware. A full discussion of the uses of Manufacturing Mode is beyond the scope of this chapter. Complete documentation and host-side software is available directly from General Software. For more information, visit the General Software Web site at http://www.gensw.com. 5.11.1 Console Redirection The system can operate either with a standard PC/AT or PS/2 keyboard and VGA video monitor, or with a special emulation of a console over an RS232 cable connected to a host computer running a terminal program. To see an example session with HYPERTERMINAL, see the debugger section’s screen display (Figure 15). To use the Console Redirection feature, remove the video display card from the system so that no video ROM is available for the BIOS to detect. In the absence of any video support, the BIOS automatically switches its keyboard and screen functions to serial I/O over COM1 on the board. The hardware connection to the host computer requires a null modem cable. 58 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference The software on the target can be any terminal emulation program that supports ANSI terminal mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The program must be set to not use flow control, or the console may seem to stall or not accept input. Caution: 5.11.2 HYPERTERMINAL’s default setting is to use flow control, which will render the console inoperative. To change this, create a new session, change the flow control setting to “none”, save the session, and exit HYPERTERMINAL. Then reinvoke HYPERTERMINAL with the session and it will operate with the new flow control setting. CE-Ready Windows CE Loader Your system’s BIOS is CE-ready and can directly boot Windows CE without loading an intermediate operating system such as DOS and LOADCEPC. Instead, the NK.BIN file can be placed on a disk drive or drive emulator, and then the BIOS can be configured through the Basic CMOS Configuration Setup Screen to boot the NK.BIN file from the boot drives instead of the boot records on those drives. To configure your system to boot Windows CE natively from a disk drive, set the “Boot Method” field to “Windows CE” in the Basic CMOS Configuration Setup Screen. Then, place a copy of NK.BIN suitable for execution by LOADCEPC in the root directory of your normal boot drive, such as drive C:. Then, reboot the system. The configuration box should be displayed (Figure 14), and immediately following should be the message “Loading Windows CE…” followed by a series of dots, indicating that the loading process is continuing. Once fully loaded, Windows CE takes over the system and runs using the standard PC keyboard, screen, and PS/2 mouse. Figure 14. CE-Ready Boot Feature 5.11.3 Integrated BIOS Debugger The system’s BIOS contains a built-in debugger that can be a valuable tool to aid the board bringup process on new designs similar to the evaluation board. It supports a DOS SYMDEB-style command line interface, and can be used on the main console’s keyboard and screen, or over a redirected connection to a terminal program (see “Console Redirection” on page 58). Intel® 815E Scalable Performance Board Development Kit Manual 59 BIOS Quick Reference To activate the debugger at any time from the main console, press the left shift and the control keys together. A display similar to the one in the HYPERTERMINAL session below (Figure 15) will appear, containing the title, “Embedded BIOS Debugger Breakpoint Trap” and a snapshot of the processor general registers. Figure 15. Integrated BIOS Debugger Running Over a Remote Terminal To leave the debugger and resume the interrupted activity (whether POST, BIOS, DOS, Windows, or an application program), enter the “G” command (short for “go”) and press ENTER. If you were at a DOS prompt when you entered the debugger, then DOS will still be waiting for its command, and will not prompt again until you press ENTER again. The debugger can also be entered from the Setup Screen System, and as a boot activity (see “Basic CMOS Configuration Screen” on page 52), as a last ditch effort during board bring-up and development if no bootable device is available. If your version of DOS, an application, or any OEM-supplied BIOS extensions have debugging code (i.e., “INT 3” instructions) remaining, then these will invoke the debugger automatically, although this is not an error. To continue, use the “G” command. When Embedded BIOS is adapted by the OEM, the debugger can be removed from the final production BIOS, and superfluous debugging code in the application will not cause the debugger to be invoked. 60 Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference A complete discussion of the debugger is beyond the scope of this chapter; however, complete documentation is available from General Software via the Web at http://www.gensw.com. 5.12 Embedded BIOS POST Codes Embedded BIOS writes progress codes, also known as POST codes, to I/O port 80H during POST, in order to provide information to OEM developers about system faults. These POST codes may be monitored on the on-board Post Code Debugger located at U12 and U13. They are not displayed on the screen. For more information about POST codes, contact General Software. Mnemonic Code POST_STATUS_START00h POST_STATUS_CPUTEST POST_STATUS_DELAY POST_STATUS_DELAYDONE POST_STATUS_KBDBATRDY POST_STATUS_DISABSHADOW POST_STATUS_CALCCKSUM POST_STATUS_CKSUMGOOD POST_STATUS_BATVRFY POST_STATUS_KBDCMD POST_STATUS_KBDDATA POST_STATUS_BLKUNBLK POST_STATUS_KBDNOP POST_STATUS_SHUTTEST POST_STATUS_CMOSDIAG POST_STATUS_CMOSINIT POST_STATUS_CMOSSTATUS POST_STATUS_DISABDMAINT POST_STATUS_DISABPORTB POST_STATUS_BOARD POST_STATUS_TESTTIMER POST_STATUS_TESTTIMER2 POST_STATUS_TESTTIMER1 POST_STATUS_TESTTIMER0 POST_STATUS_MEMREFRESH POST_STATUS_TESTREFRESH POST_STATUS_TEST15US1 POST_STATUS_TEST64KB1 POST_STATUS_TESTDATA1 POST_STATUS_TESTADDR2 POST_STATUS_TESTPARITY POST_STATUS_TESTMEMRDWR POST_STATUS_SYSINIT POST_STATUS_INITVECTORS POST_STATUS_8042TURBO POST_STATUS_POSTTURBO POST_STATUS_POSTVECTORS POST_STATUS_MONOMODE POST_STATUS_COLORMODE POST_STATUS_TOGGLEPARITY POST_STATUS_INITBEFOREVIDEO2 Code Start 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h ah bh ch 0h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah bh System Progress Report POST (BIOS is executing). Start CPU register test. Start power-on delay. Power-on delay finished. Keyboard BAT finished. Disable shadowing & cache. Compute ROM CRC, wait for KBC. CRC okay, KBC ready. Verifying BAT command to KB. Start KBC command. Start KBC data. Start pin 23,24 blocking & unblocking. Start KBC NOP command. Test CMOS RAM shutdown register. Check CMOS checksum. Initialize CMOS contents. Initialize CMOS status for date/time. Disable DMA, PICs. Disable Port B, video display. Initialize board, start memory bank detection. Start timer tests. Test 8254 T2, for speaker, port B. Test 8254 T1, for refresh. Test 8254 T0, for 18.2Hz. Start memory refresh. Test memory refresh. Test 15usec refresh ON/OFF time. Test base 64 KB memory. Test data lines. Test address lines. Test parity (toggling). Test Base 64KB memory. Prepare system for IVT initialization. Initialize vector table. Read 8042 for turbo switch setting. Initialize turbo data. Modification of IVT. Video in monochrome mode verified. Video in color mode verified. Toggle parity before video ROM test. Initialize before video ROM check. Intel® 815E Scalable Performance Board Development Kit Manual 61 BIOS Quick Reference POST_STATUS_VIDEOROM POST_STATUS_POSTVIDEO POST_STATUS_CHECKEGAVGA POST_STATUS_TESTVIDEOMEMORY POST_STATUS_RETRACE POST_STATUS_ALTDISPLAY POST_STATUS_ALTRETRACE POST_STATUS_VRFYSWADAPTER POST_STATUS_SETDISPMODE POST_STATUS_CHECKSEG40A POST_STATUS_SETCURSOR POST_STATUS_PWRONDISPLAY POST_STATUS_SAVECURSOR POST_STATUS_BIOSIDENT POST_STATUS_HITDEL POST_STATUS_VIRTUAL POST_STATUS_DESCR POST_STATUS_ENTERVM POST_STATUS_ENABINT POST_STATUS_CHECKWRAP1 POST_STATUS_CHECKWRAP2 POST_STATUS_HIGHPATTERNS POST_STATUS_LOWPATTERNS POST_STATUS_FINDLOWMEM POST_STATUS_FINDHIMEM POST_STATUS_CHECKSEG40B POST_STATUS_CHECKDEL POST_STATUS_CLREXTMEM POST_STATUS_SAVEMEMSIZE POST_STATUS_COLD64TEST POST_STATUS_COLDLOWTEST POST_STATUS_ADJUSTLOW POST_STATUS_COLDHITEST POST_STATUS_REALMODETEST POST_STATUS_ENTERREAL POST_STATUS_SHUTDOWN POST_STATUS_DISABA20 POST_STATUS_CHECKSEG40C POST_STATUS_CHECKSEG40D POST_STATUS_CLRHITDEL POST_STATUS_TESTDMAPAGE POST_STATUS_VRFYDISPMEM POST_STATUS_TESTDMA0BASE POST_STATUS_TESTDMA1BASE POST_STATUS_CHECKSEG40E POST_STATUS_CHECKSEG40F POST_STATUS_PROGDMA POST_STATUS_INITINTCTRL POST_STATUS_STARTKBDTEST POST_STATUS_KBDRESET POST_STATUS_CHECKSTUCKKEYS POST_STATUS_INITCIRCBUFFER POST_STATUS_CHECKLOCKEDKEYS POST_STATUS_MEMSIZEMISMATCH POST_STATUS_PASSWORD 62 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 60h 61h 62h 63h 64h 65h 66h 67h 80h 81h 82h 83h 84h 85h Passing control to video ROM. Control returned from video ROM. Check for EGA/VGA adapter. No EGA/VGA found, test video memory. Scan for video retrace signal. Primary retrace failed. Alternate found. Verify video switches. Establish display mode. Initialize ROM BIOS data area. Set cursor for power-on msg. Display power-on message. Save cursor position. Display BIOS identification string. Display "Hit <DEL> to ..." message. Prepare protected mode test. Prepare descriptor tables. Enter virtual mode for memory test. Enable interrupts for diagnostics mode. Initialize data for memory wrap test. Test for wrap, find total memory size. Write extended memory test patterns. Write conventional memory test patterns. Find low memory size from patterns. Find high memory size from patterns. Verify ROM BIOS data area again. Check for <DEL> pressed. Clear extended memory for soft reset. Save memory size. Cold boot: Display 1st 64KB memtest. Cold boot: Test all of low memory. Adjust memory size for EBDA usage. Cold boot: Test high memory. Prepare for shutdown to real mode. Return to real mode. Shutdown successful. Disable A20 line. Check ROM BIOS data area again. Check ROM BIOS data area again. Clear "Hit <DEL>" message. Test DMA page register file. Verify from display memory. Test DMA0 base register. Test DMA1 base register. Checking ROM BIOS data area again. Checking ROM BIOS data area again. Program DMA controllers. Initialize PICs. Start keyboard test. Issue KB reset command. Check for stuck keys. Initialize circular buffer. Check for locked keys. Check for memory size mismatch. Check for password or bypass setup. Intel® 815E Scalable Performance Board Development Kit Manual BIOS Quick Reference POST_STATUS_BEFORESETUP POST_STATUS_CALLSETUP POST_STATUS_POSTSETUP POST_STATUS_DISPPWRON POST_STATUS_DISPWAIT POST_STATUS_ENABSHADOW POST_STATUS_STDCMOSSETUP POST_STATUS_MOUSE POST_STATUS_FLOPPY POST_STATUS_CONFIGFLOPPY POST_STATUS_IDE POST_STATUS_CONFIGIDE POST_STATUS_CHECKSEG40G POST_STATUS_CHECKSEG40H POST_STATUS_SETMEMSIZE POST_STATUS_SIZEADJUST POST_STATUS_INITC8000 POST_STATUS_CALLC8000 POST_STATUS_POSTC8000 POST_STATUS_TIMERPRNBASE POST_STATUS_SERIALBASE POST_STATUS_INITBEFORENPX POST_STATUS_INITNPX POST_STATUS_POSTNPX POST_STATUS_CHECKLOCKS POST_STATUS_ISSUEKBDID POST_STATUS_RESETID POST_STATUS_TESTCACHE POST_STATUS_DISPSOFTERR POST_STATUS_TYPEMATIC POST_STATUS_MEMWAIT POST_STATUS_CLRSCR POST_STATUS_ENABPTYNMI POST_STATUS_INITE000 POST_STATUS_CALLE000 POST_STATUS_POSTE000 POST_STATUS_DISPCONFIG POST_STATUS_INT19BOOT POST_STATUS_LOWMEMEXH POST_STATUS_EXTMEMEXH POST_STATUS_PCIENUM 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 0a0h 0a1h 0a2h 0a3h 0a4h 0a5h 0a6h 0a7h 0a8h 0a9h 0b0h 00h 0b1h 0b2h 0b3h Password accepted. Entering setup system. Setup system exited. Display power-on screen message. Display "Wait..." message. Shadow system & video BIOS. Load standard setup values from CMOS. Test and initialize mouse. Test floppy disks. Configure floppy drives. Test hard disks. Configure IDE drives. Checking ROM BIOS data area. Checking ROM BIOS data area. Set base & extended memory sizes. Adjust low memory size for EBDA. Initialize before calling C800h ROM. Call ROM BIOS extension at C800h. ROM C800h extension returned. Configure timer/printer data. Configure serial port base addresses. Prepare to initialize coprocessor. Initialize numeric coprocessor. Numeric coprocessor initialized. Check KB settings. Issue keyboard ID command. KB ID flag reset. Test cache memory. Display soft errors. Set keyboard typematic rate. Program memory wait states. Clear screen. Enable parity and NMIs. Initialize before calling ROM at E000h. Call ROM BIOS extension at E000h. ROM extension returned. Display system configuration box. Call INT 19h bootstrap loader. Test low memory exhaustively. Test extended memory exhaustively. Enumerate PCI busses. Intel® 815E Scalable Performance Board Development Kit Manual 63 BIOS Quick Reference 5.13 Embedded BIOS Beep Codes Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen. When system failures are encountered at these early stages, POST uses beep codes (a sequence of tones on the speaker) to identify the source of the error. The following is a comprehensive list of POST beep codes for the system BIOS. BIOS extensions, such as VGA ROMs and SCSI adapter ROMs, may use their own beep codes, including short/long sequences, or possibly beep codes that sound like the ones below. When diagnosing a system failure, remove these adapters if possible before making a final determination of the actual POST test that failed. Mnemonic Code Beep Count POST_BEEP_REFRESH 1 POST_BEEP_PARITY 2 POST_BEEP_BASE64KB 3 POST_BEEP_TIMER 4 POST_BEEP_CPU 5 POST_BEEP_GATEA20 6 POST_BEEP_DMA 7 POST_BEEP_VIDEO 8 POST_BEEP_KEYBOARD 9 POST_BEEP_SHUTDOWN 10 POST_BEEP_CACHE 11 POST_BEEP_BOARD 12 POST_BEEP_LOWMEM 13 POST_BEEP_EXTMEM 14 POST_BEEP_CMOS 15 POST_BEEP_ADDRESS_LINE 16 POST_BEEP_DATA_LINE 17 POST_BEEP_INTERRUPT 18 POST_BEEP_PASSWORD 1 64 Description of Problem Memory refresh is not working. Parity error found in 1st 64 KB of memory. Memory test of 1st 64 KB failed. T1 timer test failed. CPU test failed. Gate A20 test failed. DMA page/base register test failed. Video controller test failed. Keyboard tes t failed. CMOS shutdown register test failed. External cache test failed. General board initialization failed. Exhaustive low memory test failed. Exhaustive extended memory test failed. CMOS restart byte test failed. Address line test failed. Data line test failed. Interrupt controller test failed. Incorrect password used to access SETUP. Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials A Table 22. Bill of Materials (Sheet 1 of 10) Rev. 1.1 Reference Designator Manuf. Part Number Alternate Manufacturing Info Description Manufacturer U7 CHIPSET (GMCH) INTEL FW82815 U15 CODEC YAMAHA YMF752-S U17 CHIPSET WINBOND W83627HF-AW "C" U12 CHIPSET (ICH2) INTEL FW82801BA U11 LINEAR IC NS LM4880MX U19 TTL74LVC06A TI 74LVC06A FAIRCHILD 74LCX06 U18 TTL74LVC07A TI 74LVC07A FAIRCHILD 74LCX07 U20 TTL74LCX14 FAIRCHILD 74LCX14 MOTOROLA 74LVC14 U8 TTLPI5C3384Q X PERICOM PI5C3384QX IDT 74FST3384Q, TI 74CBT3384A U5 TTL-PACSZ1284-02 CMD PAC-SZ1284-02 U28 TTL-PACVGA201 CMD PAC-VGA201 U9,U10 TTL-75232 GOLDSTAR 75232 U6 CLOCK GENERATO R ICS ICS9250BF-28 U29 CLOCK GENERATO R ICS ICS9112BM-17 Q2,Q18 TRANSISTO R FAIRCHILD MMBT2907A MOTOROLA MMBT2907A, PHILIPS PMBT2907A Q1,Q13,Q16,Q17 TRANSISTO R 2N7002 VISHAY 2N7002E, FAIRCHILD 2N7002 PHILIPS Intel® 815E Scalable Performance Board Development Kit Manual All Changes WINBOND W83627HF-AW "D" TI GD75232, ALI M5232 PA1 65 Bill of Materials Table 22. Bill of Materials (Sheet 2 of 10) Rev. 1.1 Description Manufacturer Q14,Q15,Q19,Q20,Q21 ,Q22 TRANSISTO R PHILIPS PMBS3904 Q5 TRANSISTO R FAIRCHILD NDS356AP Q4 TRANSISTO R FAIRCHILD NZT651 U2 REGULATO R RICHTEK RT9641ACS Q3,Q24 REGULATO R FAIRCHILD RC1117ST U4 REGULATO R RICHTEK RT9230CS Q10,Q12 MOSFET FAIRCHILD SSR3055LA Q7,Q11 MOSFET HARRIS HUF76107D3S Q6,Q9 MOSFET PHILIPS PHB55N03LT Q8 MOSFET FAIRCHILD FDS8936A FAIRCHILD NDS8936 D1,D4,D5,D10,D13,D1 4,D15,D17 DIODE VISHAY LL4148-RF VISHAY LL4148, PHILIPS BAS32L D2,D6,D7,D8,D12,D18 DIODE WILLAS SS12 MICROSEMI SS12 D3 DIODE MICROSEMI SK32B MOLEX 120 PIN (PCI) ’NYLON" FOXCONN 120 PIN (PCI), ATMEL 120 PIN (PCI) AGP 132PIN UNIVERSAL FOXCONN AGP 132PIN UNIVERSAL, TEKCON AGP 132PIN UNIVERSAL PCI1,PCI2,PCI3 AGP1 66 SLOT SLOT MOLEX Manuf. Part Number Alternate Manufacturing Info Reference Designator All Changes FAIRCHILD MMBT3904, MOTOROLA MMBT3904 AMS AMS1117, AMI AME1117ACGT PHILIPS PHD3055E Y3 X’TAL H.ELE 14.318MHZ (VERTICAL) FUJICOM 14.318MHZ (VERTICAL), TQG 14.318MHZ (VERTICAL) Y1 X’TAL H.ELE 24.576MHZ(VER TICAL) TQG 24.576MHZ(VE RTICAL) Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials Table 22. Bill of Materials (Sheet 3 of 10) Rev. 1.1 Reference Designator Y2 Description Manufacturer X’TAL KDS Manuf. Part Number Alternate Manufacturing Info 32.768KHZ EPSON 32.768KHZ, CITIZEN 32.768KHZ DIMM1,DIMM2,DIMM3 SOCKET MOLEX DIMM UNBUFFERED 168PIN 3.3V NYLON FOXCONN DIMM UNBUFFERED 168PIN 3.3V, TEKCON DIMM UNBUFFERED 168PIN 3.3V NYLON U3 SOCKET FOXCONN 370 PIN ZIF(ANTIFLUX)NEW AMP 370 PIN ZIF U23 SOCKET FOXCONN 32 PIN SP1 BUZZER HYPAK KC-1206 U7 HEAT SINK AAVID 37.4*37.4*9.8mm +LATCH GREEN SW1 DIP SWITCH 8*2 PIN JP1(1-2) JUMPER 2PIN (BLACK) BAT1 BATTERY SOCKET D16 LED RED S1,JP3 HEADER 2*1 PIN JP1 HEADER 3*1 PIN WOL1 HEADER WAFER WOL 3*1PIN PITCH 2mm AUX1,CD2 HEADER WAFER 4*1PIN(CD-IN) JP4 HEADER 5*1 PIN(CUT PIN1) IR1,SMB1,SMB2,JP5 HEADER 5*1 PIN USB2 HEADER 5*2 PIN CUT PIN 1,2 COM2 HEADER 5*2 PIN PN1 HEADER 14x1 PIN w/ No. 6,9,12 MISSING PN2 HEADER 14x1 PIN w/ No. 3,8,11 MISSING FDC1 HEADER WAFER 17*2 PIN VL1 HEADER 20*2PIN(F) All Changes LOTES Intel® 815E Scalable Performance Board Development Kit Manual 67 Bill of Materials Table 22. Bill of Materials (Sheet 4 of 10) Rev. 1.1 Reference Designator 68 Description Manufacturer Manuf. Part Number Alternate Manufacturing Info All Changes WAFER 20*2PIN CUT PIN20(?) IDE1,IDE2 HEADER FAN1,FAN2,FAN3 HEADER MOLEX WAFER W/LOCK 3P ATXPR1 CON. WIESON MINI FIT CON.20PIN TEKCON MINI FIT CON.20PIN(NE W) USB1 CON. FOXCONN USB CON. 2*4 PIN DUAL PORT MOLEX USB CON. 2*4 PIN DUAL PORT(NEW), WIESON USB CON. 2*4 PIN DUAL PORT U1 KEYBOARD & MOUSE WIESON MINI-DIN 6Px2 DUAL PORTPC99 FOXCONN MINI-DIN 6Px2 DUAL PORTPC99 CD1 CON. CNRSLOT1 SLOT FOXCONN 60 PIN (CNR) JK1+JK2+JK3+J1 D-TYPE FOXCONN D-SUB 90° 15P(F)7+8/ PHONE*3-PC99 VGA1 D-TYPE FOXCONN D-SUB 15PIN (F) 3*5(S)-PC99 TEKCON DSUB 15PIN (F) 3*5(S)-PC99 LPT1 D-TYPE WIESON D-SUB 90° 25PIN (F) RISE HIGH PC99 TEKCON DSUB 90° 25PIN (F) RISE HIGH -PC99 WAFER 2.0m/m 4P MOLEX 60 PIN (CNR), AMP 60 PIN (CNR) COM1 D-TYPE FOXCONN D-SUB 9PIN (MALE) -PC99 WIESON DSUB 9PIN (MALE) -PC99, TEKCON DSUB 9PIN (MALE) -PC99 BAT1 BATTERY MAXELL CR2032 PANASONIC CR2032, SONY CR2032 RN74 R.P 0 OHM (8P 4R) CONCAVE 0 OHM (8P 4R) CONVEX RN36,RN37,RN38 R.P 10 OHM (8P 4R) CONCAVE 10 OHM (8P 4R) - CONVEX RN70,RN71 R.P 15 OHM (8P 4R) CONCAVE 15 OHM (8P 4R) - CONVEX Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials Table 22. Bill of Materials (Sheet 5 of 10) Rev. 1.1 Reference Designator Description Manufacturer Manuf. Part Number Alternate Manufacturing Info RN19,RN20,RN69 R.P 22 OHM (8P 4R) CONCAVE 22 OHM (8P 4R) - CONVEX RN34 R.P 33 OHM (8P 4R) CONCAVE 33 OHM (8P 4R) - CONVEX RN3,RN5,RN6,RN7,RN 8,RN9,RN10, R.P 56 OHM (8P 4R) CONCAVE 56 OHM (8P 4R) - CONVEX RN11,RN12,RN13,RN1 4,RN15,RN16,RN17,R N18,RN21,RN22,RN23, RN24,RN25,RN26,RN2 7,RN28,RN29,RN30,R N31,RN32,RN33 R.P RN39,RN40 R.P 1K (8P 4R) CONCAVE 1K (8P 4R) CONVEX RN41,RN59 R.P 2.2K (8P 4R) CONCAVE 2.2K (8P 4R) CONVEX RN58,RN64,RN66 R.P 2.7K (8P 4R) CONCAVE 2.7K (8P 4R) CONVEX RP2 R.P 2.7K (10P 8R) CONVEX (3216)R RN4,RN60 R.P 4.7K (8P 4R) CONCAVE RN42,RN43,RN44,RN4 5,RN46,RN48, R.P 8.2K (8P 4R) CONCAVE RN49,RN51,RN54,RN5 5,RN75,RN77 R.P 8.2K (8P 4R) CONVEX RN72,RN73 R.P 15K (8P 4R) CONCAVE R37,R38,R40,R166,R2 07,R237,R240, R256,R315,R326,R327 RESISTOR 0 OHM (0603) R36,R47,R48,R52,R60, R72,R141,R321, R322 RESISTOR 10 OHM (0603) R44,R50,R51,R62,R63, R104,R105,R251, R275 RESISTOR 22 OHM (0603) R45,R46,R49,R57,R58, R64,R65,R66, R67,R85,R87,R112,R1 13,R191,R236, R277,R290,R320 RESISTOR 33 OHM (0603) R91,R98,R316,R317 RESISTOR 47 OHM (0603) R59 RESISTOR 51 OHM (0603) R23 RESISTOR 56 OHM (0603) R231,R232 RESISTOR 68 OHM (0603) Intel® 815E Scalable Performance Board Development Kit Manual All Changes 4.7K (8P 4R) CONVEX 15K (8P 4R) CONVEX 69 Bill of Materials Table 22. Bill of Materials (Sheet 6 of 10) Rev. 1.1 Reference Designator 70 Description Manufacturer Manuf. Part Number R133,R142,R148,R154, R187,R230,R245 RESISTOR 100 OHM (0603) R1,R2,R5,R6,R7,R12,R 14,R15,R234,R243 RESISTOR 150 OHM (0603) R86,R238,R242 RESISTOR 220 OHM (0603) R185,R193 RESISTOR 300 OHM (0603) R8,R13,R199,R239 RESISTOR 330 OHM (0603) R16,R216 RESISTOR 510 OHM (0603) R9 RESISTOR 680 OHM (0603) R3,R4,R10,R19,R53,R 73,R84,R100, R115,R116,R117,R120, R121,R122,R129, R134,R181,R188,R196, R197,R198,R212, R217,R252,R254,R314, R323,R324,R325, R336 RESISTOR 1K (0603) R153 RESISTOR 1.8K (0603) R28,R106,R108,R110, R119,R226,R246, R328,R329 RESISTOR 2.2K (0603) R29 RESISTOR 3.9K (0603) R11,R54,R76,R79,R92, R93,R94,R95,R96, R97,R99,R101,R102,R 189,R218,R229 RESISTOR 4.7K (0603) R75,R83,R88,R89,R90, R206,R211,R249, R260,R261,R262,R263, R276,R332-R335 RESISTOR 8.2K (0603) R20,R70,R80,R107,R1 09,R147,R152, R157,R167,R208,R209, R214,R223,R233, R235,R241,R244,R255, R302,R303 RESISTOR 10K (0603) R174,R190,R272,R273 RESISTOR 15K (0603) R43,R126,R127,R128, R132,R247 RESISTOR 20K (0603) R210 RESISTOR 30K (0603) R192 RESISTOR 33K (0603) R118,R124,R125,R155, R337 RESISTOR 220K (0603) R266,R267 RESISTOR 330K (0603) R164,R271 RESISTOR 560K (0603) Alternate Manufacturing Info All Changes Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials Table 22. Bill of Materials (Sheet 7 of 10) Rev. 1.1 Reference Designator Description Manuf. Part Number Manufacturer R149,R162,R213 RESISTOR 10M (0603) PR14 RESISTOR 15 OHM (1%) 0603 R31 RESISTOR 22 OHM (1%) 0603 R56 RESISTOR 33 OHM (1%)0603 PR9,PR15,PR18,PR27 RESISTOR 40.2 OHM (1%)0603 PR41 RESISTOR 60.4 OHM (1%)0603 PR7,PR10,PR11,PR12, PR42 RESISTOR 75 OHM (1%)0603 PR21,PR24 RESISTOR 82 OHM (1%)0603 R33,R61 RESISTOR 90.9 OHM (1%)0603 PR2,PR3 RESISTOR 100 OHM (1%) 0603 PR1,PR5 RESISTOR 110 OHM 1% 0603 PR40 RESISTOR 120 OHM (1%)0603 PR4,PR6,PR8,PR43 RESISTOR 150 OHM (1%)0603 PR13 RESISTOR 174 OHM (1%)0603 PR19 RESISTOR 200 OHM (1%)0603 R318,R319 RESISTOR 243 OHM 1% (0603) PR16,PR17,PR20,PR2 5,PR26 RESISTOR 301 OHM 1% (0603) PR22,PR23,R32,R55 RESISTOR 1K 1%(0603) R39 RESISTOR 1.43K (1%)0603 PR36,PR38,PR39 RESISTOR 10K (1%)0603 PR37 RESISTOR 28K (1%)0603 PR33,PR35,R42 RESISTOR 56K(1%)0603 PR32 RESISTOR 120K 1%(0603) PR34 RESISTOR 232K 1% (0603) Intel® 815E Scalable Performance Board Development Kit Manual Alternate Manufacturing Info All Changes 71 Bill of Materials Table 22. Bill of Materials (Sheet 8 of 10) Rev. 1.1 Reference Designator 72 Manuf. Part Number Description Manufacturer RT1 THERMISTO R SEMITEC C11,C14,C26,C60,C64, C67,C71 CAPACITOR 0.001UF (0603) BC26,BC28,BC29,BC3 2,BC33, BC46BC48,BC51,BC52,BC5 5,BC57, BC59,BC62,BC63,BC6 5,BC74,BC75, BC79,BC80,BC82,BC8 7,BC88, BC90BC98,BC105,BC114,B C119, BC124,BC144, BC147,BC149,BC150, BC158-BC160,BC169BC171, BC181BC183,BC186,BC187,B C222, BC226,C17,C85 CAPACITOR 0.01UF (0603) C4,C7,C27,C119,BC1BC3,BC5, BC7BC25,BC27,BC30,BC3 1, BC34BC45,BC49,BC50,BC5 3,BC54, BC56,BC58,BC60,BC6 1,BC64,BC66, BC67,BC69BC73,BC76BC78,BC81, BC83BC86,BC89,BC99BC104, BC106BC113,BC115,BC116, BC121BC123,BC125,BC128, BC129,BC131,BC132,B C136, BC138BC140,BC142,BC143,B C145, BC146,BC151,BC154BC157,BC161BC165,BC167, BC168,BC172,BC173,B C175, BC177BC180,BC184,BC185,B C197, BC204BC218,BC221,BC227, MC51, MC52,MC55 CAPACITOR 0.1UF (0603) BC68,BC223,BC224,B C225 CAPACITOR 0.22UF (0603) C110 CAPACITOR 0.047UF (0603) Alternate Manufacturing Info All Changes 10K OHM ±3% (0603) Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials Table 22. Bill of Materials (Sheet 9 of 10) Rev. 1.1 Reference Designator Description Manuf. Part Number MC36,MC37,MC38,MC 39,MC40,MC41, MC42,MC43,MC44,MC 45,MC47,MC53, MC54,MC56,C5,C8,C1 3,C15,C18,C91, C104,C113 CAPACITOR 1UF (0603) MC48,MC57,MC59,C1, C2,C115 CAPACITOR 2.2UF (0805) MC1-MC6,MC8MC10,MC13-MC15 CAPACITOR 4.7UF(1206)"X7R " MC7,MC11,MC12,MC1 6,MC17,MC18, MC19,MC20,MC21,MC 22,MC23,MC24, MC25,MC26,MC27,MC 28,MC29,MC30, MC31,MC32,MC33,MC 34,MC35,MC46, MC60,MC61,MC62,MC 63,MC66 CAPACITOR 4.7UF(1206)"Y5V C43,C47,C50 CAPACITOR 3.3PF(0603) C12,C16,C48,C53,C54, C56,C58,C99, C101 CAPACITOR 10PF (0603) C61 CAPACITOR 15PF (0603) C33,C35,C102,C103 CAPACITOR 18PF (0603) C36,C55,C57,C63,C65, C66,C68,C97,C98 CAPACITOR 22PF (0603) C44,C51,C125,C126 CAPACITOR 47PF (0603) C74,C75,C76,C79,C80, C81,C82,C83, C84,C86,C87,C90 CAPACITOR 100PF (0603) C59,C62,C70,C73,C12 2,BC4 CAPACITOR 470PF (0603) C69,C72 CAPACITOR 560PF (0603) C94,C95 CAPACITOR 2700PF (0603) C118 CAPACITOR 3300PF (0603) CN2,CN3,CN9,CN11 C/P 100PF (8P 4C) (1206) CP1,CP2,CP3,CP4 C/P 47PF(8P4C)(1206 ) CN1,CN8,CN10 C/P 470PF (8P 4C) (1206) EC6,EC11,EC20,EC40, EC41 E/C Manufacturer TAYEH 10UF/25V (4*7) Intel® 815E Scalable Performance Board Development Kit Manual Alternate Manufacturing Info All Changes JACKCON 10UF/25V (4*7) 73 Bill of Materials Table 22. Bill of Materials (Sheet 10 of 10) Rev. 1.1 Manuf. Part Number Alternate Manufacturing Info TAYEH 22UF/16V (4*7) JACKCON 22UF/16V (4*7) E/C TAYEH 100UF/16V (6.3*7) JACKCON 100UF/16V (6*7) C6 T/C SPRAGUE 33UF/20V "D" EC1,EC2,EC4,EC7,EC 8,EC9,EC12,EC13, E/C TAYEH 1500UF/ 6.3V(8*16) EC14,EC21,EC23,EC2 4,EC25,EC29, E/C JACKCON 1500UF/ 6.3V(8*16) EC31,EC32,EC34,C32 E/C JPCON 1500UF/6.3V (8*16) L3 INDUCTOR GLOMAG IRON COIL 1UH(50MB) L1 INDUCTOR GLOMAG IRON COIL 2.5UH(5052) L2 INDUCTOR MURATA 4.7UH (0805) L4 INDUCTOR GLOMAG IRON COIL 7UH(5052B) F1,F2,F4,F5,F6,F7 FUSE BOURNS POLY S/W MSMC110-2 RAYCHEM POLY S/ WSMDC100 FB1,FB2,FB3,FB4,FB5, FB6,FB8,FB11, INDUCTOR TAIYO BEAD 241/ 100MHZ (0805) LL241 EMC BEAD 221/100MHZ (0805) INDUCTOR MURATA BEAD BLM11B750SPT( 0603) CHIPSET (FWH) INTEL N82802AC8 Reference Designator Description Manufacturer EC3,EC26,EC27,EC28, EC33,EC35,EC36, E/C EC5,EC10,EC15,EC17, EC18,EC19, All Changes EC22,EC30,EC39,C77, C78 FB12,FB13,FB14,FB15, FB16,FB17, FB19-FB29 VFB1,VFB2,VFB3,PFB 1,PFB2,PFB4, PFB5,PFB6,PFB11,PF B12, U23 74 Intel® 815E Scalable Performance Board Development Kit Manual Bill of Materials Table 23. Key Components Bill of Materials Rev. 1.1 Description Manufacturer Part # 815E Scalable Performance Board Development Kit Baseboard ABIT EIAP3815EDEVKIT Intel® Pentium® III Processor at 866 MHz with 256K L2 Intel RB80526PY866256 Intel® Celeron™ Processor at 850 MHz with 128K L2 Intel RB80526RY850128 Thermal Solution Agilent Technologies Arcti-Cooler, HACA-0001 133 MHz, 128 Mbyte, SDRAM DIMM SpecTek P16M648YLDC9-133CL3A Firmware Hub BIOS Memory, PLCC32 (8 Mbit) Intel N82802AC8 15.3 Gbyte Hard disk drive Western Digital WD153AA BlueCat Linux OS Software (preinstalled on HDD) LynuxWorks N/A Tornado 2.0/VxWorks CD Wind River Systems TEV-13720-ZC-00 ABIT SL-30 device driver CD ABIT SA-1.00E Intel® Pro/100+ Management Adapter (Fast Ethernet Controller) Intel PILA8460B NOTE: *This BOM does not include items such as mounting hardware, packaging material, documentation, etc. Intel® 815E Scalable Performance Board Development Kit Manual 75 Schematics B Schematics are provided for the following items listed below. Schematics are available from the Intel Developer’s Web site in PDF format. • • • • • • • • • • • • • • • • • • • • • • • • • • Block diagram PGA370 Part 1 and 2 AGTL Termination Clock Synthesizer GMCH Part 1 and 2 DIMM 1 and 2 DIMM 3 AGP ICH Part 1 and 2 PCI 1 and 2 PCI 3 Video Bus & Connector FWH & UDMA100 IDE 1-2 USB 0-3 AC97 CODEC Audio I/O LPC I/O Controller & FDCL WOR, WOL & 2S1P KB, MS, GAME, & IR Front Panel & CNR ATX Power & H/W Monitor Voltage Regulator Part 1 Voltage Regulator Part 2 System Configuration PU/PDR and unused gates Decoupling capacitors Intel® 815E Scalable Performance Board Development Kit Manual 77 1 2 3 4 B C D E ABIT SL30 A 25 26 27 28 29 ATX POWER & H/W MONITOR VOLTAGE REGULATOR PART 1 VOLTAGE REGULATOR PART 2 SYSTEM CONFIGURATION B C D **PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE 32 24 FRONT PANEL & CNR HISTORY 23 KB, MS, GAME & IR 30 22 WOR, WOL & 2S1P 31 21 LPC I/O CONTROLLER & FDCL DECOUPLING CAPACITORS 20 AUDIO I/O PU/PDR & UNUSED GATES 19 14 AC97 CODEC 12,13 PCI 1 & 2 18 11 ICH PART 1 & 2 USB 0-3 10 AGP 17 9 DIMM 3 FWH & UDMA100 IDE 1-2 7,8 DIMM 1 & 2 16 6 GMCH PART 1 & 2 VIDEO BUS & CONNECTOR 5 CLCOK STNTHESIZER 15 3,4 AGTL TERMINATION PCI 3 2 PGA370 PART 1 & 2 LEFT BLANK 1 PAGE BLOCK DIAGRAM TITLE COVER SHEET REVISION 0.12 Date: Size B Title Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number COVER SHEET E Sheet ABIT Computer Corp. INTEL(R) PENTIUM(R) III & CELERON(TM) PROCESSOR(PPGA)/815E CHIPSET UNIPROCESSOR ABIT SCHEMATICS A 1 of 32 Rev A 1 2 3 4 1 2 ABIT SL30 A IDE Primary Floopy FirmWare Hub USB PORT 1-4 USB B Game Port UDMA/100 ADDR IDE Secondary ADDR Mouse Keyboard SIO ICH2 GMCH CTRL Digital Video Out Device Serial 1 GTL BUS 3 DIMM Modules CLOCK C Serial 2 Parallel Audio Codec CNR &RQQHFWRU PCI ADDR/DATA PCI CNTRL C AC’97 LINK 370-PIN SOCKET PROCESSOR BLOCK DIAGRAM CTRL AGP Connector VRM B DATA 3 4 A Term. PCI CONN3 PCI CONN 2 PCI CONN 1 DATA D D Date: Size B Title Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number BLOCK DIAGRAM E Sheet ABIT Computer Corp. E 2 of 32 Rev A 1 2 3 4 A B C D RS#0 RS#1 RS#2 ABIT SL30 5,7 5,7 5,7 5 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 RS#0 RS#1 RS#2 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 Socket 370_9 AH26 AH22 AK28 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 U3A 4 3 370 - Pin Socket Part 1 4 3 AM34 GND AH2 GND AD2 GND Z2 GND V2 GND M2 GND D18 GND H2 GND D2 GND AL3 GND AK4 GND AG5 GND AC5 GND Y5 GND U5 GND Q5 GND L5 GND G5 GND D4 GND B4 GND AM6 GND AJ7 GND E7 GND B8 GND AM10 GND AJ11 GND E11 GND B12 GND AM14 GND AJ15 GND E15 GND B16 GND AM18 GND AJ19 GND E19 GND F20 GND B20 GND AM22 GND AJ23 GND D22 GND F24 GND B24 GND AM26 GND AJ27 GND D26 GND F28 GND B28 GND AM30 GND D30 GND AF32 GND AB32 GND X32 GND T32 GND P32 GND F32 GND B32 GND AH34 GND AD34 GND Z34 GND V34 GND R34 GND M34 GND H34 GND D34 GND 5 2 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 2 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VID0 VID1 VID2 VID3 GND/VID4 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# VCCVID B26 C3 AK2 AF2 AB2 T2 P2 K2 F4 E5 AM4 AE5 AA5 W5 S5 N5 J5 F2 D6 B6 AM8 AJ9 E9 B10 AM12 AJ13 E13 B14 AM16 AJ5 AJ17 E17 B18 AM20 AJ21 D20 F22 AM24 AJ25 D24 F26 AM28 AJ29 D28 AK34 F30 B30 AM32 AH32 Z32 V32 R32 M32 H32 AF34 AB34 X34 T34 P34 K34 F34 B34 AH36 B22 V36 R36 H36 D36 D32 AD32 AH24 F14 K32 AA37 Y35 VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID AF36 GND X36 GND T36 GND P36 GND K36 GND F36 GND A37 GND AC33 GND AJ3 GND AL1 GND AN3 GND Y37 GND HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 AH20 AK16 AL21 AN11 AN15 G35 AL13 U37 U35 S37 S33 E23 AN21 AA35 AA33 Date: Size B Title AL35 AM36 AL37 AJ37 AK36 AK18 AH16 AH18 AL19 AL17 C33 C31 A33 A31 E31 C29 E29 VTT1_5 A29 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC1 W3 AF4 HD#[0..63] HA#[3..31] 5,7 5,7 5,7 5,7 5,7 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number PGA370 PART 1 1 Sheet ABIT Computer Corp. 22,27 22,27 22,27 22,27 5,7 5,7 VID0 VID1 VID2 VID3 HD#[0..63] HA#[3..31] 1 3 of 32 Rev A A B C D A B C D CPU_PWGD CPURST# ABIT SL30 12 7 12 APICD0 12 APICD1 6 APICCLK_CPU 6 CPUHCLK ITPRDY# ITPCLK 6 5 DBRESET# 26 5 R315 0 J2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 HEADER 15X2 150,1% BC7 0.1UF MC7 4.7UF 150,1% PR4 4 10PF C12 22 R275 86 243 VCC2_5 150 R6 VTT1_5 330 R13 R33 150 R14 R319 PR6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2.7K 1K 150 R199 R15 VCC2_5 R314 VTT1_5 4 150 R7 243 VTT1_5 47 330 R8 X18PF Place Site w/in 0.5" of clock pin (W37) C3 Do Not stuff C 51 R59 VCCVID R318 R316 R317 47 150 R5 C37 AG1 J35 L35 J33 W37 Y33 AK26 AH4 X4 X2 AM2 F10 W35 Y1 R2 G37 L33 N33 N35 N37 Q33 Q35 Q37 G33 E37 C35 E35 J37 A35 AN35 AN37 AN33 AL33 AK32 150,1% PR8 75,1% PR7 3 VTT1_5 Socket 370_9 CPUPRES# EDGCTRL/VRSEL PICD0 PICD1 PICCLK BCLK CLKREF PWRGOOD RESET# RESET2# VTT1_5 SLEWCNTR RTTCNTR VCOREDET BINIT# AERR# BERR# BC17 0.1UF BC18 0.1UF 0.1UF BC16 Use 0603 Packages and distribute within 500 miles of Mendocino GTLREF Inputs ( 1 cap for every 2 inputs ) 0.1UF BC12 GTLREF RSP# AP0# AP1# RP# PLL1 PLL2 A20M# STPCLK# SLP# SMI# LINT0/INTR LINT1/NMI INIT# FERR# IGNNE# IERR# BR0# THRMDP THRMDN THERMTRIP# GTLREF Generation Circuit Part2 BNR# BPRI# TRDY# DEFER# LOCK# DRDY# HITM# HIT# DBSY# ADS# FLUSH# BSEL0# BSEL1# RSRVD12/JBSEL1# 370 - Pin Socket 0.1UF BC1 VCC2_5 Place 0603 Paclage near VCMOS Processor Pin RESVD21(BR1#) RSRVD13 RSRVD15 RSRVD16 RSRVD17 RSRVD18 RSRVD19 RSRVD20 RSRVD6 RSRVD7 RSRVD8 RSRVD9 RSRVD10 RSRVD11 BP2# BP3# BPM0# BPM1# PREQ# PRDY# TDI TDO TRST# TCK TMS U3B 680 R9 VCMOS Decouping 3 AB36 AD36 Z36 V_CMOS V1_5 V2_5 E33 F18 K4 R6 V6 AD6 AK12 AK22 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 5 2 E27 S35 E21 B36 AK24 V4 AC37 AL11 AN13 AN23 W33 U33 AE33 AG35 AH30 AJ35 M36 L37 AG33 AC35 AG37 AE35 AN29 AL31 AL29 AH28 AJ33 AJ31 AK30 AH14 AN17 AN25 AN19 AK20 AN27 AL23 AL25 AL27 AN31 AE37 2 150 150 220 R86 Date: Size B Title 110,%1 PR1 33UF,20% R1 R2 VCC3_3 C6 + 5 22,26 22,26 12 12 12 12 12 12 12,18 12 12 BR0# VTIN2 THRMDN A20M# STPCLK# CPUSLP# SMI# INTR NMI INIT# FERR# IGNNE# BSEL#1 0 0 1 1 VCOREDET Wednesday, March 08, 2000 1 Sheet ABIT Computer Corp. AB-SL30 V0.12 Document Number 29 29 BSEL#0 BSEL#1 4 BSEL#0 0 1 0 1 7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 13 BNR# BPRI# HTRDY# DEFER# HLOCK# DRDY# HITM# HIT# DBSY# HADS# GTLREF VCMOS VCCVID 4.7UH/SMD-0805 L2 1K R4 PGA370 PART 2 110,%1 PR5 1K R3 V3SB V3SB GTLREF 1 of 32 FSB 66M 100M rsvd 133M Rev A A B C D A B C D HA#6 HA#8 HA#11 HA#4 HA#18 HA#26 HA#29 HA#27 56/8P4R RN16 2 4 6 8 56/8P4R RN18 2 4 6 8 56/8P4R RN28 2 4 6 8 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 3,7 HREQ#1 MC22 4.7UF 0.1UF 0.1UF 5 BC35 BC34 0.1UF BC36 4,7 BNR# " One Cap for each 2 R-Pack " ABIT SL30 4.7UF MC23 VTT1_5 HA#28 HA#15 HA#12 HA#5 56/8P4R RN32 2 4 6 8 1 3 5 7 56/8P4R HA#30 HA#24 HA#20 56/8P4R RN29 2 4 6 8 1 3 5 7 HA#14 HA#7 HA#13 HA#16 HA#3 HA#9 56/8P4R RN33 2 4 6 8 HA#23 HA#17 HA#22 HA#31 HA#19 HA#21 HA#25 HA#10 2 4 6 8 56/8P4R RN31 2 4 6 8 RN30 1 3 5 7 1 3 5 7 VTT1_5 5 0.1UF 2 4 6 8 HD#29 HD#31 HD#35 HD#32 HD#33 HD#25 HD#26 HD#19 HD#11 HD#14 HD#2 HD#18 HD#7 HD#30 HD#20 HD#13 HD#3 HD#12 HD#10 HD#17 HD#23 HD#21 HD#16 HD#24 HD#8 HD#5 HD#9 HD#4 HD#15 HD#1 HD#0 HD#6 0.1UF BC38 56/8P4R 56/8P4R RN17 2 4 6 8 56/8P4R RN21 2 4 6 8 56/8P4R RN24 2 4 6 8 56/8P4R RN23 2 4 6 8 56/8P4R RN25 2 4 6 8 56/8P4R RN22 2 4 6 8 56/8P4R RN26 2 4 6 8 RN27 BC37 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 VTT1_5 0.1UF BC24 4 0.1UF BC23 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 VTT1_5 4 2 4 6 8 0.1UF BC5 56/8P4R 56/8P4R RN13 2 4 6 8 56/8P4R RN15 2 4 6 8 56/8P4R RN10 2 4 6 8 56/8P4R RN11 2 4 6 8 56/8P4R RN6 2 4 6 8 56/8P4R RN5 2 4 6 8 56/8P4R RN3 2 4 6 8 RN8 0.1UF BC14 HD#39 HD#37 HD#36 HD#38 HD#43 HD#34 HD#28 HD#22 HD#47 HD#41 HD#49 HD#51 HD#42 HD#27 HD#44 HD#45 HD#54 HD#55 HD#57 HD#63 HD#50 HD#53 HD#58 HD#46 HD#56 HD#61 HD#62 HD#60 HD#59 HD#48 HD#52 HD#40 0.1UF BC22 2 4 6 8 56 150 HA#[3..31] HD#[0..63] 56/8P4R 56/8P4R RN14 2 4 6 8 56/8P4R RN7 2 4 6 8 56/8P4R RN9 2 4 6 8 RN12 HA#[3..31] HD#[0..63] BR0# ITPRDY# HREQ#4 BPRI# HREQ#0 HREQ#3 DRDY# DBSY# RS#2 HADS# HITM# HTRDY# HIT# RS#0 DEFER# HREQ#2 HLOCK# RS#1 0.1UF BC9 0.1UF BC15 3 0.1UF BC2 0.1UF BC13 AGTL Termination R23 R12 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 VTT1_5 3 0.1UF BC3 3,7 3,7 4 4 3,7 4,7 3,7 3,7 4,7 4,7 3,7 4,7 4,7 4,7 4,7 3,7 4,7 3,7 4,7 3,7 2 2 U3C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GD28 GD29 GD30 GD31 GD32 GD33 GD34 GD35 GD36 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 Date: Size B Title Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 1 Sheet ABIT Computer Corp. AGTL TERMINATION HEATSINK GROUNDING Socket 370_9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 1 5 of 32 Rev A A B C D 1 2 3 4 ABIT SL30 A MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 13,22,28 SLP_S3# 9,10,13,22,25,30 SMBCLK 9,10,13,22,25,30 SMBDATA 29 FMOD0 12 PCLK_0/ICH 13 ICH_CLK14 13 ICH_3V66 8 GMCH_3V66 11 AGPCLK_CONN 29 FMOD1 VCC2_5 VCC3SBY VCC3SBY 1 1 1 X10PF X10PF C40 10 0.1UF X10P/8P4C MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 VCC3_3 C39 R60 4.7UF X10PF CN4 4.7UF 1 X10PF C41 0.01UF 0.1UF 33 33 33 33 33 10 R67 R290 R72 0.1UF MEMCLK8 MEMCLK9 MEMCLK10 MEMCLK11 4.7UF B 0.1UF X10PF C34 0.01UF X10PF C31 14.318MHZ Y3 0.01UF R64 R65 R66 0.1UF MC66 BC221 BC222 18PF C33 18PF C35 0.01UF X10P/8P4C CN5 BEAD PFB12 2 X10PF C42 0.01UF MC21 BC25 BC26 4.7UF MC29 BC62 BC61 BC57 BC58 BC59 BC60 0.01UF 0.1UF MC28 BC55 BC56 C29 BEAD PFB11 2 BEAD PFB5 2 BEAD B R302 X10PF C23 10K 8.2K PD# SCLK SDATA FS0 FS1 PCICLK0 PCICLK1 3V66-0 3V66-1 3V66-2 X2 REF0 X1 X10PF C22 PCLK_REF 10K R303 21 22 23 18 28 15 16 10 11 12 7 4 6 U6 L_VCC2_5 PCIV3 R249 AV3 GNDL GNDL 3 55 PFB4 2 2 56 VDDL VDDL C 5 9 14 20 25 31 35 40 44 49 5 12 1 9 8 4 13 U29 CLKOUT CLKB1 CLKB2 CLKB3 CLKB4 CLKA1 CLKA2 CLKA3 CLKA4 C 7 5 3 1 8 6 4 2 33 X33 R277 R312 16 33/8P4R RN34 6 7 10 11 2 3 14 15 C21 X10PF X18PF D X10P/8P4C CN6 X10PF X10PF C120 X10PF C133 C25 4.7UF X10PF 0.1UF MC20 0.1UF C20 0.01UF X10PF 0.1UF C19 C132 33 33 33 R48 R49 26 27 R47 22 R44 37 36 33 32 45 42 41 38 51 50 47 46 29 0.01UF 33 33 33 33 7 5 3 1 22/8P4R 7 5 3 1 22/8P4R 22 22 22 22 0.1UF 0.01UF 33 ICS9250-28 48MHZ_0 48MHZ_1 SDRAM12 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM4 SDRAM5 SDRAM6 SDRAM7 0.1UF R46 R45 R57 R58 8 6 4 2 RN19 8 6 4 2 RN20 R50 R51 R62 R63 0.01UF R320 0.1UF 54 53 1 0.01UF SDRAM0 SDRAM1 SDRAM2 SDRAM3 ICS9112B-17 GND GND REF FS1 FS2 VDD VDD 0.01UF BC32 BC31 D BC226 BC227 BC28 BC27 BC29 BC30 BC33 BC21 BC63 BC64 MEMV3 USBV3 CPUCLK_0 CPUCLK_1 IOAPIC VDD VDD VDD VDDA VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND 8 13 17 19 24 30 34 39 43 48 52 A 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 1 1 X10PF Date: Size B Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 13 8 22 SIO_CLK24 14 14 15 22 18 PCLK_1 PCLK_2 PCLK_3 PCLK_7 PCLK_8 6 MEMCLK[8..11] 10 MEMCLK[0..7] 9 7 USBCLK DOTCLK CPUHCLK GMCHHCLK APICCLK_CPU APICCLK_ICH DCLK_WR 4 4 7 4 12 ITPCLK E E Sheet ABIT Computer Corp. MEMCLK[8..11] MEMCLK[0..7] MEMCLK8 MEMCLK9 MEMCLK10 MEMCLK11 MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 VCC3SBY VCC3SBY CLOCK SYNTHESIZER X10PF C30 BEAD PFB1 2 BEAD C28 Title X10PF C24 4.7UF MC19 4.7UF MC18 PFB2 2 of 32 Rev A 1 2 3 4 A B C D 4 GTLREF HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 5 K2 L1 H1 C38 X18PF RS#0 RS#1 RS#2 Do Not Stuff C Place Site w/in 0.5" of clock ball(v6) R4 P1 T2 R3 N5 P5 R1 U1 P2 T1 T3 P3 T5 R5 V5 Y2 V3 W1 U4 V2 W3 W4 U5 Y5 Y3 U3 Y1 W5 V1 AA7 H3 AA5 L4 M3 G1 N4 M5 J3 J1 K1 L3 K3 U6 AA10 M1 N1 M2 L5 N3 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 86 R61 VTT1_5 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HA#[3..31] 3,5 RS#0 3,5 RS#1 3,5 RS#2 3,5 3,5 3,5 3,5 3,5 HA#[3..31] ABIT SL30 3,5 0.1UF 0.1UF 6 GMCHHCLK 17,18,22,30 PCIRST# 4 CPURST# 4,5 HLOCK# 4,5 DEFER# 4,5 HADS# 4,5 BNR# 4,5 BPRI# 4,5 DBSY# 4,5 DRDY# 4,5 HIT# 4,5 HITM# 4,5 HTRDY# BC73 BC72 Place close to GMCH 5 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 Host Interface RS#0 RS#1 RS#2 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HCLK RESET# CPURST# HLOCK# DEFER# ADS# BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY# GTLREFA GTLREFB U7A 4 AA1 AB2 AF2 AD4 AB1 AB3 AA3 AC4 AC1 AF3 AD1 AE3 AD2 AD3 AF1 AA4 AD6 AC3 AE1 AB6 AF4 AE5 AC8 AB5 AF5 AC6 AF6 AD11 AF8 AD8 AD5 AB7 AF7 AD7 AB8 AE7 AE9 AB9 AF9 AD10 AF12 AB11 AB10 AD9 AC10 AF10 AD14 AD12 AB12 AE11 AE15 AF11 AF13 AB14 AF14 AB13 AB15 AE13 AC14 AD13 AD15 AF16 AF15 AC12 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 HD#[0..63] 4 HD#[0..63] 3,5 DCLK_WR SM_RAS# SM_CAS# SM_WE# SM_BS0 SM_BS1 10 SM_CSB#[4..5] 9 SM_CSB#[0..3] 10 SM_CSA#[4..5] 9 SM_CSA#[0..3] 10 SM_CKE[4..5] 9 SM_CKE[0..3] VCC3SBY 9,10 SM_DQM[0..7] 6 9,10 9,10 9,10 9,10 9,10 9,10 SM_MAA[0..12] 9 SM_MAB#[4..7] 10 SM_MAC#[4..7] 3 40,1% C36 3 2 Date: Size B Title SM_WE# SM_MAA9 SM_CAS# SBA7 SM_BS0 SM_BS1 SM_MAA10 SM_MAA11 SM_MAA12 SM_RAS# BC190 X0.1UF BC188 X0.1UF 1 X0.1UF BC191 X0.1UF BC189 VCC3SBY X0.1UF X0.1UF X0.1UF BC194 X0.1UF BC195 R89 R88 SM_MAA9 SM_RAS# SM_MAA10 VCOREDET R_REFCLK R_BSEL#0 : HI=100 LO=66 Kicker : HI=NON-Cu LO=Cu : HI=133 LO=100/66 HI=133 LO=100 X10K X10K 8.2K 8.2K 8.2K 4 Wednesday, March 08, 2000 AB-SL30 V0.12 1 Sheet ABIT Computer Corp. 7 of 32 Rev A 29 29 SM/LM muxing strap , active low ALLZ : LO=ALLZ HI=Normal IOQ depth : HI=4 LO=1 Slot vs. Socket : HI=Socket LO=SC242 XOR chain : LO=XOR HI=Normal Host Freq FSB P-MOS Host Freq LM FREQ : R77 R68 R90 SM_WE# SM_CAS# Backside decouping , should be placed under chipset AGP signal field BC193 BC192 VDDQ Backside decouping , should be placed under chipset memory signal field SM_MD[0..63] 9,10 GMCH PART 1 SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SM_MD[0..63] D23 C23 D22 F21 E21 G20 F20 D20 F19 E19 D19 E18 B18 F18 G18 D17 A3 A1 C1 F2 G3 D6 C5 B4 D4 C2 D3 E4 F5 G4 J6 K5 A26 A25 B24 A24 B23 A23 C22 A22 D21 B21 A21 C20 B20 A20 C19 A19 A4 A2 B1 E1 G2 E6 D5 C4 B3 D2 E3 F4 F6 G5 H4 J4 Document Number SYSTEM MEMORY Solano SRCOMP SDQM0 SDQM1 SDQM2 SDQM3 SDQM4 SDQM5 SDQM6 SDQM7 SCLK RESVD SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 SRAS# SCAS# SWE# SCSB#0 SCSB#1 SCSB#2 SCSB#3 SCSB#4 SCSB#5 SCSA#0 SCSA#1 SCSA#2 SCSA#3 SCSA#4 SCSA#5 SBS0 SBS1 SMAC4 SMAC5 SMAC6 SMAC7 SMAB#4 SMAB#5 SMAB#6 SMAB#7 SMD0 SMD1 SMD2 SMD3 SMD4 SMD5 SMD6 SMD7 SMD8 SMD9 SMD10 SMD11 SMD12 SMD13 SMD14 SMD15 SMD16 SMD17 SMD18 SMD19 SMD20 SMD21 SMD22 SMD23 SMD24 SMD25 SMD26 SMD27 SMD28 SMD29 SMD30 SMD31 SMD32 SMD33 SMD34 SMD35 SMD36 SMD37 SMD38 SMD39 SMD40 SMD41 SMD42 SMD43 SMD44 SMD45 SMD46 SMD47 SMD48 SMD49 SMD50 SMD51 SMD52 SMD53 SMD54 SMD55 SMD56 SMD57 SMD58 SMD59 SMD60 SMD61 SMD62 SMD63 SM_CSB#[4..5] 22PF G7 D16 F15 A7 A6 A18 C17 B6 A5 F7 G10 D8 E8 E9 D7 C8 C7 U7B SMAA0 SMAA1 SMAA2 SMAA3 SMAA4 SMAA5 SMAA6 SMAA7 SMAA8 SMAA9 SMAA10 SMAA11 SMAA12 2 SM_CSB#[0..3] SM_CSA#[4..5] SM_CSA#[0..3] SM_CKE[4..5] SM_CKE[0..3] PR9 SM_DQM[0..7] SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CKE4 SM_CKE5 C16 D18 E16 F9 F8 D10 D9 B9 A8 SM_CSB#0 SM_CSB#1 SM_CSB#2 SM_CSB#3 SM_CSB#4 SM_CSB#5 2 B10 4 A10 6 C10 8 A9 10/8P4R B13 D11 D15 A17 D14 E14 E13 B17 1 3 5 7 RN36 RN38 1 3 5 7 1 3 5 7 D13 B16 F12 RN37 A16 2 B12 4 A12 6 C11 8 A11 D12 C13 10/8P4R E11 A13 B7 10/8P4R 2 B15 4 A15 6 C14 8 A14 SM_CSA#0 SM_CSA#1 SM_CSA#2 SM_CSA#3 SM_CSA#4 SM_CSA#5 SM_MAC#4 SM_MAC#5 SM_MAC#6 SM_MAC#7 SM_MAB#4 SM_MAB#5 SM_MAB#6 SM_MAB#7 SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8 SM_MAA9 SM_MAA10 SM_MAA11 SM_MAA12 SM_MAA[0..12] SM_MAB#[4..7] SM_MAC#[4..7] A B C D A B C D GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# ST0 ST1 ST2 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 ABIT SL30 40,1% PR15 5 PR14 U7C HCLK HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HUBREF HLSTB HLSTB# HCOMP VSYNC HSYNC RED GREEN BLUE DCLKREF IWASTE IREF DDDA DDCK LTVCK LTVDA LTVDATA0 LTVDATA1 LTVDATA2 LTVDATA3 LTVDATA4 LTVDATA5 LTVDATA6 LTVDATA7 LTVDATA8 LTVDATA9 LTVDATA10 LTVDATA11 BLANK# TVCLKIN/SL_STALL CLKOUT0 CLKOUT1 TVVSYNC TVHSYNC 4 SBA0/LMD31 SBA1/LMD25 SBA2/LDQM2 SBA3/LMD26 SBA4/LMD23 SBA5/LWE# SBA6/LMD22 SBA7/LGM_FREQ_SEL 4 Display Cache, Video, and HUB Interface Solano RBF#/LMD30 WBF# AGPREF GRCOMP OCLOCK RCLOCK ST0/LMD28 ST1/LDQM3 ST2/LMD29 ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# GFRAME#/LMA10 GDEVSEL#/LMD11 GIRDY#/LMD12 GTRDY#/LMA7 GSTOP#/LMA0 GPAR/LMA6 GREQ#/LMD27 GGNT# PIPE#/LMD24 GCBE#0/LMA3 GCBE#1/LMD10 GCBE#2/LMD13 GCBE#3/LRDS# GAD0/LDQM0 GAD1/LMD4 GAD2/LMD7 GAD3/LMD3 GAD4/LMD6 GAD5/LMD2 GAD6/LMD5 GAD7/LMD1 GAD8/LMD0 GAD9/LMA4 GAD10/LDQM1 GAD11/LMA2 GAD12/LMD8 GAD13/LMA5 GAD14/LMD9 GAD15/LMA1 GAD/16/LMA8 GAD17/LMD14 GAD18/LMA11 GAD19/LMD15 GAD20/LMA9 GAD21/LMD16 GAD22/LCS# GAD23/LMD17 GAD24/LCKE GAD25/LMD18 GAD26/LCAS# GAD27/LMD19 GAD28/LTCLK1 GAD29/LMD20 GAD30/LTCLK0 GAD31/LMD21 15PF/5%,MPO C61 OCLK = 0.5" RCLK = 1.5" 0.1UF BC89 15.1% AD24 AC24 AC23 M22 L23 U22 V23 Y23 AA24 R26 P26 P23 P21 P25 R24 AE26 AD25 AC26 H23 N21 T25 Y26 K26 J22 K25 J21 L24 J20 L26 K23 K22 M25 M24 M26 M21 N24 N22 N26 T26 T22 U24 T23 U26 T24 V24 U21 V25 V21 V26 W21 W24 W22 W26 Y21 AD26 AB24 J24 J26 OCLK R22 RCLK P22 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GAD[0..31] NOTE : 11 RBF# 11 WBF# 11 CONN_AGPREF GCBE#0 GCBE#1 GCBE#2 GCBE#3 GAD[0..31] 11 11 11 11 11 5 R251 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 22 FTD0 FTD1 FTD2 FTD3 FTD4 FTD5 FTD6 FTD7 FTD8 FTD9 FTD10 FTD11 Place as close as Possible to GMCH and via straight to VSS plane 174,1% PR13 AB22 AB25 AB23 AB26 AA22 AA26 Y22 Y25 F22 H24 H26 H25 G24 F24 E26 E25 D26 D25 D24 C26 H21 G25 F26 H20 AF22 AF23 AD22 AE22 AE23 AE24 Y20 AD23 AA18 AB18 AB21 AA20 AD16 AF17 AE17 AD17 AF18 AD18 AF20 AD20 AC20 AF21 AE21 AD21 AB19 AC18 AE19 AF19 AC16 AB17 FTD[0..11] HL[0..10] SBA[0..7] SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 HLSTB HLSTB# GMCH_3V66 CRT_VSYNC CRT_HSYNC VID_RED VID_GREEN VID_BLUE DOTCLK 3VDDCDA 3VDDCCL 3VFTSCL 3VFTSDA FTBLNK# SL_STALL FTCLK0 FTCLK1 FTVSYNC FTHSYNC FTD[0..11] HL[0..10] SBA[0..7] 11 11 11 11 11 11 11 11 301,1% PR17 3 Place as close as Possible to GMCH and via straight to VSS plane 0.01UF BC90 AF24 AE25 K20 Y24 L21 M23 U25 N25 R21 U20 U23 W20 B2 B5 B8 B11 B14 B19 B22 B25 E2 F10 F14 F17 G6 G8 G19 H2 H5 H7 AA21 Y7 E23 AF26 AF25 W6 Y9 Y18 AA6 AA8 AA11 AA13 AA15 AA17 AA19 AB16 AB20 AC22 AD19 C25 E24 F23 G22 J7 K6 M6 P6 T6 V7 G26 VDDQ VCC3SBY VCC1_8 301,1% PR16 VCC1_8 Place R as Close as possible to GMCH VCC1_8 40,1% 12 12 10PF C58 Do Not Stuff C Place Site w/in 0.5" of clock ball(AA21) PR18 6 17 17 17 17 17 6 17 17 17 17 17 17 17 17 17 17 17 12 11 3 U7D GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 Power and Ground Solano GND GND VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 VCC_1.8 2 AB4 E7 AC2 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC25 AE2 AE4 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 B26 C3 C6 C9 C12 C15 C18 C21 C24 D1 E5 E10 E12 E15 E17 E20 E22 F1 F3 F11 F13 T21 U2 U7 K24 V4 V6 V20 V22 W2 W7 W23 W25 Y4 Y6 Y8 Y10 Y17 Y19 AA2 AA9 AA12 AA14 AA16 Date: Size B Title U7E 1K,1% 82,1% GMCH PART 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 1 Sheet ABIT Computer Corp. 600PF N2 N6 N11 N12 N13 N14 N15 N16 N23 AA23 F16 F25 G9 G17 G21 G23 P24 H6 H22 J2 J5 J23 J25 K4 K7 K21 L2 L6 L11 L12 L13 L14 AA25 P4 8 GMCH_AGPREF 11 1K,1% PR23 VDDQ GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PR22 C72 600PF C69 Solano GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PR24 82,1% PR21 P11 P12 P13 P14 P15 P16 R2 R6 R11 R12 R13 R14 R15 R16 R23 R25 T4 T11 T12 T13 T14 T15 T16 L15 L16 L22 M4 M11 M12 M13 M14 M15 M16 L25 1 of 32 Rev A A B C D 1 2 3 4 SM_MAB#[4..7] SM_CKE[0..3] 7 SM_BS0 SM_BS1 7,10 7,10 CH6-12 ABIT SL30 6,10,13,22,25,30 SMBDATA 6,10,13,22,25,30 SMBCLK SM_RAS# SM_CAS# 7,10 7,10 SM_WE# 7,10 7 SM_CSB#[0..3] 7 SM_CSA#[0..3] MEMCLK[0..7] 6 7,10 SM_DQM[0..7] 7 7,10 SM_MD[0..63] 7,10 SM_MAA[0..12] A A SMBDATA SMBCLK SM_BS1 SM_BS0 SM_CAS# SM_RAS# SM_WE# SM_CSB#[0..3] SM_CSA#[0..3] SM_CKE[0..3] MEMCLK[0..7] SM_DQM[0..7] SM_MAB#[4..7] SM_MD[0..63] SM_MAA[0..12] SMBDATA SMBCLK MEMCLK2 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD21 SM_MD22 SM_MD23 SM_CKE1 SM_MD20 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_CSB#0 SM_DQM2 SM_DQM3 MEMCLK0 SM_MAA0 SM_MAA2 SM_MAA4 SM_MAA6 SM_MAA8 SM_MAA10 SM_BS1 SM_WE# SM_DQM0 SM_DQM1 SM_CSA#0 SM_MD14 SM_MD15 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD0 SM_MD1 SM_MD2 SM_MD3 VCC3SBY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DIMM1 B DIMM168 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VDD WE#/WE0# DQM0 DQM1 CS0# DU/OE0# VSS A0 A2 A4 A6 A8 A10/AP BA1/A12 VDD VDD CLK0/DU VSS DU/OE2# CS2# DQM2 DQM3 DU/WE2# VDD CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC VREF/DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2/NC NC WP SDA SCL VDD B VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VDD CAS#/DU DQM4 DQM5 CS1# RAS#/DU VSS A1 A3 A5 A7 A9 BA0/A11 A11/A13 VDD CLK1/DU A12/DU VSS CKE0/DU CS3# DQM6 DQM7 A13/DU VDD CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC VREF/DU REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3/NC NC SA0 SA1 SA2 VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VCC3SBY SM_CSB#2 SM_DQM2 SM_DQM3 SM_CKE0 SM_CSB#1 SM_DQM6 SM_DQM7 C SMBDATA SMBCLK MEMCLK6 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD60 SM_MD61 SM_MD62 SM_MD63 MEMCLK3 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD21 SM_MD22 SM_MD23 SM_CKE3 SM_MD20 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD53 SM_MD54 SM_MD55 SM_MD52 SM_MD16 SM_MD17 SM_MD18 SM_MD19 MEMCLK4 MEMCLK1 SM_MAA12 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MAA0 SM_MAA2 SM_MAB#4 SM_MAB#6 SM_MAA8 SM_MAA10 SM_BS1 SM_WE# SM_DQM0 SM_DQM1 SM_CSA#2 SM_MD14 SM_MD15 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MAA1 SM_MAA3 SM_MAA5 SM_MAA7 SM_MAA9 SM_BS0 SM_MAA11 SM_CAS# SM_DQM4 SM_DQM5 SM_CSA#1 SM_RAS# SM_MD46 SM_MD47 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD32 SM_MD33 SM_MD34 SM_MD35 C VCC3SBY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DIMM2 DIMM168 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VDD WE#/WE0# DQM0 DQM1 CS0# DU/OE0# VSS A0 A2 A4 A6 A8 A10/AP BA1/A12 VDD VDD CLK0/DU VSS DU/OE2# CS2# DQM2 DQM3 DU/WE2# VDD CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC VREF/DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2/NC NC WP SDA SCL VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VDD CAS#/DU DQM4 DQM5 CS1# RAS#/DU VSS A1 A3 A5 A7 A9 BA0/A11 A11/A13 VDD CLK1/DU A12/DU VSS CKE0/DU CS3# DQM6 DQM7 A13/DU VDD CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC VREF/DU REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3/NC NC SA0 SA1 SA2 VDD D 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 D VCC3SBY Date: Size B Title R28 2.2K VCC3SBY Wednesday, March 08, 2000 E Sheet 9 DM_SA_PU ABIT Computer Corp. AB-SL30 V0.12 Document Number DIMM 1 & 2 MEMCLK7 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD53 SM_MD54 SM_MD55 SM_MD52 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_CKE2 SM_CSB#3 SM_DQM6 SM_DQM7 MEMCLK5 SM_MAA12 SM_MAA1 SM_MAA3 SM_MAB#5 SM_MAB#7 SM_MAA9 SM_BS0 SM_MAA11 SM_CAS# SM_DQM4 SM_DQM5 SM_CSA#3 SM_RAS# SM_MD46 SM_MD47 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD32 SM_MD33 SM_MD34 SM_MD35 E of 10 32 Rev A 1 2 3 4 1 2 3 4 SM_MAC#[4..7] SM_CKE[4..5] 7 SM_BS0 SM_BS1 7,9 7,9 ABIT SL30 A 9 DM_SA_PU 6,9,13,22,25,30 SMBDATA 6,9,13,22,25,30 SMBCLK SM_RAS# SM_CAS# 7,9 7,9 SM_WE# 7,9 7 SM_CSB#[4..5] 7 SM_CSA#[4..5] MEMCLK[8..11] 6 7,9 SM_DQM[0..7] 7 7,9 SM_MD[0..63] 7,9 SM_MAA[0..12] A SMBDATA SMBCLK SM_BS1 SM_BS0 SM_CAS# SM_RAS# SM_WE# SM_CSB#[4..5] SM_CSA#[4..5] SM_CKE[4..5] MEMCLK[8..11] SM_DQM[0..7] SM_MAC#[4..7] SM_MD[0..63] SM_MAA[0..12] SMBDATA SMBCLK MEMCLK10 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD21 SM_MD22 SM_MD23 SM_CKE5 SM_MD20 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_CSB#4 SM_DQM2 SM_DQM3 MEMCLK8 SM_MAA0 SM_MAA2 SM_MAC#4 SM_MAC#6 SM_MAA8 SM_MAA10 SM_BS1 SM_WE# SM_DQM0 SM_DQM1 SM_CSA#4 SM_MD14 SM_MD15 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD0 SM_MD1 SM_MD2 SM_MD3 B B VCC3SBY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DIMM3 DIMM168 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VDD WE#/WE0# DQM0 DQM1 CS0# DU/OE0# VSS A0 A2 A4 A6 A8 A10/AP BA1/A12 VDD VDD CLK0/DU VSS DU/OE2# CS2# DQM2 DQM3 DU/WE2# VDD CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC VREF/DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2/NC NC WP SDA SCL VDD VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VDD CAS#/DU DQM4 DQM5 CS1# RAS#/DU VSS A1 A3 A5 A7 A9 BA0/A11 A11/A13 VDD CLK1/DU A12/DU VSS CKE0/DU CS3# DQM6 DQM7 A13/DU VDD CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC VREF/DU REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3/NC NC SA0 SA1 SA2 VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VCC3SBY C C MEMCLK11 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD53 SM_MD54 SM_MD55 SM_MD52 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_CKE4 SM_CSB#5 SM_DQM6 SM_DQM7 MEMCLK9 SM_MAA12 SM_MAA1 SM_MAA3 SM_MAC#5 SM_MAC#7 SM_MAA9 SM_BS0 SM_MAA11 SM_CAS# SM_DQM4 SM_DQM5 SM_CSA#5 SM_RAS# SM_MD46 SM_MD47 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD32 SM_MD33 SM_MD34 SM_MD35 D D Date: Size B Title DIMM 3 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet ABIT Computer Corp. E 10 of 32 Rev A 1 2 3 4 1 2 3 4 1 3 5 7 1 3 5 7 ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# RBF# CH6-18 A 1 3 5 7 SBA4 SBA5 SBA6 SBA7 ABIT SL30 1 3 5 7 SBA0 SBA1 SBA2 SBA3 1 3 5 7 ST0 ST1 ST2 1 3 5 7 1 3 5 7 GFRAME# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# WBF# 1 3 5 7 GIRDY# GDEVSEL# GPERR# GSERR# A 8.2K/8P4R 8.2K/8P4R RN45 2 4 6 8 8.2K/8P4R RN47 2 4 6 8 8.2K/8P4R RN46 2 4 6 8 8.2K/8P4R RN44 2 4 6 8 8.2K/8P4R RN43 2 4 6 8 8.2K/8P4R RN42 2 4 6 8 8.2K/8P4R RN48 2 4 6 8 RN49 2 4 6 8 VDDQ AGPUSBP AGP_OC# GIRDY# 8 ADSTB0 GCBE#1 GAD[0..31] SBA[0..7] 8 8 8 GMCH_AGPREF 8 8 8 GDEVSEL# GCBE#2 ADSTB1 SBSTB ST0 ST2 RBF# 8 8 8 8 8 8 14,15,30 PIRQ#B 6 AGPCLK_CONN 8 GREQ# 19 19 B B SBA[0..7] GAD[0..31] GAD1 GAD5 GAD3 ADSTB0 GAD7 GAD10 GAD8 GAD14 GAD12 GSERR# GPERR# GDEVSEL# GIRDY# GAD17 GAD21 GAD19 ADSTB1 GAD23 GAD27 GAD25 GAD31 GAD29 SBA4 SBA6 SBA2 SBSTB SBA0 ST0 ST2 RBF# GREQ# V3SB VCC3_3 VCC5 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 C OVRCNT# 5V_A 5V_B USB+ GND_K INTB# CLK REQ#/DQ27 VCC3.3_F ST0/DQ28 ST2/DQ29 RBF#/DQ30 GND_L RESV_H SBA0/DQ31 VCC3.3_G SBA2/DQM2 SB_STB GND_M SBA4/DQ23 SBA6/DQ22 RESV GND_N 3.3VAUX1 VCC3.3_H AD31/DQ21 AD29/DQ20 VCC3.3_I AD27/DQ19 AD25/DQ18 GND_O AD_STB1 AD23/DQ17 VDDQ_F AD21/DQ16 AD19/DQ15 GND_P AD17/DQ14 C/BE2#/DQ13 VDDQ_G IRDY#/DQ12 3.3VAUX2 GND_Q RESV_K VCC3.3_J DEVSEL#/DQ11 VDDQ_H PERR# GND_R SERR# C/BE1#/DQ10 VDDQ_I AD14/DQ9 AD12/DQ8 GND_S AD10/DQM1 AD8/DQ0 VDDQ_J AD_STB0 AD7/DQ1 GND_T AD5/DQ2 AD3/DQ3 VDDQ_K AD1/DQ4 VREF_CG AGP1 C AGP4XU_20 12V TYPEDET# RESV_A USBGND_A INTA# RST# GNT# VCC3.3_A DQM3/ST1 RESV_B DQ24/PIPE# GND_B WBF# DQ25/SBA1 VCC3.3_B DQ26/SBA3 SB_STB# GND_C WE#/SBA5 M_FREQ_SEL/SBA7 RESV_C GND_D RESV_D VCC3.3_C TCLK0/AD30 TCLK1/AD28 VCC3.3_D CAS#/AD26 AD24 GND_E AD_STB1# RAS#/C/BE3# VDDQ_A A0/AD22 A9/AD20 GND_F A11/AD18 A8/AD16 VDDQ_B A10/FRAME# RESV_E GND_G RESV_F VCC3.3_E A7/TRDY# CS#/STOP# PME# GND_H A6/PAR A1/AD15 VDDQ_C A5/AD13 A2/AD11 GND_I A4/AD9 A3/C/BE0# VDDQ_D AD_STB0# DQ5/AD6 GND_J DQ6/AD4 DQ7/AD2 VDDQ_E DQM0/AD0 VREF_GC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 GAD0 GAD4 GAD2 ADSTB0# GAD6 GAD9 GAD13 GAD11 GPAR GAD15 GTRDY# GSTOP# GFRAME# GAD18 GAD16 GAD22 GAD20 ADSTB1# GAD26 GAD24 GAD30 GAD28 SBA5 SBA7 SBA3 SBSTB1# WBF# SBA1 PIPE# ST1 GGNT# 2.2K R106 VCC12 VCC12 VDDQ D D 19 8 8 8 8 8 12,14,15,23 8 8 8 8 8 8 8 Date: Size B Title CONN_AGPREF 8 ADSTB0# GCBE#0 GPAR GTRDY# GSTOP# PCI_PME# GFRAME# ADSTB1# GCBE#3 SBSTB# WBF# PIPE# ST1 14,15,30 14,15,30 8 AGPUSBN PIRQ#A PCI_RST# GGNT# 27 TYPEDET# AGP Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet ABIT Computer Corp. Q13 2N7002 CON_AGPREF Place close to GMCH 11 200,1% PR19 301,1% PR20 VDDQ E of 32 Rev A 1 2 3 4 A B C D GPIO23 GPIO27 GPIO28 18 30 30 5 ICH_IRQ#E ICH_IRQ#F ICH_IRQ#G ICH_IRQ#H P66DET S66DET GPI8 EXTSMI# LPC_PME# 30 30 30 30 18 18 30 25 22,30 ABIT SL30 PCI_REQ#A PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# ICHRST# PLOCK# PAR SERR# PERR# PCI_PME# C_BE#0 C_BE#1 C_BE#2 C_BE#3 AD[0..31] 30 6 14,15,30 C101 14,15,30 14,15,30 10PF 14,15,30 NPOP 14,15,30 30 14,15,30 14,15 14,15,30 14,15,30 11,14,15,23 14,15 14,15 14,15 14,15 14,15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 N3 N2 N1 M4 Y11 AA11 Y14 W14 AB15 A15 D14 C14 L1 B14 A14 AB14 AA14 M3 L2 W11 V3 AB7 W8 V4 W1 AA15 AA7 W2 W7 Y7 Y15 AA3 AB6 Y8 AA9 AA4 AB4 Y4 W5 W4 Y5 AB3 AA5 AB5 Y3 W6 W3 Y6 Y2 AA6 Y1 V2 AA8 V1 AB8 U4 W9 U3 Y9 U2 AB9 U1 W10 T4 Y10 T3 AA10 I6519163 U12A ICH2_5 AD[0..31] E14 E15 E16 E17 E18 F18 G18 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8 PIRQ#E/GPI2 PIRQ#F/GPI3 PIRQ#G/GPI4 PIRQ#H/GPI5 GPI6 GPI7 GPI8 GPI12 GPI13 GPO18 GPO19 GPO20 GPO21 GPOD22 GPO23 GPIOD27 GPIOD28 REQ#A/GPI0 GNT#A/GPO16 PCICLK FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PERR# PCI_PME# C_BE#0 C_BE#1 C_BE#2 C_BE#3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 D2 D10 E5 K19 L19 P5 V9 H18 J18 P18 R18 R5 T5 U5 V5 V6 V7 V8 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 VCC3_3_18 VCC3_3_19 VCC3_3_20 VCC1_8 V3SB V3SB V3SB U18 T18 VCCPS1 VCCPS2 VCCA VCC1_8 F5 G5 VCCPX1 VCCPX2 VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 VCC1_8_5 VCC1_8_6 4 V17 V18 VCCUSB1 VCCUSB2 VCC3_3 V1_8SB V1_8SB 3 V14 V15 V16 VCCCS1 VCCCS2 VCCCS3 5 H5 J5 VCCAX1 VCCAX2 LAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GNT#0 GNT#1 GNT#2 GNT#3 GNT#4 GNT#B/GPO17/GNT#5 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 REQ#B/GPI1/REQ#5 IRQ14 IRQ15 APICCLK APICD1 APICD0 SERIRQ PIRQ#A PIRQ#B PIRQ#C PIRQ#D HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HLSTB HLSTB# HCOMP HUBREF A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGOD 4 3 A1 VSS0 A10 VSS1 A2 VSS2 A21 VSS3 A22 VSS4 AA1 VSS5 AA2 VSS6 AA21 VSS7 AA22 VSS8 AB1 VSS9 AB2 VSS10 AB21 VSS11 AB22 VSS12 B1 VSS13 B10 VSS14 B2 VSS15 B21 VSS16 B22 VSS17 B3 VSS18 B9 VSS19 C2 VSS20 C3 VSS21 C4 VSS22 C9 VSS23 D3 VSS24 D5 VSS25 D6 VSS26 D7 VSS27 D8 VSS28 D9 VSS29 E6 VSS30 E7 VSS31 E8 VSS32 E9 VSS33 J10 VSS34 J11 VSS35 J12 VSS36 J13 VSS37 J14 VSS38 J9 VSS39 K1 VSS40 K10 VSS41 K11 VSS42 K12 VSS43 K13 VSS44 K14 VSS45 K9 VSS46 L10 VSS47 L11 VSS48 L12 VSS49 L13 VSS50 L14 VSS51 L9 VSS52 M9 VSS53 M10 VSS54 M11 VSS55 M12 VSS56 M13 VSS57 M14 VSS58 N9 VSS59 N10 VSS60 N11 VSS61 N12 VSS62 N13 VSS63 N14 VSS64 P9 VSS65 P10 VSS66 P11 VSS67 P12 VSS68 P13 VSS69 P14 VSS70 2 G3 H2 G2 G1 H1 F3 F2 F1 M2 M1 R4 T2 R1 L4 R2 R3 T1 AB10 P4 L3 F21 C16 N20 N19 P22 N21 P1 P2 P3 N4 A4 B5 A5 B6 B7 A8 B8 A9 C8 C6 C7 C5 A6 A7 A3 B4 D11 A12 R22 A11 C12 C11 B11 B12 C10 B13 C13 A13 2 RN69 1 3 5 7 RN68 1 3 5 7 Date: Size B Title 22/8P4R 2 4 6 8 22/8P4R 2 4 6 8 25 25 25 25 14 14 15 14,30 14,30 15,30 30 30 30 18 18 6 4 4 22,30 30 30 30 30 8 8 4 4 4 4 4,18 4 4 4 4 22,30 22,30 4 8 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number Sheet 1 12 of 32 301,1% 0.01UF Place as close as Possible to ICH and via straight to VSS plane PR26 BC119 301,1% PR25 VCC1_8 PR27 Place R as Close as 40,1% possible to ICH VCC1_8 ABIT Computer Corp. LAN_TXD1 25 LAN_TXD2 25 LAN_CLK 25 LAN_RSTSYNC 25 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 PGNT#0 PGNT#1 PGNT#2 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5 IRQ14 IRQ15 APICCLK_ICH APICD1 APICD0 SERIRQ ICH_IRQ#A ICH_IRQ#B ICH_IRQ#C ICH_IRQ#D HLSTB HLSTB# A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# KBRST# A20GATE CPU_PWGD HL[0..10] ICH2 PART 1 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL[0..10] 1 Rev A A B C D 1 2 3 4 ABIT SL30 A A 6 USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBOC#0-1 USBOC#2-3 EE_CS EE_DIN EE_DOUT EE_SHCLK 19 19 19 19 19 19 19 19 19 19 25 25 25 25 VCC5 ICH_CLK14 BATTERY BAT1 JP1 10M Y2 10M C96 RN71 15/8P4R 1 2 3 4 5 6 7 8 560K R271 CP1 22 18,22 18,22 18,22 18,22 18,22 25,29 20,25 20,25 20,25,29 X18PF 20,25,30 25,30 25,29 C88 6 6 560K 47PF/8P4C R164 OVT# SLP_S3# SLP_S5# PWROK GPIO25 22 PWRBTN# 23,30 ICH_RI# 22 RSMRST# 22,30 6,22,28 28 22,26 30 C LDRQ#0 LAD0 LAD1 LAD2 LAD3 LFRAME# AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 ICH_SPKR VBIAS RTCX1 RTCX2 RTCRST# USBCLK ICH_3V66 22 SUSCLK 6,9,10,22,25,30 SMBDATA 6,9,10,22,25,30 SMBCLK 30 SMBALERT# 22,26 CASEOPEN# RN70 15/8P4R 1 2 3 4 5 6 7 8 18PF X10P 18PF 32.768KHZ R149 10 C102 B 2200PF C110 1.0UF C113 1.0UF C104 R141 C103 R162 1K SS12/SMD CCM0S 100 R187 3 2 1 15K R174 1K R181 D12 R134 Q16 2N3904 B 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 1 3 5 7 C 1 3 5 7 47PF/8P4C CP2 K4 K3 J4 J3 W19 Y20 Y21 W20 W17 Y18 AB19 AA19 W18 Y19 AB20 AA20 Y12 W12 AB13 AB12 AB11 Y13 W13 V22 P19 R19 P21 Y22 W22 N22 T21 U22 T22 T20 M19 P20 D4 W15 V21 AA13 W16 AB18 R20 Y16 W21 AA17 R21 Y17 AA18 AA16 AB16 AB17 T19 ICH2_5 EE_CS EE_DIN EE_DOUT EE_SHCLK OC#0 OC#1 OC#2 OC#3 USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1 AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 SPKR VBIAS RTCX1 RTCX2 RTCRST# CLK14 CLK48 CLK66 GPIO25 GPIO24 THRM# SLP_S3# SLP_S5# PWROK RSM_PWROK PWRBTN# RI# RSMRST# SUS_STAT# SUSCLK SMBDATA SMBCLK SMBALTER#/GPI11 INTRUDER# U12B VCCRTC U21 VCCRTC D12 D13 VCPU1 VCPU2 VCC5SBY M20 K2 D D SMLINK0 SMLINK1 VRMPWRGD TP0 FS0 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDCS#1 SDCS#1 PDSC#3 SDCS#3 V5R1 V5R2 V19 V5R_SUS U19 V20 B15 U20 AA12 D18 B19 D19 A20 C20 C21 D22 E20 D21 C22 D20 B20 C19 A19 C18 A18 H19 H22 J19 J22 K21 L20 M21 M22 L22 L21 K22 K20 J21 J20 H21 H20 G22 B18 F22 B17 G19 D17 G21 C17 G20 A17 F20 F19 E22 A16 D16 B16 18 15,25,30 15,25,30 27 18 18 18 18 18 18 18 18 18 18 18 18 D8 R129 18 18 18 18 18 4 R324 SS12/SMD 1K 1K VCC3_3 VCC5 Wednesday, March 08, 2000 E Sheet ABIT Computer Corp. AB-SL30 V0.12 Document Number ICH2 PART 2 SDD[0..15] SMLINK0 SMLINK1 VRM_PWRGD PDD[0..15] SDA[0..2] PDREQ SDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY Date: Size B Title PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDD[0..15] SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD[0..15] PDA[0..2] PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 SDA[0..2] 0.1UF BC197 PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA[0..2] 0.1UF 1.0UF E21 C15 E19 D15 BC125 C91 VCMOS E 13 V3SB of 32 Rev A 1 2 3 4 1 2 3 4 SERR# AD[0..31] ABIT SL30 12,15 C_BE#[0..3] 12,15 15,30 ACK64# 12,15,30 12,15,30 PLOCK# 12,15,30 PERR# 12,15,30 DEVSEL# IRDY# PREQ#0 12,30 12,15,30 PCLK_1 6 11,15,30 PIRQ#B 15,30 PIRQ#D ACK64# AD1 AD5 AD3 AD8 AD7 AD12 AD10 C_BE#1 AD14 PERR# AD17 C_BE#2 AD21 AD19 C_BE#3 AD23 AD27 AD25 AD31 AD29 A C_BE#[0..3] AD[0..31] A B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 VCC12- VCC5 VCC3_3 PCI1 PCI_CON_32BIT AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT#1 RESERVED PRSNT#2 GND GND RESERVED GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE#3 AD23 GND AD21 AD19 +3.3V AD17 C/BE#2 GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#1 AD14 GND AD12 AD10 GND B C/BE#0 +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V(I/O) RESERVED GND GND RESERVED RST# +5V(I/O) GNT GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3 AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 B A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 VCC12 VCC5 AD2 AD0 AD6 AD4 C_BE#0 AD9 AD13 AD11 AD15 AD18 AD16 AD22 AD20 AD24 R_AD16 AD28 AD26 AD30 V3SB VCC3_3 PGNT#0 REQ64#1 PAR STOP# TRDY# FRAME# R133 100 30 C 12,15 12,15,30 12,15,30 12,15,30 AD16 11,12,15,23 11,15,30 12 PCI_RST# PCI_PME# 11,15,30 15,30 PIRQ#A PIRQ#C C 12,30 6 PREQ#1 PCLK_2 ACK64# AD1 AD5 AD3 AD8 AD7 AD12 AD10 C_BE#1 AD14 SERR# PLOCK# PERR# DEVSEL# IRDY# AD17 C_BE#2 AD21 AD19 C_BE#3 AD23 AD27 AD25 AD31 AD29 PIRQ#C PIRQ#A D B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 VCC5 VCC12- VCC3_3 D PCI2 PCI_CON_32BIT AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT#1 RESERVED PRSNT#2 GND GND RESERVED GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE#3 AD23 GND AD21 AD19 +3.3V AD17 C/BE#2 GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#1 AD14 GND AD12 AD10 GND Date: Size B Title A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 PIRQ#B PIRQ#D AD2 AD0 AD6 AD4 C_BE#0 AD9 AD13 AD11 PAR AD15 STOP# TRDY# FRAME# AD18 AD16 AD22 AD20 AD24 R_AD17 AD28 AD26 PCI_PME# AD30 PCI_RST# VCC3_3 V3SB Wednesday, March 08, 2000 E Sheet 14 REQ64#2 of R142 AD17 100 PGNT#1 ABIT Computer Corp. AB-SL30 V0.12 Document Number PCI 1 & 2 C/BE#0 +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V(I/O) RESERVED GND GND RESERVED RST# +5V(I/O) GNT GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3 AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 VCC12 VCC5 E 30 12 32 Rev A 1 2 3 4 1 2 3 4 SERR# AD[0..31] ABIT SL30 12,14 C_BE#[0..3] 12,14 14,30 ACK64# 12,14,30 12,14,30 PLOCK# 12,14,30 PERR# 12,14,30 DEVSEL# IRDY# PREQ#2 12,14,30 PCLK_3 6 12,30 14,30 PIRQ#D 11,14,30 PIRQ#B A A C_BE#[0..3] AD[0..31] ACK64# AD1 AD5 AD3 AD8 AD7 AD12 AD10 C_BE#1 AD14 PERR# AD17 C_BE#2 AD21 AD19 C_BE#3 AD23 AD27 AD25 AD31 AD29 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 VCC12- VCC5 VCC3_3 PCI3 PCI_CON_32BIT AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT#1 RESERVED PRSNT#2 GND GND RESERVED GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE#3 AD23 GND AD21 AD19 +3.3V AD17 C/BE#2 GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE#1 AD14 GND AD12 AD10 GND B C/BE#0 +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +5V(I/O) RESERVED GND GND RESERVED RST# +5V(I/O) GNT GND PME# AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3 AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 B A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 VCC12 VCC5 AD2 AD0 AD6 AD4 C_BE#0 AD9 AD13 AD11 AD15 AD18 AD16 AD22 AD20 AD24 R_AD18 AD28 AD26 AD30 V3SB VCC3_3 PGNT#2 REQ64#3 PAR SMLINK0 SMLINK1 STOP# TRDY# FRAME# R148 100 30 C 12,14 13,25,30 13,25,30 12,14,30 12,14,30 12,14,30 AD18 11,12,14,23 11,14,30 12 PCI_RST# PCI_PME# 14,30 11,14,30 PIRQ#C PIRQ#A C D D Date: Size B Title PCI 3 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet ABIT Computer Corp. E 15 of 32 Rev A 1 2 3 4 A B C D LEFT BLANK ABIT Computer Corp. Date: Size B Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 16 of 32 Rev A E Sheet 1 1 ABIT SL30 Title 2 2 This Page Is Left Blank. E 3 D 3 C 4 B 4 A 1 2 3 4 ABIT SL30 VID_BLUE 3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC 3VFTSDA 3VFTSCL 8 8 8 8 8 8 8 FTD[0..11] VID_GREEN 8 8 VID_RED 8 A 7,18,22,30 PCIRST# A FTD[0..11] 3.3PF C43 FTD9 FTD10 FTD11 FTD6 FTD7 FTD8 FTD3 FTD4 FTD5 FTD0 FTD1 FTD2 3 4 7 8 11 14 17 18 21 22 1 13 1 3.3PF C47 1 3.3PF C50 3VHTPLG 75,1% PR10 75,1% PR11 75,1% PR12 1 X10PF C45 X10PF B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B X_VBUS FTD0 FTD1 FTD2 GND(1) FTD3 FTD4 FTD5 GND(2) FTD6 FTD7 FTD8 GND(3) FTD9 FTD10 FTD11 VCC(1) VCC(3) VCC18(3) VCC3(3) GND(5) VL1 VCC 24 1B1 2 1A1 1B2 5 1A2 1B3 6 1A3 1B4 9 1A4 1B5 10 1A5 SSOP24 2B1 15 2A1 2B2 16 2A2 2B3 19 2A3 2B4 20 2A4 2B5 23 2A5 BEA# BEB# GND 12 U8 QST3384 BEAD 2 VFB1 5VDDCDA 5VDDCCL 5VHSYNC 5VVSYNC 5VHTPLG 5VFTSDA 5VFTSCL FTCLK0 FTCLK1 VCC3(1) FTBLNK# FTHSYNC FTVSYNC SL_STALL VCC18(1) 3VFTSCL 3VFTSDA 3VHTPLG VCC(2) PCIRST# VCC3(2) GND(4) VCC18(2) 5VHTPLG 5VFTSDA 5VFTSCL VCC(4) 4.7K 4.7K A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 R96 R97 0.22UF0.22UF BC224 BC225 8 7 6 5 BEAD 3 2 1 C C PAC-VGA201/QSOP DDC_OUT1 DDC_OUT2 SYNC_IN1 SYNC_OUT1 SYNC_IN2 SYNC_OUT2 SD1 SD2 VCC3_3 VCC1_8 VCC5 VCC2 POWER_UP GND VIDEO_3 VIDEO_2 VIDEO_1 VCC1 VCC3 U28 0.22UF BC223 4 C46 X10PF C49 VCC5 VCC1_8 2 VFB2 BEAD 2 VFB3 B 9 10 11 12 13 14 15 16 2 4 6 8 33 RN41 2.2K/8P4R 1 3 5 7 22PF C55 R85 4.7K R95 10PF C54 D 0.1UF BC86 1N4148 D4 22PF C57 R87 R322 R321 D VCC5 33 10 10 Date: B Size Title 10PF C56 1K R73 2 C53 BEAD ABIT Computer Corp. 8 8 8 8 8 8 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet 17 of VGA_CONN VGA1 FTBLNK# FTHSYNC FTVSYNC SL_STALL 6 1 11 7 2 12 8 3 13 9 4 14 10 5 15 E FTCLK0 FTCLK1 DDCCL MON2PU VS BV HS GV DDCDA RV MONOPU VIDEO BUS & CONNECTOR 1K 0.22UF FB11 BC68 FUSE_1.0A R84 VCC5 F5 10PF 10PF C48 1 32 A Rev 1 2 3 4 A B C D LAD0 LAD1 LAD2 13,22 13,22 13,22 8 ABIT SL30 GPIO23 12 7,17,22,30 PCIRST# 8 R206 0.1UF BC173 7 8.2K VCC3_3 7 0 R207 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FWH32 VPP RST# FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0 FWH1 FWH2 GND U23 FWH 6 VCC CLK FGPI4 IC GNDA VCCA GND VCC INIT# FWH4 RFU RFU RFU RFU RFU FWH3 6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC3_3 R211 0.1UF BC175 5 8.2K 0.1UF BC177 5 LAD3 INIT# LFRAME# PCLK_8 0.1UF BC178 13,22 4,12 13,22 6 SDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 13 13 13 13 13 12 4 13 25 SDA[0..2] SDCS#1 IDEACTS# VCC3_3 SDD[0..15] 13 PDCS#1 IDEACTP# VCC3_3 PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 IDERST# PDA[0..2] PDD[0..15] 13 13 25 13 13 13 13 13 12 30 13 13 4 R75 IDERST# SDA[0..2] SDD[0..15] R83 IDERST# PDA[0..2] PDD[0..15] 4.7K 3 4.7K R76 VCC3_3 4.7K 4.7K R79 VCC3_3 3 47PF C44 47PF C51 SDA2 SDA1 SDA0 R112 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 PDA2 PDA1 PDA0 R113 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 IDE Date: Size B Title 33 33 IDE1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IDE2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number Sheet 18 of 13 SDCS#3 13 12 12 1 1 S66DET PDCS#3 P66DET ABIT Computer Corp. 15K R70 470 R69 15K R80 470 R82 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 FWH & UDAM100 IDE 1-2 PIN_2X20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PIN_2X20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 32 Rev A A B C D A B C D AGPUSBN AGPUSBP 11 11 8 ABIT SL30 CNRUSBN CNRUSBP 25 25 USBOC#2-3 13 USBP2N USBP2P USBP3N USBP3P AGP_OC# 13 13 13 13 CNR_OC# 11 USBP0N USBP0P USBP1N USBP1P USBOC#0-1 25 13 13 13 13 13 8 X0 X0 7 RN73 15K/8P4R R269 R268 R266 R267 330K 330K V3SB RN72 15K/8P4R 7 1 3 5 7 2 4 6 8 1 3 5 7 2 4 6 8 F7 VCC5DUAL F4 VCC5DUAL 6 FUSE_1.0A FUSE_1.0A 6 C122 470PF + EC39 100UF 2 BEAD 1 470PF FB25 BC4 BEAD FB8 + EC18 2 100UF 1 5 5 1 FB29 1 FB24 1 1 4 BEAD 2 FB28 BEAD 2 FB23 4 1 BEAD 2 FB27 BEAD 2 FB22 1 1 1 BEAD 2 FB26 BEAD 2 FB21 3 BEAD 2 BEAD 2 3 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 Date: Size B Title 47PF/8P4C CP4 47PF/8P4C CP3 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 1 2 1 2 USB1 2 4 6 8 HEADER_2 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number Sheet 19 Pin 1 near USB2 Pin 4 Pin 2 near USB2 Pin 6 Pin 1 near USB2 Pin 3 Pin 2 near USB2 Pin 5 ABIT Computer Corp. JP5 JP5 JP4 JP4 HEADER 4X2 1 3 5 7 USB2 USB_CON2 VCC0 DATA0DATA0+ GND0 VCC1 DATA1DATA1+ GND1 HEADER_2 USB 0-3 JP5 JP4 1 2 3 4 5 6 7 8 2 1 1 of 32 Rev A A B C D A B C 8 ABIT SL30 25 AC97SPKR 21 LNLVL_OUT_R 21 LNLVL_OUT_L 21 AUX_L 21 AUX_R 21 CD_R 21 CD_L 21 CD_REF 21 LINE_IN_R 21 LINE_IN_L 21 MIC_IN 7 7 R154 10K R155 1K 6 0.1UF BC141 6 MC58 MC56 X1UF 1UF 5 5 C94 MC53 PC_BEEP LINE_IN_R LINE_IN_L MIC1 MIC2 CD_R CD_L CD_REF VIDEO_R VIDEO_L AUX_L AUX_R PHONE MONO_OUT LINE_OUT_R LINE_OUT_L LNLVL_OUT_R LNLVL_OUT_L 2700PF 2700PF 1UF C95 12 24 23 21 22 20 18 19 17 16 14 15 13 37 36 35 41 39 0.1UF BC140 VCC3_3 1UF MC54 29 AFILT1 D 8 DVSS1 4 AFILT2 30 1 FILT_L 4 4 0.1UF MC52 32 DVDD1 0.1UF BC139 7 0.1UF MC55 0.1UF BC136 2.2UF MC48 3 22PF C98 24.576MHZ Y1 CS1 CS0 CHAIN_CLK EAPD RESET# SDATA_OUT SDATA_IN SYNC BIT_CLK 3 10PF C99 R253 22PF C97 X0 CS4299 46 45 48 47 11 5 8 10 6 U15 0.1UF BC129 "SINGLE POINT CONNECTION" 4.7UF MC46 0.1UF MC51 PFB6 BEAD VCC5 AC’97 CODEC DVSS2 RX3D 33 FILT_R 31 1 2 38 AVDD2 9 DVDD2 CX3D 34 AVSS2 26 AVSS1 42 VREF 27 VREFOUT 28 XTL_OUT 3 25 AVDD1 40 44 43 NC40 NC44 NC43 XTL_IN 2 Date: Size B Title 1K 21 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number Sheet ABIT Computer Corp. AUD_VREFOUT 21 EAPD PRI_DWN_RST# 29 AC_SDOUT 13,25,29 AC_SDIN0 13,25,30 AC_SYNC 13,25 AC_BITCLK 13,25 AC97 CODEC R254 1K R252 VCC5_AUDIO 2 20 1 1 of 32 Rev B A B C D A B C D LINE_IN_L 20 MIC_IN 8 ABIT SL30 20 20 AUD_VREFOUT LINE_IN_R 20 20 EAPD 20 LNLVL_OUT_R 20 LNLVL_OUT_L 8 1UF MC41 1UF 7 100PF 100PF C85 0.01UF 1K R120 2.2K R119 C86 C80 R121 1K 1 6 100PF C76 BEAD FB16 2 MC42 1 5 1 BEAD FB15 2 5 PHONEJACK JK3 Microphone Input PHONEJACK JK2 Line_In Analog Input FB17 2 BEAD R122 1K 6 1UF MC44 20K R127 MC45 1UF 20K R132 1UF MC47 7 1 2 3 4 1 2 3 4 CD_INR AUX_INR AUX_INL CD_ING CD_INL 4 "SINGLE POINT CONNECTION" 2.54_WAFER_4 AUX1 1 2 3 4 2mm_WAFER_4 CD1 2.54_WAFER_4 CD2 3 1 2 3 4 LM4880 OUTA INA BYPASS GND U11 100UF 1K R116 1K R117 1K R115 8 7 6 5 3 1UF MC36 R125 220K VDD OUTB INB SHUTDN 1UF Date: Size B Title 100PF C84 2 2 Wednesday, March 15, 2000 AB-SL30 0.12 1UF 1UF MC38 1UF MC39 MC43 C90 100PF Sheet ABIT Computer Corp. 100PF C82 R128 20K PHONEJACK JK1 Document Number AUDIO I/O 100PF C83 100PF C79 0.1UF BC123 R124 220K 100PF 100PF VCC5_AUDIO C74 C75 R118 220K MC37 100PF C81 BEAD FB14 2 C78 1 R105 20 BEAD 20 FB13 2 100UF 1 R104 C77 Stereo HP/Spkr out CD Analog Input 20K 100PF MC40 1UF R126 C87 4 + + 21 AUX_R AUX_L 1 CD_REF CD_L CD_R 1 of 32 20 20 20 20 20 Rev A A B C D A B C D 8 ABIT SL30 8 VCC5 VCCRTC THRMDN VCC5 -5VIN -12VIN +12VIN +3.3VIN VTT VCORE HM_VREF VTIN3 FANPWM2 FANPWM1 BEEP MIDI_IN MIDI_OUT J1BUTTON2 J2BUTTON2 JOY1Y JOY2Y JOY2X JOY1X J2BUTTON1 J1BUTTON1 26 26 25 24 24 24 24 24 24 24 24 24 24 13,18 13,18 13,18 13,18 13,18 LAD3 LAD2 LAD1 LAD0 LFRAME# 13 LDRQ#0 12,30 SERIRQ 6 SIO_CLK24 12,30 LPC_PME# 6 PCLK_7 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 3,27 3,27 3,27 3,27 26 26 26 4,26 VTIN2 26 VTIN1 13,30 OVT# 4,26 26 26 26 26 26 26 26 26 6,9,10,13,25,30 SMBCLK 6,9,10,13,25,30 SMBDATA 7 7 BC161 0.1UF BC154 0.1UF BEAD 1 BEAD FB20 2 FDC1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER_17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 HEAD# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# DS1# RWC# BC172 0.1UF R185 300 R193 300 6 VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 IOAVCC 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 FDD Signals Trace 8 or 10 mil 1 FB19 2 6 5 4 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 W83627HF VTIN3 VREF VCOREA VCOREB +3.3VIN AVCC +12VIN -12VIN -5VIN AGND SCL/GP21 SDA/GP22 PLED/GP23 WDTO/GP24 IRRX/GP25 IRTX/GP26 VSS RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# VCC CASEOPEN# SUSCLKIN VBAT SUSCIN/GP30 PWRCTL#/GP31 PWROK/GP32 RSMRST#/GP33 CIRRX/GP34 PSIN# PSOUT# MDAT MCLK DRVDEN0 DRVDEN1 INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 5 4 BC162 .1U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 BC155 .1U 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 U17 3 VCC3_3 VCC5 W83627HF SUSLED/GP35 KDAT KCLK VSB KBRST GA20M KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 R166 0 3 V3SB R167 10K Date: Size B Title VCC5SBY VCC5SBY R157 10K MDAT MCLK 7,17,18,30 PCIRST# ABIT Computer Corp. 23 23 23 23 23 23 23 23 23 23 23 23 PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 ACK# BUSY PE SLCT 23 23 23 23 23 23 23 23 23 23 23 TXD0 RXD0 DTR#0 RTS#0 DSR#0 CTS#0 STB# AFD# ERR# PAR_INIT# SLIN# 12,30 12,30 25 23 23 KBRST# A20GATE KEYLOCK# RI#0 DCD#0 25 24 24 24 24 PWRBTN# SUSLED KDAT KCLK 25 13 PANSWIN 13 13,26 RSMRST# PWROK 6,13,28 SLP_S3# 26 SUSCLK PS_ON 13,26 13 CASEOPEN# 24 24 23 23 23 23 23 23 23 23 IRRX IRTX RI#1 DCD#1 TXD1 RXD1 DTR#1 RTS#1 DSR#1 CTS#1 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number Sheet LPC I/O CONTROLLER & FDC BC151 0.1UF VCC5 2 22 1 1 of 32 Rev A A B C D 1 2 3 4 PAR_INIT# SLIN# STB# PDR0 PDR1 PDR2 PDR3 SLCT PDR4 PE PDR5 BUSY PDR6 PDR7 ACK# 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 A ERR# 22 ABIT SL30 AFD# ICH_RI# 22 13,30 11,12,14,15 PCI_PME# A RI1 RI0 100 R229 4.7K R230 10K R109 10K R107 R110 2.2K R108 2.2K 3 2 1 HEADER_3*1(2MM) WOL1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI9 SI8 P5 SI7 P4 SI6 P3 SI5 SI4 SI3 SI2 SI1 P2 P1 U5 B PAC-S1284 P6 SO9 SO8 SO7 SO6 VCC SO5 GND SO4 SO3 SO2 SO1 P7 P8 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Parallel Port Q15 2N3904 Q14 2N3904 WAKE ON MODEM 2N3904 Q21 VCC5SBY WAKE ON LAN B 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 DCD#1 DTR#1 CTS#1 TXD1 RTS#1 RXD1 DSR#1 RI#1 DCD#0 DTR#0 CTS#0 TXD0 RTS#0 RXD0 DSR#0 RI#0 VCC5 C 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 LPT LPT1 SS12/SMD BC49 .1U D2 VCC12- SS12/SMD D6 C 12 13 14 15 16 17 18 19 10 11 12 13 14 15 16 17 18 19 10 11 GD75232 RY5 DA3 RY4 DA2 DA1 RY3 RY2 RY1 -12V GND U10 GD75232 RY5 DA3 RY4 DA2 DA1 RY3 RY2 RY1 -12V GND U9 RA5 DY3 RA4 DY2 DY1 RA3 RA2 RA1 12V 5V RA5 DY3 RA4 DY2 DY1 RA3 RA2 RA1 12V 5V 9 8 7 6 5 4 3 2 1 20 9 8 7 6 5 4 3 2 1 20 VCC12 DCD1 DTR1 CTS1 TXDD1 RTS1 RXDD1 DSR1 RI1 DCD0 DTR0 CTS0 TXDD0 RTS0 RXDD0 DSR0 RI0 D7 D SS12/SMD VCC5 D CN11 Date: B Size Title Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number CONNECTOR_DB9 COM1 100PF/8P4C CN9 E Sheet 2 4 6 8 10 23 of HEADER_5X2 1 3 5 7 9 COM2 COM2 100PF/8P4C CN2 1 6 2 7 3 8 4 9 5 COM1 E ABIT Computer Corp. WOL, WOR & 2S1P 100PF/8P4C RTS1 RI1 CTS1 DSR1 DTR1 BC54 RXDD1 .1U DCD1 TXDD1 100PF/8P4C CN3 DCD0 DSR0 RXDD0 RTS0 TXDD0 BC99 CTS0 .1U DTR0 RI0 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 32 A Rev 1 2 3 4 1 2 3 4 JOY2Y JOY1Y J2BUTTON2 J1BUTTON2 MIDI_IN 22 22 22 22 22 IRRX 22 A MCLK 22 ABIT SL30 IRTX MDAT 22 22 KCLK KDAT 22 22 MIDI_OUT 22 VCC5DUAL J1BUTTON1 J2BUTTON1 JOY1X JOY2X 22 22 22 22 A C67 1000PF C71 1000PF C63 22PF C65 22PF IR1 RN4 8 6 4 2 F2 R18 F1 0 0 IR HEADER_1X5 1 2 3 4 5 C68 22PF R17 C66 22PF C64 1000PF R91 RN40 8 6 4 2 XFUSE_1.0A 4.7K/8P4R 7 5 3 1 8 6 4 2 B 2 2 BEAD FB4 2 BEAD FB6 2 1 1 7 5 3 1 7 5 3 1 BEAD 2 FB2 BEAD BEAD FB5 2 FB3 1 1 1 R93 4.7K VCC5 BEAD FB1 470PF8P4C 8 6 4 2 CN1 470PF 470PF/8P4C 470PF 1 C59 CN8 R94 4.7K C62 47 1K/8P4R 7 5 3 1 1K/8P4R 7 5 3 1 XFUSE_1.0A RN39 8 6 4 2 47 R98 4.7K R99 C60 1000PF VCC5 4.7K R92 VCC5 R102 4.7K VCC5 2.2UF C1 BEAD FB12 F6 2.2UF C2 470PF/8P4C CN10 R101 4.7K VCC5 2 1 VCC5 VCC5 B 8 6 4 2 8 6 4 2 7 5 3 1 7 5 3 1 8 6 4 2 7 5 3 1 8 6 4 2 7 5 3 1 0 VCC5 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 GAME_PORT J1 C Keyboard Mouse KB/MOUSE 7 8 9 10 11 12 16 17 13 14 15 1 2 3 4 5 6 U1 Game Port 470PF C73 JOY_2Y JOY_1Y J2BUT2 J1BUT2 MIDI_INPUT MIDI_OUTPUT J1BUT1 J2BUT1 JOY_1X JOY_2X 470PF C70 XFUSE_1.0A R103 C D D Date: B Size Title Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet KB, MS, GAME ,WOL & IR ABIT Computer Corp. E 24 of 32 A Rev 1 2 3 4 A B C D BEEP 22 AC97SPKR 8 ABIT SL30 20 13,29 ICH_SPKR SUSLED HWRST# 26 22 IDEACTS# 18 PANSWIN 22 IDEACTP# EXTSMI# 18 KEYLOCK# 22 12 8 2 4 R256 0 XHEADER 2X2 1 3 JP2 R255 10K VCC5 0.1UF BC185 R223 10K VCC5 R241 10K 7 R226 7 Q20 2N3904 R231 68 68 Q22 2N3904 R234 150 VCC5SBY 1N4148 1N4148 R232 D14 D15 R240 0 R242 R244 220 10K VCC5SBY 0 BC184 0.1UF 33 R236 VCC5 R238 220 VCC5 R237 R243 150 VCC5 6 JP2 TRADITIONAL PC SOUND 1-2 ON ON BOARD BUZZ OR DIRECT TO SPKR 3-4 ON MIXED IN ON_BOARD AC97 CODEC 2.2K Q19 2N3904 R235 10K 0.1UF C119 R233 10K V3SB 6 SMI_SW PWR_SW HDD LED KEYLOCK RESERVE 5 BUZZER SP1 13 13 19 12 12 EE_SHCLK EE_DOUT CNR_OC# LAN_RXD2 LAN_RXD0 12 LAN_TXD1 12 LAN_RSTSYNC VCC5SBY 13,15,30 SMLINK1 13,15,30 SMLINK0 13,20 AC_SYNC 13,20,29 AC_SDOUT 13,20 AC_BITCLK 6,9,10,13,22,30 SMBCLK 29 PRI_DWN GREEN LED SPEAKER RESET HEADER_14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PN2 HEADER_14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PN1 5 R246 2.2K 4 R239 330 VCC5 R247 20K 1 2 3 4 5 LED D16 SMBCON CNR RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD2 LAN_TXD0 GND LAN_CLK LAN_RXD1 RESERVED USB+ GND USB+12V GND +3.3VDUAL +5VD 3 1 2 3 4 5 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 SMBCON SMB1 GND EE_DIN EE_CS SMB_A1 SMB_A2 SMB_SDA AC97_RESET# RESERVED AC97_SD_IN1 AC97_SD_IN0 GND 3 VCC5 GND EE_DOUT EE_SHCLK GND SMB_A0 SMB_SCL PRIMARY_DN# GND AC97_SYNC AC97_SD_OUT AC97_BITCLK RESERVED RESERVED RESERVED GND RESERVED RESERVED GND LAN_TXD1 LAN_RSTSYNC GND LAN_RXD2 LAN_RXD0 GND RESERVED +5VDUAL USB_OC# GND -12V +3.3VD CNRSLOT1 SMB2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 VCC3_3 VCC12-VCC5SBY 4 Date: Size B Title 2 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 1 EE_DIN EE_CS Sheet 25 1 AC_SDIN1 AC_SDIN0 of 32 13,30 13,20,30 Rev A 6,9,10,13,22,30 13,29 13 13 19 19 CNRUSBP CNRUSBN 12 12 12 12 LAN_CLK LAN_RXD1 LAN_TXD2 LAN_TXD0 SMBDATA AC_RST# ABIT Computer Corp. R272 C125 R273 C126 15K 15K 47PF 47PF FRONT PANEL & CNR VCC12V3SB VCC5 2 A B C D 1 2 3 4 PS_ON VCCRTC FANPWM2 FANPWM1 R213 R16 R216 ABIT SL30 S1 10M 510 510 A HEADER_2PIN If case is opened, this switch should be closed. 13,22 CASEOPEN# 22 22 4 DBRESET# 25 HWRST# 22 A Q1 2N7002 R10 4.7K R11 Q17 2N7002 1K 1K 4.7K R218 R217 VCC5 VCC_5- + 22UF EC35 22UF EC3 HEADER_3 FAN3 3 2 1 + VCC12 + HEADER_3 FAN2 3 2 1 HEADER_3 FAN1 3 2 1 Q2 2N2907 +12CPUFAN VCC12 22UF EC38 1 2 3 4 5 6 7 8 9 10 B 1N4148 D5 PWR FAN 1K R100 1K 1N4148 VCC5 R19 D1 CPU FAN 1K 1N4148 VCC5 14 1 7 6 12 74LVC14A U20A 2 74LVC14A U20F 74LVC14A V3SB 13 5 U20C FANIO3 FANIO2 FANIO1 CHASSIS FAN BC165 .1U R212 V3SB 100 VCC5SBY VCC12 ATXPWROK D13 VCC5 R245 R323 1K V3SB 3.3V 3.3V GND +5V GND +5V GND PWROK AUX5V +12V ATX_PWCON 3.3V -12V GND PS_ON GND GND GND -5V +5V +5V ATXPR1 Q18 2N2907 +12CHFAN VCC12 11 12 13 14 15 16 17 18 19 20 22 22 22 3 13 1 BC164 .1U VCC5SBY C 2 12 4 C 74LVC06A U19B VCC5SBY 74LVC06A U19F VCC5SBY VCC5 D10 1N4148 74LVC06A U19A VCC5SBY 14 7 VCC12- B 4,22 4,22 22 VCC3_3 VTT1_5 VCCVID VCC12 THRMDN VTIN2 VTIN1 VTIN3 HM_VREF 22 R192 33K 22 2UF C115 R190 15K 74LVC14A 8 11 D 56K,1% PR33 56K,1% PR35 28K,1% PR37 3300PF C118 30K R210 PR38 Date: B Size Title 120K,1% PR32 232K,1% 10K PR34 10K R214 10K R208 R209 10K,1% PR36 10K,1% PR39 10K,1% 10 HEADER_2 JP3 4.7K R189 V3SB E PWROK Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet ATX POWER & H/W MONITOR ABIT Computer Corp. 26 VCC_5- -5VIN -12VIN VCC12- +3.3VIN VTT VCORE +12VIN Voltage Sensing "power use" 10K_1%-THRM/0603 RT1 "system use" X10K_1%-THRM/0603 RT2 74LVC06A U19E VCC5SBY Temperature Sensing 9 U20D D 1 2 VCC3_3 t t of 22 22 22 22 22 22 32 13,22 A Rev 1 2 3 4 1 2 3 ABIT SL30 A 11 EC32 + VCC1_8 VTT1_5 TYPEDET# 1500UF 1500UF EC34 + VDDQ 13 VRM_PWRGD 1500UF EC31 + L4 1500UF EC25 + R31 22 B R32 1K Q10 HUF75307D3S TO-252 7UH R191 R56 1500UF 33 100UF EC30 + 14 15 19 18 16 10 11 HIP6020 VSEN4 DRIVE4 VSEN3 DRIVE3 VAUX VSEN2 SELECT PHASE2 UGATE2 OCSET2 U4 10 R36 VCC12 VID0 VID1 VID2 VID3 VID4 SS COMP1 FB1 VSEN1 PGND LGATE1 PHASE1 UGATE1 OCSET1 1K R53 VCC3_3 "SINGLE POINT CONNECTION 1K 2 1 9 1UF R55 VCC3_3 10 4.7K R52 R54 VCC3_3 Q12 3055 TO-252 C13 33 C26 1000PF 1500UF C32 + D3 1N5820 EC29 + Q11 HUF76107D3S TO-252 B 28 VCC 4 A PGOOD 8 FAULT/RT 13 GND 17 7 6 5 4 3 12 20 21 22 24 25 26 27 23 C C C17 0.01UF 20K R43 10PF 55N03 Q9 TO-263 C16 C27 0.1UF R38 0 R37 0 3.9K R29 55N03 Q6 TO-263 1000PF C11 VCCPWM L3 1UH VCC5 EC24 + EC21 + 2.2K 270K R42 3UH R39 5.1K R40 1000PF C14 L1 EC1 + EC4 + EC8 + EC13 + EC12 + EC2 + EC7 + D ABIT Computer Corp. E Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet VOLTAGE REGULATORS PART 1 Date: B Size Title VID0 VID1 VID2 VID3 VCCVID 1500UF 1500UF 1500UF 1500UF 1500UF 1500UF 1500UF 1500UF EC9 + C15 0.22UF 1500UF 1500UF 1500UF EC23 + D 27 3,22 3,22 3,22 3,22 of 32 A Rev 1 2 3 4 1 2 3 4 ABIT SL30 A VCC5 VCC3_3 VCC5SBY 6,13,22 SLP_S3# 13 SLP_S5# V3SB A C18 1UF EC20 + 10UF NZT651/SOT223 Q4 EC15 + 100UF EC22 + 100UF 0.1UF C7 6 7 5 2 13 B 0.1UF C4 R20 10K 4 9 3 100UF EC17 + VCC5SBY B 1 1 2 3 4 D1 D1 D2 D2 DLA 5VDL FDS8936 / SI9936 S1 G1 S2 G2 Q8 HIP6501 S3 S5 EN5VDL EN3VDL SS VSEN2 DRV2 8 7 6 5 10 12 11 1UF C5 16 15 1500UF EC14 + 1UF C8 C EC10 + VCC3SBY C VCC5DUAL 100UF Q5 NDS356AP/SOT23 VCC5SBY HUF76121D3S/TO252 Q7 100UF 10UF U2 EC19 + VCC3_3 EC11 + VCC12 5VDLSB 3V3DL FAULT/MSET 3V3DLSB 5VSB 14 12V GND 8 10UF + EC40 V3SB 10UF + EC6 VCC5 3 3 VIN Q24 VIN Q3 ADJ 1 ADJ 1 2 2 D 60,1% PR41 120,1% PR40 LM1117ADJ VOUT 100,1% PR2 100,1% PR3 LM1117ADJ VOUT D Date: B Size Title 10UF + EC41 V1_8SB 100UF + EC5 VCC2_5 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet VOLTAGE REGULATORS PART 2 ABIT Computer Corp. E 28 of 32 A Rev 1 2 3 4 C R153 1.8K R260 8.2K R261 8.2K R262 8.2K R263 8.2K D SW2:7-8 ON BOARD AC97 CODEC ON 7 PRIMARY CODEC DISABLE ON 8 PRI_DWN_RST# 20 6 6 13,20,25 13,25 7 R_REFCLK FMOD0 FMOD1 AC_SDOUT ICH_SPKR 7 R_BSEL#0 E Rev 4 1 Date: B Size Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet SYSTEM CONFIGURATION ABIT Computer Corp. 29 of 32 STRAP(SPKR) NO REBOOT ON 2ND WATCHDOG TIMEOUT REBOOT ON 2ND WATCHDOG TIMEOUT SW2:6 ON OFF Title AC_SDOUT USE CPU FREQ STRAP IN ICH REGISTER FORCE CPU FREQ STRAP TO SAFE MODE(1111) SW2:5 ON OFF SW2:3-4FSB / SYSTEM MEMORY ON ON 66M/PC100 OFF ON 100M/PC100 OFF OFF 133M/PC100 OR PC133 SW2:1-2 FSB / SYSTEM MEMORY ON1-2 CPU DEFAULT OFF 1-2BY SW2:3-4 A 1 2 B RN59 1.8K/8P4R D 2 A DIPSW-8 16 15 14 13 12 11 10 9 1N4148 D17 SW1 1 2 3 4 5 6 7 8 V3SB C 3 ABIT SL30 PRI_DWN 25 13,25 AC_RST# BSEL#0 BSEL#1 4 4 B 3 4 A 2 4 6 8 1 3 5 7 1 2 3 4 PERR# SERR# PLOCK# STOP# DEVSEL# TRDY# IRDY# FRAME# A ICH_IRQ#E ICH_IRQ#F ICH_IRQ#G ICH_IRQ#H 12 12 12 12 ABIT SL30 ICH_IRQ#A ICH_IRQ#B ICH_IRQ#C ICH_IRQ#D 12 12 12 12 PIRQ#A PIRQ#B PIRQ#C PIRQ#D ACK64# REQ64#1 REQ64#2 REQ64#3 14,15 14 14 15 11,14,15 11,14,15 14,15 14,15 PREQ#3 PREQ#5 PREQ#4 12 12 12 12,15 PREQ#2 12,14 PREQ#1 12,14 PREQ#0 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 12,14,15 SMBALERT# ICH_RI# SMBCLK SMBDATA PCI_REQ#A OVT# KBRST# A20GATE GPI8 GPIO25 GPIO27 GPIO28 X0/8P4R 1 3 5 7 0/8P4R RN76 2 4 6 8 R152 R147 2.7K/8P4R 2.7K/8P4R RN77 2 4 6 8 RN75 2 4 6 8 10K 10K 8.2K 8.2K/8P4R 8.2K/8P4R RN51 2 4 6 8 4.7K/8P4R RN54 2 4 6 8 4.7K/8P4R RN60 2 4 6 8 RN55 2 4 6 8 ICH R276 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 13,25 AC_SDIN1 13,20,25 AC_SDIN0 12,22 SERIRQ 12 13,22 12,22 12,22 12 13 12 12 13,15,25 SMLINK0 13,15,25 SMLINK1 12,22 LPC_PME# 13 13,23 6,9,10,13,22,25 6,9,10,13,22,25 1 3 5 7 B B RN74 2 4 6 8 2.7K/8P4R 10 5 VCC5 1 3 5 7 1 3 5 7 2.7K/8P4R RN66 2 4 6 8 2.7K/8P4R RN64 2 4 6 8 1 3 5 7 C C 1 3 5 7 R1 R2 R3 R4 R5 R6 R7 R8 RP2 2.7K/10P8R RN58 2 4 6 8 1 2 3 4 6 7 8 9 PCI C C VCC3_3 VCC3_3 VCC3_3 V3SB V3SB V3SB 9 5 12 6 8 74LVC06A U19D VCC5SBY 74LVC06A U19C VCC5SBY ICHRST# 9 D 13 11 D 74LVC07A U18D 8 VCC3_3 14 7 A Title Date: Size B 10 4 PCIRST# PCI_RST# IDERST# Wednesday, March 08, 2000 AB-SL30 V0.12 E Sheet PU/PDR & UNUSED GATES Document Number E ABIT Computer Corp. 74LVC14A 74LVC07A 74LVC14A U20B 3 R198 1K VCC3_3 74LVC07A U18C 6 VCC3_3 R197 1K VCC3_3 74LVC07A U18B 4 VCC3_3 74LVC07A U18A 2 R196 1K VCC5 U20E 11 5 3 1 VCC3_3 U18F 12 VCC3_3 74LVC07A U18E 10 VCC3_3 R188 1K BC163 .1U VCC3_3 VCC3_3 14 7 14 7 14 7 14 7 14 7 30 of 32 7,17,18,22 11,14,15 18 Rev A 1 2 3 4 1 2 3 4 MC5 4.7UF MC31 MC30 MC11 4.7UF MC16 4.7UF BC66 0.1UF 0.1UF MC24 4.7UF BC71 0.1UF BC78 0.1UF 0.01UF 0.01UF 0.1UF 0.1UF 8 7 6 5 ABIT SL30 HOLE A 0.1UF 0.1UF H1 1 2 3 4 BC107 BC100 " misc. " BC132 BC131 VCC3_3 0.01UF BC80 0.01UF BC74 0.1UF A BC106 0.1UF BC138 0.1UF BC109 0.1UF BC121 " ICH : 0.1U//0.01U at each conner " BC82 BC87 VCC3_3 0.1UF BC39 4.7UF MC14 0.1UF BC53 0.1UF H3 1 2 3 4 BC122 0.01UF BC150 0.01UF BC88 0.1UF BC50 HOLE A 0.1UF BC128 0.01UF BC149 0.01UF BC65 0.1UF BC42 0.1UF BC145 0.01UF BC147 0.01UF BC48 0.1UF B 4.7UF MC2 0.1UF 8 7 6 5 B 0.01UF BC144 2.2UF MC57 4.7UF MC1 0.1UF BC180 MC12 MC17 0.01UF BC199 0.01UF 0.01UF BC200 0.01UF H5 1 2 3 4 0.01UF 8 7 6 5 0.01UF BC159 0.1UF BC204 HOLE A BC158 2.2UF MC59 H6 1 2 3 4 0.01UF BC160 0.1UF BC205 MC35 HOLE A 0.01UF 22UF EC36 0.1UF BC142 MC34 0.01UF BC95 0.1UF BC20 4.7UF MC33 0.01UF BC96 0.1UF BC40 4.7UF 0.1UF 0.1UF 0.01UF BC79 BC67 BC77 MC32 4.7UF 0.01UF BC46 0.1UF BC97 0.1UF BC92 0.1UF BC93 C HOLE A 0.01UF BC171 0.1UF BC115 8 7 6 5 0.01UF BC183 0.1UF BC113 0.01UF BC182 0.1UF BC116 VCC1_8 " ICH : Near Power Pins " H7 1 2 3 4 0.01UF BC170 0.1UF BC207 0.1UF BC91 0.1UF 0.01UF BC181 0.1UF BC208 0.1UF BC98 0.01UF BC47 0.1UF BC84 BC102 0.1UF 0.1UF BC167 BC101 0.1UF BC156 " GMCH : Near Display Cache Quadrant " " Within 70 mils of GMCH " 8 7 6 5 BC169 0.1UF BC206 0.1UF BC94 VDDQ 0.01UF BC105 0.1UF 0.1UF BC157 VCC12- " ATX POWER " C " Display Cache : Near the Power Pins " BC11 4.7UF MC25 4.7UF BC114 MC27 4.7UF BC75 4.7UF Backside : not po[ulated. 0.01UF BC198 0.1UF BC81 4.7UF 0.1UF BC143 VDDQ VCC3SBY " DIMM1 : Near Power Pins " 4.7UF MC4 22UF BC168 " ATX POWER " EC26 VCC12 V3SB " ICH : Near Power Pins " 0.01UF BC52 0.1UF BC45 4.7UF MC3 0.1UF BC70 HOLE A 0.1UF BC146 0.01UF BC124 0.01UF BC51 0.1UF BC44 0.1UF BC10 4.7UF MC9 0.1UF BC69 H4 1 2 3 4 0.1UF BC8 BC43 8 7 6 5 0.1UF BC19 4.7UF MC15 22UF EC28 VCC_5- " ATX POWER " " GMCH : 0.1U//0.01U at each conner and each side-center " 4.7UF VCC3SBY " GMCH : Near System Mem Quadrant " 4.7UF MC26 VCC1_8 4.7UF 4.7UF MC13 0.1UF BC76 4.7UF MC10 22UF BC41 " ATX POWER " EC27 VCC5 VCC3SBY " DIMM0 : Near Power Pins " MC8 4.7UF 0.1UF 0.1UF MC6 BC83 BC85 4.7UF VCCVID 22UF EC33 VCC3_3 " ATX POWER " A 0.1UF BC104 0.1UF BC112 MC61 0.1UF 0.01UF BC187 0.1UF BC209 V1_8SB MC63 4.7UF 0.1UF BC203 MC62 4.7UF BC202 4.7UF 0.01UF BC186 0.1UF BC210 0.1UF D BC211 " ICH : Near Power Pins " Backside : not po[ulated. 0.1UF BC201 4.7UF MC60 VCC3SBY " DIMM2 : Near Power Pins " 0.1UF BC103 0.1UF BC179 D 0.1UF BC212 0.1UF BC213 0.1UF BC111 Date: Size B Title 0.1UF BC214 0.1UF BC110 0.1UF BC216 0.1UF 0.1UF BC218 ABIT Computer Corp. BC217 Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number E Sheet DECOUPLING CAPACITORS 0.1UF BC215 0.1UF BC108 E 31 of 32 Rev A 1 2 3 4 A B C D HISTORY ABIT Computer Corp. Date: Size B Wednesday, March 08, 2000 AB-SL30 V0.12 Document Number 32 of 32 Rev A E Sheet 1 1 ABIT SL30 Title 2 2 This Page Is Left Blank. E 3 D 3 C 4 B 4 A Index #, defined 7 A I I/O Controller Hub (ICH2) 24 Instructions, notational conventions 7 Accelerated Graphics Port (AGP) Support 12 M B Baseboard Features 11 Beep codes 49, 64 BIOS Basic Setup Screen 52 Configuring floppy drives 53 Configuring IDE drives 54 Console redirection 58 Custom Setup Screen 55 Drive assignments 53 Integrated BIOS debugger 59 Setup Screen System 51 Shadow Configuration Setup Screen 56 Standard Diagnostics Routines Setup Screen 57 BlueCat™ Linux 14 C Chipset 11 clock generation 28 CMOS memory 46 Console Redirection 58 CPU 11 D Manufacturing Mode 58 Measurements, defined 8 Memory Support 11 N Notational conventions 7 O Online help 9 P Peripheral Connectors 12 POST beep codes 64 post code debugging 31 POST codes 49, 61 Power Supply/Management 12 Power-on Self Test (POST) 49 pre-boot environment 49 Product literature, ordering 9 S Documents online 9 Drive assignments 53 Setup Screen System 52 Signals, notational conventions 8 System I/O 12 E T Embedded BIOS 49 Integrated Debugger 57 Manufacturing Mode 58 Technical support 9 thermal management 22 thermal solution 31 F U Firmware Hub (FWH) 24 Units of measure, defined 8 URL 9 G Graphics and Memory Controller Hub (GMCH) 23 W Windows CE 59 World Wide Web 9 www.intel.com 9 Intel® 815E Scalable Performance Board Development Kit Manual Index-111