Download MSI MS-9105 Instruction manual

Chapter 3
AGP Master 1 WS Write
When Enabled, writes to the AGP bus are executed with one wait state
inserted.
AGP Master 1 WS Read
When Enabled, one wait state is inserted in the AGP read cycle.
CPU & PCI Bus Control
Press <Enter> and the following sub-menu screen will appear:
CPU & PCI Bus Control
CPU to PCI Write Buffer
PCI Master 0 WS Write
PCI Delay Transaction
Enabled
Enabled
Disabled
Item Help
Menu Level 88
CPU to PCI Write Buffer
When Enabled, CPU can write up to four words of data to the PCI write
buffer before CPU must wait for PCI bus cycle to finish. If Disabled,
CPU must wait after each write cycle until PCI bus signals that it is
ready to receive more data.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transaction cycles. Select Enabled to support compliance with
PCI specification version 2.1.
Memory Hole
In order to improve performance, certain space in memory can be reserved
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