Download VR Series 64-/32-Bit Microprocessor Programming Guide AN

VOLUME 2 VR SERIES ARCHITECTURE
The following describes the Config register and Status register, which are important in initialization, etc., among
these CP0 registers.
(1) Config register
The Config register can be read/written and displays/sets various states of the processor.
The Config register of each CPU appears as shown below.
Figure 1-7. Config Register (1/2)
(a) VR4121, VR4181
31 30
28 27
24
23
22
21 20 19
16 15 14
13 12 11
9 8
6 5
3 2
0
0
EC
EP
AD
00
M16
0010
BE
10
CS
IC
DC
000
K0
1
3
4
1
2
1
4
1
2
1
3
3
3
3
(b) VR4122
31 30
28 27
24 23 22 21 20 19
17 16
IS
EC
EP
AD
00
M16
001
1
3
4
1
2
1
3
15 14 13 12 11
BP BE
1
9 8
6
5
3 2
4
0
10
CS
IC
DC
IB
00
K0
2
1
3
3
1
2
3
1
(c) VR4300 Series
31 30
28 27
24 23
16
15 14
4
3
2
0
0
EC
EP
0000010
BE
11001000110
CU
K0
1
3
4
7
1
11
1
3
(d) VR5000 Series
31 30
16
15
0
EC
28 27
EP
24 23 22 21 20 19
SB
SS
EW
SC
1
BE EM EB SE
1
3
4
2
2
2
1
1
18 17
1
14
1
13
1
12 11
1
4
3
IC
9 8
DC
6 5
IB
DB
0
2
K0
0
3
3
1
1
1
3
(e) VR5432
31 30
28 27
24 23 22 21
16 15 14
3
2
0
0
EC
EP
EM
110110
BE
110011011110
K0
1
3
4
2
6
1
12
3
(f) VR5500
31 30
26
28 27
24 23 22 21 20 19 18 17 16 15 14
3
2
0
0
EC
EP
EM
11
EW
10
BE
110011011110
K0
1
3
4
2
2
2
2
1
12
3
Application Note U10710EJ5V0AN