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Transcript

SERVICE MANUAL
Model:
PDP4210EA
Safety Precaution
Technical Specifications
Block Diagram
Circuit Diagram
Basic Operations & Circuit Description
Main IC Specifications
Product Specification of PDP Module
Trouble Shooting Manual of PDP Module
Spare Part List
Exploded View
If you forget your V-Chip Password
Software Upgrade
This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.
Safety Precaution
RISK OF ELECTRIC SHOCK
DO NOT OPEN
The lightning flash with arrowhead symbol,
within an equilateral triangle, is intended to
alert the user to the presence of uninsulated
“dangerous voltage” within the product’s enclo
sure that may be of sufficient magnitude to
constitute a risk of electric shock to persons.
CAUTION: TO REDUCE THE RISK OF
ELECTRIC SHOCK, DO NOT REMOVE COVER
(OR BACK). NO USER-SERVICEABLE PARTS
INSIDE. REFER SERVICING TO QUALIFIED
SERVICE PERSONNEL ONLY.
The exclamation point within an equilateral
triangle is intended to alert the user to the
presence of important operating and
maintenance (servicing) instructions in the
literature accompanying the appliance.
CAUTION
PRECAUTIONS DURING
SERVICING
1. In addition to safety, other parts and
assemblies are specified for conformance with
such regulations as those applying to spurious
radiation. These must also be replaced only
with specified replacements.
Examples: RF converters, tuner units, antenna
selection switches, RF cables, noise-blocking
capacitors, noise-blocking filters, etc.
2. Use specified internal Wiring. Note especially:
1) Wires covered with PVC tubing
2) Double insulated wires
3) High voltage leads
3. Use specified insulating materials for hazardous
live parts. Note especially:
1) Insulating Tape
2) PVC tubing
3) Spacers (insulating barriers)
4) Insulating sheets for transistors
5) Plastic screws for fixing micro switches
4. When replacing AC primary side components
(transformers, power cords, noise blocking
capacitors, etc.), wrap ends of wires securely
about the terminals before soldering.
MAKE YOUR CONTRIBUTION
TO PROTECT THE
ENVIRONMENT
Used batteries with the ISO symbol
for recycling as well as small accumulators
(rechargeable batteries), mini-batteries (cells) and
starter batteries should not be thrown into the
garbage can.
Please leave them at an appropriate depot.
WARNING:
Before servicing this TV receiver, read the
SAFETY INSTRUCTION and PRODUCT
SAFETY NOTICE.
SAFETY INSTRUCTION
The service should not be attempted by anyone
unfamiliar with the necessary instructions on this
apparatus. The following are the necessary
instructions to be observed before servicing.
1. An isolation transformer should be connected in
the power line between the receiver and the
AC line when a service is performed on the
primary of the converter transformer of the set.
2. Comply with all caution and safety related
provided on the back of the cabinet, inside the
cabinet, on the chassis or picture tube.
5. Make sure that wires do not contact heat
generating parts (heat sinks, oxide metal film
resistors, fusible resistors, etc.)
6. Check if replaced wires do not contact sharply
edged or pointed parts.
7. Make sure that foreign objects (screws, solder
droplets, etc.) do not remain inside the set.
3. To avoid a shock hazard, always discharge the
picture tube's anode to the chassis ground
before removing the anode cap.
4. Completely discharge the high potential voltage
of the picture tube before handling. The picture
tube is a vacuum and if broken, the glass will
explode.
5. When replacing a MAIN PCB in the cabinet,
always be certain that all protective are
installed properly such as control knobs,
adjustment covers or shields, barriers, isolation
resistor networks etc.
6. When servicing is required, observe the original
lead dressing. Extra precaution should be given
to assure correct lead dressing in the high
voltage area.
PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in this
apparatus have special safety-related
characteristics.
These characteristics are offer passed
unnoticed by visual spection and the protection
afforded by them cannot necessarily be obtained
by using replacement components rates for a
7. Keep wires away from high voltage or high
tempera ture components.
higher voltage, wattage, etc.
The replacement parts which have these
8. Before returning the set to the customer,
always perform an AC leakage current check
special safety characteristics are identified by
marks on the schematic diagram and on the parts
on the exposed metallic parts of the cabinet,
such as antennas, terminals, screwheads,metal
list.
overlay, control shafts, etc., to be sure the set
is safe to operate without danger of electrical
read the parts list in this manual carefully. The
use of substitute replacement parts which do not
shock. Plug the AC line cord directly to the
AC outlet (do not use a line isolation
have the same safety characteristics as specified
in the parts list may create shock, fire, or other
transformer during this check). Use an AC
voltmeter having 5K ohms volt sensitivity or
hazards.
9. Must be sure that the ground wire of the AC
more in the following manner.
Connect a 1.5K ohm 10 watt resistor paralleled
inlet is connected with the ground of the
apparatus properly.
by a 0.15µF AC type capacitor, between a
good earth ground (water pipe, conductor etc.,)
and the exposed metallic parts, one at a time.
Measure the AC voltage across the combination
of the 1.5K ohm resistor and 0.15 uF
capacitor. Reverse the AC plug at the AC
outlet and repeat the AC voltage measurements
for each exposed metallic part.
The measured voltage must not exceed 0.3V
RMS.
This corresponds to 0.5mA AC. Any value
exceeding this limit constitutes a potential
shock hazard and must be corrected
immediately.
The resistance measurement should be done
between accessible exposed metal parts and
power cord plug prongs with the power switch
"ON". The resistance should be more than
6M ohms.
AC VOLTMETER
Good earth ground
such as the water
pipe, conductor,
etc.
Place this probe
on each exposed
metallic part
AC Leakage Current Check
Before replacing any of these components,
Technical
Specifications
DATE FIRST ISSUED
REVISIONS
ISSUED
ISSUE
1
DATE
MODEL :
PDP4210EA
42” Plasma Display
RAISED BY
CHECKED BY
NUMBER OF PAGES
10
DESCRIPTION
SPECIFICATION AGREED :
RAISED BY :
SIGNATURE
DATE
......................................................................................
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...
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...........................
...
Q/A DEPARTMENT
......................................................................................
.......
...........................
...
CUSTOMER
......................................................................................
.......
...........................
...
......................................................................................
.......
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...
R & D DEPARTMENT
COMMERCIAL DEPARTMENT
PRODUCTION DEPARTMENT
SPECIFICATION APPROVED :
SIGNATURE :
.
NOTE :
Only documents stamped “Controlled Document” to be used for manufacture of production parts.
DATE :
Technical
1.
CONTINUATION PAGE
Specifications
PDP4210EA
NUMBER
2
OF
10
PAGES
Standard Test Conditions
All tests shall be performed under the following conditions, unless otherwise specified.
1.1
Ambient light
:
150ux (When measuring IB, the ambient luminance
≦0.1Cd/m2)
1.2
Viewing distance
:
50cm in front of PDP
1.3
Warm up time
:
30 minutes
1.4
PDP Panel facing
:
no restricted
1.5
Measuring Equipment :
PC, Chroma 2225 signal generator (with Chroma digital
additional card) or equivalent, Minolta CA100 photometer
1.6
Magnetic field
:
no restricted
1.7
Control settings
:
Brightness, Contrast, Tint, Color set at Center(50)
1.8
Power input
:
110~120Vac,60Hz
1.9
Ambient temperature :
1.10 Display mode
:
1.11 Other conditions
:
20°C ± 5°C (68°F ± 9°F)
31.5KHz/60Hz (Resolution 852 x 480)
1.11.1
With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When
measuring the color tracking and luminance of a same still screen, be sure
to accomplish the measurement in one minute to ensure its accuracy.
1.11.2
Due to the structure of PDP, the extra-high-bright same screen should not
hold over 5 minutes for fear of branding on the panel.
Technical
CONTINUATION PAGE
Specifications
PDP4210EA
NUMBER
3
OF
10
PAGES
ELECTRICAL CHARACTERISTICS
2.
3.
Power Input
2.1
Voltage
:
110 ~120VAC
2.2
Input Current
:
3.5A
2.3
Maximum Inrush Current
Test condition
:
:
<30 A (FOR AC110V ONLY)
Measured when switched off for at least 20 mins
2.4
Frequency
:
2.5
Power Consumption
Test condition
:
:
≤ 330W
full white display with maximum brightness and
contrast
2.6
Power Factor
:
Meets IEC1000-3-2
2.7
Withstanding voltage
:
1.5kVac or 2.2kVdc for 1 sec
:
:
:
:
:
:
:
42” Plasma display
16:9
852x480
1000 cd/m² (Panel module without filter)
3000:1 (Panel module without filter)
Over 160°
English,Spaish,French
4.1.1 TV standard
4.1.2 TV Tuning system
4.1.3 CATV
4.1.4 Composite signal
4.1.5 Y,C Signal
4.1.6 Component signal
4.1.7 Graphic I/P
:
:
:
:
:
:
:
4.1.8 PnP compatibility
4.1.9 I/P frequency
:
:
NTSC/ATSC
181CH (for NTSC), 2~69CH (for ATSC)
125CH (for NTSC)
AV
S-Video
Y, Pb/Cb, Pr/Cr, HDTV compatible
Analog: D-sub 15pin detachable cable
Digital: DVI
DDC 1.0
fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz (640x480
recommended)
Display
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.
60Hz(±3Hz)
Screen Size
Aspect Ratio
Pixel Resolution
Peak Brightness
Contrast Ratio (Dark room)
Viewing Angle
OSD language
Signal
4.1
AV & Graphic input
Technical
4.2
4.3
5.
PDP4210EA
Audio input
Audio I/P(L/Rx5)
:
1 for DVI
1 for D-Sub
2 for YPbPr
1 for S-Video /AV
Audio output
Audio O/P(L/Rx1)
:
Monitor out(L/R)
SPDIF
:
Optical x 1
Environment
5.1 Operating environment
5.1.1 Temperature
:
5.1.2 Relative humidity:
5.2
6.
CONTINUATION PAGE
Specifications
Storage and Transport
5.2.1 Temperature
:
5.2.2 Relative humidity:
NUMBER
4
OF
10
PAGES
5º to 33°C
20% to 85%(non-condensing)
-20°C to 60°C(-4º to 140°F)
5% to 95%
Panel Characteristics
6.1
6.2
Type
Size
:
:
6.3
6.4
6.5
6.6
6.7
6.8
Aspect ratio
:
Viewing angle :
Resolution
:
Weight
:
Color
:
Contrast
:
6.9
Peak brightness :
LG V6
42”, 1005mm(width)x597mm(height)x61mm(depth)±1
mm)
16:9
Over 160°
852x480
14.8kg ±0.5 kg (Net)
16.77 million colors by combination of 8 bits R,G,B digital
Average 60:1 (In a bright room with 150Lux at center)
Typical 3000:1 (In a dark room 1/25 White Window
pattern at center).
Typical 1000cd/㎡ (1/25 White Window)
6.10 Color Coordinate Uniformity :
Test Pattern
:
Contrast; Brightness and Color control
at normal setting
Full white pattern
Average of point A,B,C,D and E +/- 0.01
Technical
CONTINUATION PAGE
Specifications
6.11 Color temperature
:
PDP4210EA
NUMBER
5
OF
10
PAGES
Contrast at center (50); Brightness center (50);
Color temperature set at Natural
x=0.285±0.02
y=0.293±0.02
6.12 Cell Defect Specifications
Subject to Panel supplier specification as appends.
7.
Front Panel Control Button
7.1
8.
CH Up / Down Button
:
Volume Up/ Down Button
:
Menu Button
:
Push the key to changing the channel up or down.
When selecting the item on OSD menu.
Push the key to increase the volume up or down.
When selecting the adjusting item on OSD menu
increase or decrease the data-bar.
Enter to the OSD menu.
Input Select Button
:
Push the key to select the input signals source.
7.2
Stand by Button
:
Switch on main power, or switch off to enter power
Saving modes.
7.3
Main Power Switch
:
Turn on or off the unit.
OSD Function
Full on screen display
Technical
9.
Specifications
CONTINUATION PAGE
PDP4210EA
NUMBER
6
OF
10
PAGES
Agency Approvals
Safety
UL60950
Emissions
FCC class B
10. Reliability
11.1 MTBF
11. Accessories
:
20,000 hours(Use moving picture signal at 25°C ambient)
:
User manual x1, Remote control x1, Stand x1, Power cord x1,
Battery x 2.
Technical
CONTINUATION PAGE
Specifications
PDP4210EA
NUMBER
7
OF
10
13. Support the Signal Mode
A. VGA and DVI mode
NO.
Resolution
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
640 x 400
640 x 480
640 x 480
640 x 480
720 x 400
800 x 600
800 x 600
800 x 600
800 x 600
832 x 624
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1280 x 720
1280 x 960
1280 x 1024
Horizontal
Frequency
(KHz)
31.47
31.50
37.50
37.86
31.47
35.16
37.90
46.90
48.08
49.00
48.40
56.50
60.00
63.86
67.52
45.00
60.02
64.00
Vertical
Frequency
(Hz)
70.08
60.00
75.00
72.81
70.08
56.25
60.32
75.00
72.19
75.00
60.00
70.00
75.00
70.02
75.02
60.00
60.02
60.01
Dot Clock
Frequency
(MHz)
25.17
25.18
31.50
31.50
28.32
36.00
40.00
49.50
50.00
57.27
65.00
75.00
78.75
94.51
108.03
74.25
108.04
108.00
Horizontal
Frequency
(KHz)
15.734
31.468
31.25
37.50
45.00
33.75
Vertical
Frequency
(Hz)
59.94
59.94
50.00
50.00
60.00
60.00
Dot Clock
Frequency
(MHz)
13.50
27.00
27.00
74.25
74.25
74.25
B. HDTV Mode (YPbPr)
NO.
Resolution
1
2
3
4
5
6
480i
480p(720x480)
576p(720x576)
720p(1280x720)
720p(1280x720)
1080i(1920x1080)
- When the signal received by the Display exceeds the allowed range, a warning message
“Main Not Support!” shall appear on the screen.
- You can conﬁrm the input signal format from the on-screen.
- DVI could not support some PC Graphic cards.
PAGES
Technical
Specifications
CONTINUATION PAGE
PDP4210EA
NUMBER
8
OF
10
Remote Control
Standby ( ): Press to turn on and off.
Mute (
): Press to mute the sound.
Press again to restore the sound.
0~9 Number Buttons: Press 0~9 to
select a channel, and used to input the
password; the channel changes after
2 seconds.
EPG: Press to display EPG mode.
Press it again to exit EPG mode.
Input: Press to select the signal
source, such as TV, AV, S-Video,
Component 1, Component 2, VGA,
DVI or DTV.
DTV: Press to choose DTV directly.
Dot: Press number buttons with it to
select the channels directly in DTV.
VOL +/-: Press to adjust the volume.
CH +/- : Press to select the channel
forward or backward.
MTS: Press repeatedly to cycle through
the Multi-channel TV sound (MTS)
options: Mono, Stereo and SAP
(Second Audio Program).
◄,►,▲,▼, Enter: Press ◄,►,▲,
▼ to move the on-screen cursor. To
select an item, press Enter to conﬁrm.
And it can also press ▲ or ▼ to
select channels, press ◄ or ► to
adjust the volume.
Exit: Press this button to exit.
Menu: Press to enter into the on-screen
setup menu, press again to exit.
V-Chip: Press to select the child
protect mode.
CCD: Press to select the Closed Caption mode.
Freeze: Press to freeze the picture, press again to restore the picture.
Display: Press to display the channel information and it disappear after 3 seconds.
Favorite: Press repeatedly to cycle through the favorite channel list.
Add/Erase: Press to add or delete favorite or dislike channels.
S.Mode: Press repeatedly to cycle through the sound mode: Normal, News, Cinema,
Flat and User.
PIC Size: Press repeatedly to cycle through the picture size that best corresponds your
viewing requirements: Normal, Full, Wide1, Wide2, Wide3, 4:3, No Scale and Panoramic.
(Continued on next page)
PAGES
Technical
Specifications
CONTINUATION PAGE
PDP4210EA
NUMBER
9
OF
10
P.Mode: Press repeatedly to cycle
through the picture mode: Normal,
Vivid, Hi-Bright, User and Dark.
System: Press repeatedly to cycle
through the system options: AUTO,
and NTSC3.58.
Recall: Press to return to previous
channel.
Sleep: Press repeatedly until it
displays the time in minutes (5 Min,
10 Min, 15 Min, 30 Min, 60 Min, 90
Min, 120 Min and, OFF) that you
want the TV to remain on before
shutting off. To cancel sleep time,
press SLEEP repeatedly until sleep
OFF appears.
Red: Press this button to access the
red item or page.
Blue: Press this button to access the
blue item or page.
Green: Press this button to access
the green item or page.
Yellow: Press this button to access
the yellow item or page.
Note: Press CH +/- on the remote control can turn on TV set from standby mode.
Insertion of Batteries:
- Turn the remote control upside down, press and slide off the battery cover.
- Insert two 1.5V (AAA) batteries into the compartment, take care to observe the  and 
markings indicated inside.
- Replace the cover and slide in reverse until the lock snaps.
PAGES
Technical
Specifications
CONTINUATION PAGE
PDP4210EA
NUMBER
10
OF
10
PHYSICAL CHARACTERISTICS
14. Power Cord
Length
:
1.8m nominal
Type
:
optional
:
“Black” colour as defined by colour plaque reference number
15. Cabinet
15.1 Color
15.2 Weight
Net weight
Gross weight
:
:
36.2 kg(with stand) /34.0kg(without stand)
41.0 kg
15.3 Dimensions(with stand)
Width
Height
Depth
:
:
:
1040 mm
690 mm
290 mm
PAGES
Block Diagram
Product Specification of PDP Module
LVDS Input
Control Signal
(Serial Interface)
Input
Interface
Controller
Vs(180V~190V)
Memory
Controller
Va(55V~65V)
Vcc(+5V)
Driver
Timing
Controller
APL Data
Color Plasma Display Panel
852 X 480 pixels
Common sustain driver
Scan Driver
Display data, Driver timing
Address Driver
☞ Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.
Block Diagram
X6965D
SAW Filter
(U9)
TD1336
Tuner(U8)
UPC3218
AGC Amplifier
(U10)
2nd_IF+ & 2nd_IFDifferential Data Stream
MT5111
DTV Front-end
(U11)
TS[0...7]
(U15)
74HC74
(U12)
I2C
EEPROM
24C16(U13)
I2C
256Mb DDR
MT5351
DTV Back-end
(U14)
(U18)
SPD
Video Data[0...23]
Audio Data
256Mb DDR
Control
Signals
Coaxial
Connect with
MT8205
32Mb
Flash(U17)
Block Diagram
Power Connector
To PDP
From MT 5351
LVDS Data
Control Signals
Audio
U30-U33
3.3V
74LVC244A
Vedio[0...23]
SiI161B
(SiI169) Video[0...23]
DVI
DVI Reciver
(U18)
Flash
I2C (MT8205 I2C)
5V
DVII2C
16M-BIT(U9)
EEPROM
24C02(U19)
(U23)
BA7612F
TV
128Mb(U10)
(U7)
AV
(U16)
IDTQS3
VH257
YpbPr×2
DDR
MT8205
CVBS×2 (CVBS0 is from tuner.)
V_BYPASS
3.3V
2.5V
1.8V
PDP Connector
RGB Output
PDP Control Signals
To PDP
1.8V
2.5V
1.25V
5V
3.3V
(Supplied by PDP)
Data[0...31]
Address[0...11]
YPbPr
DDR
S-Video
VGA
Bypass Out
24C02(U14)
TTL Signals
(Used by MT8205)
CS4334
(U22)
Audio Bypass
DVI Audio in
YPbPr Audio in
(U17)
AV2 Audio
CD4052
AV1 Audio
I2C
MT8776
(U20)
AV Audio in
Audio L
& Audio R
5V
5V
I2C
MT8205 I2C
(U25)
UART0 (Communication with MT5351)
UART2 (MT5351 DownLoad)
Dout
MX232A
(U1)
EEPOROM
IDTQS3VH257
From MT3551
3.3V
5V
VGAI2C
Din
RS232
Signals
128Mb(U11)
EEPROM
24C16(U2)
5V
3.3V
2.5V
1.25V
LP2996
(U12)
1.25V
2.5V
Circuit Diagram
-
Power supply board of PDP Module, DGP-420WXGA
Power supply board of PDP Module, USP490M-42LP
Main (Video) board
Audio/Tuner board
ATSC board
Keypad board
Remote control receiver board
External L/R Speakers board
Remote control board
5
4
CN01
3-176976-2
2
1
L104
CH108200S
L103
CH108200S
R108
5W 15
R103
5W 20
T208
PFC COIL 200uH
D102
FEP30JP
PFC +
PFC+
190VS
CN03
3-176976-1
C101
275VAC 1uF
RELAY1
SDT-SH-118DM
TNR101
14D 621K
Q102,Q103,Q109
SPW20N60C3*3
R603
BD101
D25XB60
R112
R224
2.2M
PFC VCC
R115
1.5KF
R109
1W 4.7
3K
C108
680pF
R106
1W 4.7
R107
1W 4.7
R116
10KF
D213
LL4148
C114
0.68uF
R133
33KF
R114
R132
33KF
C115
3
EN
10
C220
RYC
D104
US1M
R142
6.8KF
R141
4.7KF
Q207
KRC103M
8
0.001uF
7
CT
R235
4.7KF
1
RT
C211
0.001uF
2
FB
R236
10KF
C301,301A
10V 2200uF*2
OUT
IS +
3
R608
120KF
Q702
KTC3207
VR601
5K
C212
0.0047uF
D211
1N5234B
T206
VA EER4042
D700
FSF10A60
60VA
R303
1KF
R704
22KF
R253
2W 240K
R700
VA
VS
R155
100KF
R152
100KF
R154
100KF
R153
100KF
R151
100KF
R150
100KF
R149
100KF
R148
100KF
R305
5W15
PFC ON/OFF
C213
630V 0.01uF
VA VCC
D209
LL4148
PC100
PC-17K1C
D303
1N5245B
R706
20KF
R229
1W 4.7F
VA DET
PC102
R707
2.7KF
Q208
KTA1281
Q300
FQP17N40
Q108
KTC3198Y
C701,702,704
100V 330uF
Q209
SPW11N80C3
R306
5W6.8
R245
10KF
GND
60VA
C304
50V 4.7uF
R247
1.2K
R246
5W 0.2
PFC GND
C215
C500
1KV0.001uF
R520
470F
R502
0
D202
BYV26EGP
D5001
SF30SC6
PC202
C200
630V 0.01uF
Q201
SPW11N80C3
IC500A
KA431AZ
R210
1W 10F
R511
15KF
6
4.7KF
SEL
CABLE
7
4
12
7
171825-4
171825-7
5
1-171825-2
9
171825-9
190VS
2
1
1
1-1123723-4
1-1123723-0
4
5VCTRL
8
1-1123723-8
CN809
9VSC
8
171825-8
1
2
171825-2
3
11
100F
50V0.01uF
10KF
50V0.01uF
R422
C411
10KF
R416 1KF
R415
15
16
17
18
19
20
21
14
INT1/RB3
11
INT0/RB2
10
BUZ/RB1
9
AN0/AVref/RB0
8
RD1
7
RD2
RD3
Xin
Xout
|RESET
Vss
RC0
RD0
6
VDD
5
AN6/RA6
AN6/RA6
4
13
2
7
6
21
20
16
18
17
19
변경
후
PH967C6
FEP30JP
JSS 2209
R420 4.7KF
R418 1KF
R417 1KF
R412 1KF
330F
R411
330F
3
13
2
12
2
15
9
4
5
8
1
RY ON/OFF
7
11
VS ON
2
3
RLY ON
6
8
6
변경
전
DGP-420WXGA
5VD OUT
6
60VA
ACD OUT
3
10
3
Xout
MULTI ON/OFF
3
2
AC DET
5
7
9
5
5VCTRL
2004/07/28
A
R423 1KF
4
5
6
R410
3
4
4
CN805
5
방전CTL
5VD
3
5
4
4
5VSC
VA,VS ON/OFF
6
8
50V 0.1uF
+30V DET
2
+9V DET
2
1KF
7
7
50V 0.1uF
C409
+12V DET
3
1
1KF
6
5VCTRL
R404
8
1
24V/30V
50V 0.1uF
C408
VA DET
4
VS_ON
12VSC
CN802
3
C407
+5V DET
2
1
50V 0.1uF
CN808
5
190VS
50V 0.1uF
C406
R403 1KF
2
SB5V
CN807
C405
일자/사유
SW400
VS DET
1
10
9
9VSC
GND
ACD
RLY_ON
60VA
1
4
+5VSTBY
3
CN801
50V 0.1uF
R409 2KF
CN806
CN804
50V 0.68uF
C404
PFC ON/OFF
1
C403
1KF
GND
AN5/RA5
AN4/RA4
1
R519
1.5KF
2
+9V DET
J2
0
GND
ON/OFF
GND
IC401
HMS87C1304A
9VSC
R518
3.9KF
C514
35V 47uF
RC1
R516
1KF
2
Vo
C516
35V 1000uF
2
Xin
+12V DET
R515
1.8KF
4
Vin
3
PC-17K1C
PC201
1
D10L20U
5VSC
CRST400
4MHZ
1
C410
LED400
GREEN
R514
2KF
CN803
A
R711
11KF
D212
1N5234B
C226
0.001uF
C401
50V 0.1uF
R526
D503
C227
0.001uF
C219
0.01uF
1
GND
C262
4.7uF
VR700
5K
3
OUT
IC502
KIA378R09PI
C201
0.01uF
Q701
KTC3207
IC202
KA7552A
R421
VCC
C400
50V 0.1uF
+12V /1.0A
C511
35V 47uF
R262
1KF
C520
VA ON/OFF
R709
36KF
PC206
3
IS +
GND
1
22
3
2
Vo
R532
1W 2.7K
C510
35V 470uF
C208
470pF
R703
36KF
IC400
KIA7045AP
24
Vin
D502
PC202
PC-17K1C
R719
18KF
NO
R406
VCC
1KF
R402
RA3/AN3
1
31GF6
4
R401
R513
2.7KF
R531
IC200
KA7552A
R217
10KF
R714
18KF
LED401
RED
R405
R219
10K
Q202
KRC103M
IS +
R712
18KF
REVISION HISTORY
R510
5W 1K
2
FB
0.22uF
R721
45.3KF
PC205
R400
1KF
5VCTRL
GND
ON/OFF
2
C205
R717
45.3KF
R252
1W 100R
PC206
PC-17K1C
C261
4.7uF
IC501
KIA278R12PI
C519
R718
45.3KF
5
OUT
PWM0/COMP0/RB4
C507
35V 47uF
5
R220
1/4W 100R
3
R702
33KF
10KF
C214
0.01uF
+30V DET
R512
15KF
R508
0R
OUT
R708
18KF
12
R507
5W 2.7K
GND
RT
R701
18KF
+30V/1.0A (+24V/1.25A)
R525
56KF
4
CT
1
FB
CS
R414 2KF
Output
6
7
4.7KF
GND
0.001uF
R218
R710
18KF
B
35V 47uF
C204
2
RA0/EC0
Adj
SUF30J
C506
50V 220uF
R216
100KF
R249
10KF
2
R509
3.3KF
CS
0.047uF
23
C505
1KV 0.001uF
1
R237
5W 0.1
R720
45.3KF
R261
1KF
PC205
PC-17K1C
3
R214
360RF
8
C218
RA2/AN2
R505
1W 4R7
D501
1uF
RT
R251
R504
1.8KF
R522
4.7KF
R716
45.3KF
IC500
KA317
Input
R212
10KF
Q200
KTA1281
C203
CT
1
GND
B
C202
7
4.7KF
R408 1KF
D203
LL4148
0.001uF
R250
3
D206
LL4148
C530
1uF
C217
+5V DET
R501
3.3KF
GND
LL4148
Q210
KRC103M
R503
1KF
PC201
8
1KF
D200
MULTI VCC
5VSC
1uF
VCC
+5VCTRL
VR500
2K
C216
GND
D500
SF30SC6
R248
100KF
R407
R209
2W 240K
C504,C555~C557
10V 2200uF*4
4
C550~C554
10V 2200uF*5
R715
45.3KF
35V 47uF
MULTI ON/OFF
L500
6*20 2.5uH
RA1/AN1
R500
1W 10
C
R705
20KF
1KV 100pF
1W 10
D302
US1M
R307
5W6.8
방전 CTL
AC DET
C700
D208
BYV26EGP
GND
D301
US1M
R615
18KF
PFC +
IC300
KA431AZ
R156
1KF
T207
MULTI EER4042
R627
120KF
R607
130KF
IC201
KA7552A
PC101
C302
0.68uF
PFC VCC
PFC +
R606
270KF
PC204
D226
LL4148
D106
US1M
R613
120KF
R243
1W 47R
C225
0.1uF
C263
10uF
R302
1.02KF
R146
2W 100
C120
35V 47uF
R604
120KF
R628
120KF
5
PC204
PC-17K1C
+5VSTBY
R301
220F
CS
C210
R260
2.4KF
D105
US1M
C128
35V 470uF
1uF
C117
35V 470uF
3
D108 1N5236B
R175
0
C209
D111
1N4148
U100
5M0280R-YDTU
1
C118
0.01uF
C126
250V 0.47uF
R602
2W 100K
35V 47uF
L301
PC101
PC-17K1C
PC100
VCC
R190
200KF
FB
R192
56KF
4
R195
56KF
0.1uF
R198
56KF
R140
7.5KF
C119
R189
200KF
2
R193
56KF
DRAIN
R196
56KF
GND
R199
56KF
Q107
KTC3198Y
R233
100KF
R136
10KF
D300
SB560
C121
630V 0.01uF
AC-1
C
PC102
PC-17K1C
27uH
D107
US1M
R231
5W 0.05
R620
2W 100K
R110
10KF
10KF
PFC+
R145
2W 240K
R232
1K
R137
T100
STBY EE1927
R143
3W 470K
R230
4.7KF
6
4
IS
VR
R134
24KF
CA
2
PK
8
R131
33KF
D
GND
Q206
KTA1281
4
R130
240KF
VC
R128
75KF
GT
Q105
KTA1281
R111
100F
15
R127
75KF
GND
R126
75KF
U101 UC3854N
RS
R125
75KF
IA
R612
12KF
Q106
KSP2907
R176
10KF
16
VS DET
C221
630V 0.1uF
1KV 220pF
190VS
Q104
KTC3209
C109
68PF
6
1W4R7
R228
1W 4.7
C123
35V 47uF
D109
1N5236B
13
50V 10uF
14
0.0022uF
12
10KF
1
VI
VO
VS
7
R129
150KF
9
R124
220KF
11
R122
18KF
C113
2.2uF
R135
R123
330KF
5
C112
330pF
RE
R121
160KF
CT
R120
160KF
SS
R119
180KF
C116
R118
180KF
MO
0.1uF
R117
180KF
R611
300KF
C601
R225
1M
R144
10F
R113
24KF
R227
1W 4.7
C111
PFC+
C602
250V 820uF
3KF
C102,103
250V 0.001uF
C110
470pF
D601
FSF10A60
R223
2.2M
TNR102
14D 621K
D
1KV 220pF
Q203,204
SPW11N80C3*2
C206
630V 0.047uF
VA VCC
R104
10W 0.02
LL4148
L102
23mH
C600
1W4R7
R610
300KF
R222
2.2M
D204
LL4148
D103
R600
C222
630V 0.1uF
D205
BYV26EGP
C105,106
450V 330uF
C104
630V 1uF
RYC
R609
300KF
R226
2W 240K
R221
2.2M
R102
1W 390KJ
1
D600
FSF10A60
T204,205
VS EER4042
L101
23mH
2
2
VCC
1
2
1
CN02
3-176976-1
3
VI
GND
F101
250VAC 8A
<
HIC_MICOM
m
D
<D
1
1
USP490M-42LP
A
B
C
D
E
MT8205E (PBGA388) LCDTV BOARD 4 LAYERS
DV18A
1. INDEX
2. LDO
3. MT8205E PBGA388
4. MT8205 ANALOG DECOUPLING
5. DDR MEMORY & FLASH
6. VGA IN & PC AUDIO IN
7. VIDEO IN & TUNER IO
8. AUDIO/VIDEO IN CIRCUIT
9. DVI INPUT
10.LVDS/CRT/TTL OUT
11.BACK LIGHT / KEYPAD
12.WM8776 & A/V BYPASS
13.ATSC INTERFACE
14.PDP INTERFACE
2
3
4
5
2
3
4
5
CE88
3
Q14
CB136
0.1uF
D28
1N4148
2N3904
2
0
R342
URST#
1
10
+
R341
47uF/16v
+12V
TUNER_12V
8205UP3_1
PWR_ GND
INVERTER_PWR
GPIO_DVD1
DV18A
6
6
13
13
3,13
3,13
7,10
7,10
3
4
+12V
7,10,13,14
TUNER_12V
7
8205UP3_1
3
PWR_GND
11
INVERTER_PWR 11
GPIO_DVD1
3
DV18A
2,3
ADD BY MTK
RSRXD
PCRXD
RSTXD
5VSB
+
CE1
220uF/16v
C220UF16V/D6H11
PCTXD
C1 0.1uF
5VSB
C2
0.1uF
C3
0.1uF
C5
0.1uF
U1
13
8
11
10
R1IN
R2IN
T1IN
T2IN
1
3
4
5
2
6
C+
C1C2+
C2V+
V-
R1OUT
R2OUT
T1OUT
T2OUT
12
9
14
7
VCC
16
GND
15
INVERTER_PWR
5VSB DV33A
J3
INVERTER_PWR
R335 R336
0/NC 0
1
2
3
4
5
6
7
8
ADD BY MTK
PWR_ GND
C4
0.1uF
3
8x1 W/HOUSING
DIP8/W/H/P2.54
MAX232A
1
DV33A
0.1uF
2
3
4
5
2
3
4
5
R337
10k
U2
1
2
3
4
NC
NC
NC
GND
VCC
WP
SCL
SDA
8
7
6
5
R3
10K
R4
10K
5
4
3
2
1
Add by MTK
EEPROM 24C16
SOP8/SMD
C132
20pF
1
2
C133
20pF
8205UP3_1 HIGH :POWER OFF
LOW :POWER ON
R1
10k
J1
GPIO_DVD1
S CL
SDA
1
9
8
7
6
5VSB
SYSTEM EEPROM
HOLE/GND
H2
5VSB
5VSB
1
9
8
7
6
CB1
9
8
7
6
10/NC
RSRXD
RSTXD
PCRXD
PCTXD
TXD
RXD
SCL
SDA
URST#
HOLE/GND
H1
9
8
7
6
DV33A
R73
SYS _PWR
5VSB
R112
8205UP3_1
R
R0603/SMD
R2
R6
10k
J4
SOT23/SMD
2N3904
1
2
3
4
R xD
TxD
8205UP3_1
1
5x1 W/HOUSING
PH5/2.0
R5
10k
Q1
2
3
RSRXD
RSTXD
PCRXD
PCTXD
TXD
RXD
S CL
SDA
URST#
Power down Reset circuit
3
4
4.7k
RS-232
4x1 W/HOUSING
DIP4/W/H/P2.0
2
Add by MTK
VCC
J2
1
2
3
4
5
6
7
8
9
10
11
HOLE/GND
H3
9
8
7
6
2
3
4
5
2
3
4
5
L44
L50
FB
BEAD/SMD/1206
FB
BEAD/SMD/1206
1
1
9
8
7
6
PWR_ GND
AUIO IN/OUT GND
DIGITAL GND
L1
TUNER_12V
+12V
+
FB
BEAD/SMD/0805
CE2
220uF/16v
C220UF16V/D6H11
+
CE3
47uF/16v
CB2
0.1uF
DIP11/P2.54
HOLE/GND
H4
9
8
7
6
2
3
4
5
2
3
4
5
From Power board.
J21
VCC
1
9
8
7
6
ANALOG INPUT GND
For Tuner
+12V
1
1
2
3
4
5
6
7
8
9
10
1
+12V
1
M1 1
M2 1
M3
1
V1 1
V2 1
V3 1
1
CON10
V4
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
INDEX
Sheet
Wednesday, October 12, 2005
E
1
of
15
A
B
C
D
E
4
4
Power ON alive source
R0805/SMD
U3
CE5
220uF/16v
3
DV33
CM1117-3.3V
ADJ/GND
L2
OUT
Vout
2
CB4
0.1uF
+
CE6
220uF/16v
+
CB5
0.1uF
L3
OUT
2
+
SOT223/SMD
CE7
220uF/16v
FB
BEAD/SMD/0805
CB6
0.1uF
3
AV33
DV33A
CM1117-3.3V
L4
OUT
AV33
2
FB
BEAD/SMD/0805
+
1
ADJ/GND
U5
IN
CB3
0.1uF
220uF/16v
TP1
TEST POINT DIP1.0
CM1117-3.3V
IN
0/NC
R0805/SMD
3
U4
3
CE4
FB
BEAD/SMD/0805
SOT223/SMD
R99
5VSB
DV33
SOT223/SMD
CE8
220uF/16v
C6
10uF/10v
DV33A
U6
CB7
0.1uF
3
+
CE9
100uF/16v
CB8
0.1uF
IN
ADJ/GND
+
IN
1
3
CM1117-1.8V
DV18A
TP2
L5
OUT
DV18A
2
+
1
VCC
ADJ/GND
0/NC
1
R96
SOT223/SMD
CE10
220uF/16v
FB
BEAD/SMD/0805
DV18A
CB9
0.1uF
DV18A
1,3
2
2
1
1
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
LDO
Wednesday, October 12, 2005
Sheet
E
2
of
15
C
D
E
R106
DV33A
XTALI
XTALO
ANALOGVDD
ADCV DD
APLLVDD
VPLLVDD
ADCPLLVDD1
ADCPLLVDD
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
PWM2VREF
ADC VDD0
ADC VDD4
AVCM
VOCM
VICM
VREFP4
V REFN4
DA CFS
DA CVREF
DACV DD
LVDDA
IR
ANALOGVDD
XTALO
XTALI
GND
APLL_CAP
GND
APLLVDD
ANALOGVDD
GND
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DV18A
VI7
VI8
VI9
VI10
VI11
GND
VI12
VI13
VI14
VI15
GND
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
DV IODCK
VGAVSYNC#
H SYNC_VGA
GND
DV18A
GND
ADCPLLVDD1
ADCPLLVDD
GND
GND
ANALOGVDD
AD CVDD0
R EDRED+
GREENGREEN+
VGASOG
BLUEBLUE+
GND
AD CVDD0
VOCM
GND
VICM
AD CVDD0
C RCR+
CBCB+
YY+
SOY
GND
AD CVDD0
SCSC+
S YSY+
GND
0
RSTVCC
CB135
0.1uF
XTALI
XTALO
ANALOGVDD
ADCVDD
APLLVDD
VPLLVDD
ADCPLLVDD1
ADCPLLVDD
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
PWM2VREF
ADCVDD0
ADCVDD4
AVCM
VOCM
VICM
VREFP4
VREFN4
DACFS
DACVREF
DACVDD
LVDDA
IR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
7,11
U7
ADC VDD4
ADC VDD4
MPX1
MPX2
GND
VREFP4
V REFN4
GND
AD IN4
AD IN3
AD IN2
AD IN1
AD IN0
ADCV DD
PWM2VREF
AUXTOP
AUXBOTTOM
GND
VPLLVDD
VPLLVDD
GND
GND
REXTA
VPLLVDD
LVDDA
AP7
GND
AP6
A N6
AP5
A N5
LVDDA
AP4
A N4
AP3
A N3
GND
CLK1+
CLK1AP2
A N2
LVDDA
AP1
A N1
AP0
A N0
GND
DACV DD
DA CVREF
DA CFS
GND
3
DACV DD
GND
DACV DD
G
GND
B
R
VS YNC
H SYNC
DV33A
2
GND
DV18A
GND
3
U27
LM809
SOT23/SMD
IN
CE81
+
URST#
2
OUT
22uF/25v
R270
100K
VFEVDD1
ADCVDD4
SIF
AF
ADCVSS4
REFP4
REFN4
ADCVSS
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
ADCVDD
PWM2VREF
AUXVTOP
AUXVBOTTOM
VPLLVSS
VPLLVDD
DLLVDD
DLLVSS
BGVSS
REXTA
BGVDD
LVDDA
A7P
A7N
CLK2P
CLK2N
LVSSA
A6P
A6N
A5P
A5N
LVDDB
A4P
A4N
A3P
A3N
LVSSB
CLK1P
CLK1N
A2P
A2N
LVDDC
A1P
A1N
A0P
A0N
LVSSC
DACVDDC
VREF
FS
DACVSSC
SVM
DACVDDB
DACVSSB
DACVDDA
G
DACVSSA
B
R
DE
VSYNCO
HSYNCO
VCLK
EBO7
EBO6
EBO5
EBO4
DVDD3I
EBO3
EBO2
EBO1
EBO0
EGO7
DVSS18
EGO6
EGO5
EGO4
EGO3
EGO2
EGO1
EGO0
ERO7
ERO6
ERO5
DVDD18
ERO4
ERO3
ERO2
DVSS3
ERO1
ERO0
OBO7
OBO6
OBO5
External Reset Circuit
MT8205
AE2
AF1
AF2
AE3
AF3
AE4
AF4
AC5
T11
AD5
AE5
AF5
AC6
AD9
AD6
AE6
AF6
AC7
AD7
AD18
AE7
AF7
AC8
AD8
AF8
P12
AE9
AF9
AE10
AF10
AC11
AD11
AF12
AE15
AD15
AC19
AC15
AF16
AE16
R12
AD16
AC16
AF17
AD17
AD14
AE14
AF14
AF13
AE13
AD13
AC13
AE8
AC10
AC17
AE12
AD12
AE11
T12
AF11
AE17
F_OE#
AF15
W E#
AC12
PCE#
AC14
AF18
AE18
DV33A
AD10
AF19
8205UP1_2 AE19
8205UP1_3 AF20
8205UP1_4 AE20
DV18A
AD19
GPIO_DVD1
AD20
AC20
AF21
8205UP3_0 AE21
8205UP3_1AD21
GND
P13
URST#
AC21
UP3_4
AD22
UP3_5
AC22
GPIO_DVD2 AF22
GPIO_DVD0 AE22
SW
AF23
GPIO
AE23
PWM0
AD23
PWM1
AC23
IR
AF24
R xD
AE24
TxD
AD24
GND
R13
I CE
AC24
HWS CL
AF25
HWSDA AE25
DVISCL
AF26
DVISDA
AE26
REQUEST#AB23
REA DY# AB24
DV33A
DV33A
DV33A
DV33A
AOSDATA3
DOUT
DACBCLK
DACLRC
DACMCLK
GND
A_DQ24
A_DQ25
A_DQ26
SDV25
A_DQ27
A_DQ28
GND
A_DQ29
SDV25
A_DQ30
A_DQ31
A_DQS3
A_DQM1
GND
A_DQS2
A_DQ23
A_DQ22
GND
A_DQ21
A_DQ20
DV18A
A_DQ19
SDV25
A_DQ18
A_DQ17
A_DQ16
A_RA4
GND
A_RA5
A_RA6
A_RA7
A_RA8
GND
A_RA9
A_RA11
A_CKE
SDV25
A_CLK
A_CLK#
GND
A_RA3
A_RA2
A_RA1
A_RA0
A_RA10
A_BA1
SDV25
DV18A
A_BA0
A_CS#
A_RAS#
GND
A_CAS#
A_WE#
A_DQ8
A_DQ9
A_DQ10
SDV25
A_DQ11
GND
A_DQ12
A_DQ13
GND
A_DQ14
A_DQ15
A_DQS1
GND
DV18A
V REF
GND
A_DQM0
A_DQS0
A_DQ7
SDV25
A_DQ6
A_DQ5
GND
A_DQ4
A_DQ3
SDV25
A_DQ2
A_DQ1
A_DQ0
DV33A
R7
10K/NC
D1
1N4148/SMD
URST#
CE11
+
10uF/25v/NC
Internal Reset Circuit
DV33A
R8
47k
DACBCLK
GND
HWSDA
HWSCL
DV18A
R15
R16
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
V REF
ORO7
ORO4
ORO2
VI[0..23]
F_A[0..20]
F_ D[0..7]
F_OE#
TXD
RXD
WE#
PCE#
8205UP3_0
MPX1
MPX2
R/NC
R/NC
R17
R18
0
0
AD IN3
AD IN2
AD IN1
AD IN0
R365
R366
R367
R368
10K
10K
10K
10K
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
VREF
5
5
5
5
5
5
5
5
5
5
5
5
5
5
ORO7
ORO4
ORO2
VI[0..23]
F_A[0..20]
F_D[0..7]
F_OE#
12
12
7
9,13
5
5
5
TXD
RXD
WE#
PCE#
8205UP3_0
MPX1
MPX2
1,13
1,13
13
5
11
8
8
OGO[0..6]
OGO[0..6]
7,9,13
OBO[0..7]
AP[0..7]
A N[0..6]
R
G
B
OBO[0..7]
AP[0..7]
AN[0..6]
11
10
10
R
G
B
10
10
10
RED+
R EDGREEN+
GREENBLUE+
BLUECVBS1+
CVBS1CVBS2+
CVBS2CVBS0+
CVBS0SOY
SY+
S YSC+
SCY+
YCB+
CBCR+
C RCLK1+
CLK1-
RED+
REDGREEN+
GREENBLUE+
BLUECVBS1+
CVBS1CVBS2+
CVBS2CVBS0+
CVBS0SOY
SY+
SYSC+
SCY+
YCB+
CBCR+
CRCLK1+
CLK1-
8
8
8
8
8
8
8
8
8
8
8
8
7
8
8
8
8
8
8
8
8
8
8
10
10
SCL_8205
SDA_8205
SCL_8205
SDA_8205
10
10
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1
AOSDATA3
MUTE
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1
AOSDATA3
MUTE
12
12
12
12
12
12
12
3
2
VGASOG
8
HSYNC_VGA 6
VGAVSYNC# 6
PWM0
8205UP3_1
8205UP1_2
8205UP1_3
SW
OGO7
PWM1
OGO4
DVISCL
DVISDA
11
1
9,11
13
13
12
12
9,13
9
9
GPIO_DVD0
GPIO_DVD1
GPIO_DVD2
7
1
7
10,14
10,14
10
10
PDP signal cotrol GPIO.
GPIO
GPIO
ORO6
ORO6
7,10
10
F_A21
AD IN4
URST#
DV18A
4
10
10
PDP power cotrol GPIO.
ORO1
ORO1
ORO3
ORO3
ORO5
ORO5
8205UP1_4
8205UP1_4
REQUEST#
READ Y#
SDA_8205
SCL_8205
9,13
9,13
9,13
9,13
VSYNC
HSYNC
GPIO_DVD0
GPIO_DVD1
GPIO_DVD2
DVD GPIO PORTS
UP3_5
UP3_4
DVIODCK
DVIDE
DVIHSYNC
DVIVSYNC
VS YNC
H SYNC
PWM0
8205UP3_1
8205UP1_2
8205UP1_3
SW
OGO7
PWM1
OGO4
DVISCL
DVISDA
REQUEST#
READY#
13
13
F_A21
ADIN4
URST#
DV18A
9
14
1
1,2
1
Title
DV18A
Size
C
Date:
A
DV IODCK
DV IDE
DV IHSYNC
DVIVSY NC
VGASOG
HS YNC_VGA
VGAVSYNC#
UP3_4 FOR S/W SCL
UP3_5 FOR S/W SDA
R9
1k
Change by MTK
AOSDATA1
BGA388/SOCKET
MT8205
OBO4
OBO3
OBO2
OBO1
OBO0
OGO7
OGO6
OGO5
GND
OGO4
OGO3
OGO2
OGO1
DV33A
OGO0
ORO7
ORO6
ORO5
ORO4
DV18A
ORO3
ORO2
ORO1
MUTE
F_A15
GND
F_A14
F_A13
F_A12
F_A11
F_A10
F_A9
F_A8
F_D0
F_D1
DV18A
F_D2
F_D3
F_D4
GND
F_D5
F_D6
F_D7
F_A0
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7
F_A16
DV33A
F_A17
F_A18
F_A19
F_A20
GND
F_A21
1
DV IDE
DVIVSY NC
DV IHSYNC
DV18A
C24
D24
A24
Y24
A25
A26
B26
F23
B25
B24
C26
C25
E24
N15
G26
G25
F26
F24
F25
E26
N16
E25
G24
D26
D25
H25
H26
P14
J25
J26
K25
P16
K26
L25
AA24
L26
H24
M25
M26
N25
J23
R16
J24
K23
K24
L23
R14
L24
M23
N26
H23
P26
P25
P15
M24
N23
N24
R26
P24
P23
U23
AA23
R24
R23
T24
R15
T23
U24
W26
V25
V26
V23
U25
T13
U26
T25
T15
T26
R25
W25
W23
Y23
G23
T16
Y26
Y25
AA26
V24
AA25
AB26
T14
AB25
AC26
W24
AC25
AD26
AD25
DE_DVI
VSYNC_DVI
HSYNC_DVI
DVDD18
AOSDATA0
AOSDATA1
AOSDATA2
DVDD3I
AOSDATA3
LIN
AOBCK
AOLRCK
AOMCLK
DVSS3
DQ24
DQ25
DQ26
DVDD2
DQ27
DQ28
DVSS2
DQ29
DVDD2
DQ30
DQ31
DQS3
DQM1
DVSS18
DQS2
DQ23
DQ22
DVSS2
DQ21
DQ20
DVDD18
DQ19
DVDD2
DQ18
DQ17
DQ16
RA4
DVSS2
RA5
RA6
RA7
RA8
DVSS18
RA9
RA11
CKE
DVDD2
RCLK
RCLKB
DVSS2
RA3
RA2
RA1
RA0
RA10
BA1
DVDD2I
DVDD18
BA0
RCS#
RAS#
DVSS2
CAS#
RWE#
DQ8
DQ9
DQ10
DVDD2
DQ11
DVSS18
DQ12
DQ13
DVSS2
DQ14
DQ15
DQS1
AVSS18
AVDD18
RVREF
DVSS18
DQM0
DQS0
DQ7
DVDD2
DQ6
DQ5
DVSS2
DQ4
DQ3
DVDD2
DQ2
DQ1
DQ0
OBO4
OBO3
OBO2
OBO1
OBO0
OGO7
OGO6
OGO5
DVSS18
OGO4
OGO3
OGO2
OGO1
DVDD3
OGO0
ORO7
ORO6
ORO5
ORO4
DVDD18
ORO3
ORO2
ORO1
ORO0
HIGHA7
DVSS18
HIGHA6
HIGHA5
HIGHA4
HIGHA3
HIGHA2
HIGHA1
HIGHA0
AD0
AD1
DVDD18
AD2
AD3
AD4
DVSS3
AD5
AD6
AD7
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
A16
DVDD3I
A17
IOA18
IOA19
IOA20
DVSS18
IOA21
IOALE
IOOE#
IOWR#
IOCS#
WR#
RD#
DVDD3
INT0#
UP12
UP13
UP14
DVDD18
UP15
UP16
UP17
UP30
UP31
DVSS18
PRST#
UP34
UP35
FCICLK
FCICMD
FCIDAT
GPIO0
PWM0
PWM1
IR
RXD
TXD
DVSS3
ICE
SCL
SDA
SCL0
SDA0
SCL1
SDA1
OBO7
OBO6
OBO5
C3
D3
C1
C2
L11
D1
D2
F2
D4
E1
E2
E3
E4
F1
F4
F3
G3
J3
G4
H3
K3
K4
J4
H4
L3
G2
G1
H2
H1
M12
J2
J1
K2
K1
L4
L2
L1
M2
M1
M11
N2
N1
P2
P1
M3
R2
R1
T2
T1
N12
N3
M4
N4
N11
T4
P3
R3
P4
U4
R4
U3
V4
T3
U1
U2
V1
V2
V3
W1
W2
AC9
W3
W4
Y1
Y2
Y3
P11
Y4
AA1
AA2
AA3
AA4
AB1
AB2
AB3
AB4
AC1
AC18
AC2
AC3
AC4
R11
AD1
AD2
AD3
AD4
AE1
VFEVSS1
AVCM
ADCVDD0
CVBS2N
CVBS2P
CVBS1N
CVBS1P
CVBS0N
CVBS0P
ADCVSS0
REFP0
REFN0
ADCVDD1
SCN
SCP
SYN
SYP
ADCVSS1
REFP1
REFN1
VFEVDD0
VOCM
VFEVSS0
VICM
ADCVDD2
CRN
CRP
CBN
CBP
YN
YP
SOY
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
RN
RP
GN
GP
SOG
BN
BP
ADCVSS3
REFP3
REFN3
VSYNC
HSYNC
DVSS
DVDD
ADCPLLVSS1
ADCPLLVDD1
ADCPLLVDD
ADCPLLVSS
SYSPLLVSS
SYSPLLVDD
TESTP
TESTN
XTALVDD
XTALO
XTALI
XTALVSS
APLL_CAP
APLLVSS
APLLVDD
DMPLLVDD
DMPLLVSS
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
DVSS18
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
VCLK_DVI
4
R104
L12
D5
C4
B1
A1
B2
A2
B3
A3
L13
B4
A4
C5
B5
A5
B6
A6
M13
D6
C6
D7
B7
N13
A7
C7
B8
A8
B9
A9
B10
A10
C8
D10
D9
C9
D11
C11
D8
B11
A11
B12
A12
D13
B13
A13
C10
D12
C12
C13
C14
N14
D14
L14
D15
C15
M14
L15
D16
B14
A14
C16
B15
A15
M15
A16
D18
D17
C17
C18
B16
A17
B17
A18
B18
C19
D19
E23
A19
B19
C20
D20
A20
L16
B20
C21
D21
A21
M16
B21
C22
D22
A22
B22
C23
D23
A23
B23
GND
AVCM
AD CVDD0
CVBS2CVBS2+
CVBS1CVBS1+
CVBS0CVBS0+
GND
5VSB
0
GND
B
1
A
B
C
D
Doc Number
Rev
V1.2
MT5205BGA388
Wednesday, October 12, 2005
Sheet
E
3
of
15
A
4
ADCV DD
DACV DD
AVCM
VOCM
VICM
VREFP4
V REFN4
ADC VDD0
ADC VDD4
PWM2VREF
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
XTALI
XTALO
DV18A
1,2,3
DACVREF
DACFS
ADCPLLVDD1
ADCPLLVDD
APLLVDD
ANALOGVDD
VPLLVDD
LVDDA
3
3
3
3
3
3
3
3
ADCVDD
DACVDD
AVCM
VOCM
VICM
3
3
3
3
3
VREFP4
VREFN4
ADCVDD0
ADCVDD4
PWM2VREF
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
XTALI
XTALO
3
3
3
3
3
3
3
3
3
3
3
D
MT8205 ANALOG DECOUPLING&DIGITAL DECOUPLING
AV33
E
DV33A
L7
L6
CE12
FB
BEAD/SMD/0603
CB11
+
C7
4.7uF
C0603/SMD
CE13
+
0.1uF
10uF/25v
DV18A
FOR DACVDD
AV33
10uF/25v
DACV DD
ANALOGVDD
L12
DV18A
CB10
0.1uF
C0603/SMD
GND
FB
BEAD/SMD/0603
C24
4.7uF
C0603/SMD
C8
4.7uF
C0603/SMD
FB
BEAD/SMD/0603
ADCPLLVDD1
DACV DD
C9
4.7uF
C0603/SMD
C10
0.1uF
CB32
0.1uF
C0603/SMD
ADCPLLVDD
0
CE14
22uF/25v
+
GND
CB12
0.1uF
C0603/SMD
GND
GND
R20
C13
4.7uF
C0603/SMD
C14
4.7uF
C0603/SMD
R101
VCC
FOR ADCVDD
AVCM
GND
3
IN
+
CB18
0.1uF
CE16
100uF/16v
GND
OUT
FB
BEAD/SMD/0805
CE17
220uF/16v
+
SOT223/SMD
CE18
10uF/25v
CB16
0.1uF
GND
CB36
0.1uF
C0603/SMD
R22
APLLVDD
0
GND
GND
ADC _VDD
+
C27
4.7uF
C0603/SMD
CB35
0.1uF
ADC_VDD
2
CB15
0.1uF
C0603/SMD
ADCV DD
FB
Vout
C15
4.7uF
C0603/SMD
L14
ADC VDD0
L8
CE15
47uF/16v
+
0/NC
CM1117-3.3V
VOCM
CB46
0.1uF
ANALOGVDD
CB14
0.1uF
C0603/SMD
GND
R0805/SMD
U8
CB45
4.7uF
GND
4
CB13
0.1uF
C0603/SMD
DACV DD
ADJ/GND
DA CVREF
DA CFS
ADCPLLVDD1
ADCPLLVDD
APLLVDD
ANALOGVDD
VPLLVDD
LVDDA
C
1
DV18A
B
CE20
22uF/25v
+
PWM2VREF
CB17
+
0.1uF
CE22
47uF/16v
CB20
0.1uF
C0603/SMD
GND
CB42
0.1uF
C0603/SMD
ANALOGVDD
GND
GND
C17
4.7uF
C0603/SMD
C18
4.7uF
C0603/SMD
VICM
CB22
0.1uF
C0603/SMD
GND
CB47
0.1uF
3
GND
3
AV33
VREFP4
ADC_VDD
C0603/SMD
CB44 4.7uF
CB48
4.7uF
C0603/SMD
V REFN4
R23
0
L10
L11
ADC VDD0
G ND
CB24
0.1uF
C0603/SMD
FB
BEAD/SMD/0805
CB49 4.7uF
C0603/SMD
VPLLVDD
GND
C20
0.1uF
ADC VDD0
CB28
0.1uF
CB30
0.1uF
GND
C19
4.7uF
C0603/SMD
FB
BEAD/SMD/0603
GND
VPLLVDD
DIGITAL DECOUPLING
DV33A
CB27
0.1uF
C0603/SMD
+
CE21
47uF/16v
C21
4.7uF
C0603/SMD
CB29
0.1uF
C0603/SMD
GND
ADC VDD0
CB33
0.1uF
CB43
0.1uF
CB25
0.1uF
CB26
0.1uF
CB31
0.1uF
C22
0.01uF
VPLLVDD
C23
3300pF
C25
4.7uF
C0603/SMD
GND
AV33
CB34
0.1uF
C0603/SMD
GND
L13
2
ADC VDD4
C26
4.7uF
C0603/SMD
FB
BEAD/SMD/0603
CB41
0.1uF
L9
LVDDA
GND
CB37
0.1uF
C0603/SMD
DA CVREF
C33
0.1uF/NC
GND
APLL_CAP
C32
1500pF
GND
100k
XTALI
XTALO
C11
33pF
CB38
0.1uF
C0603/SMD
CB39
0.1uF
C0603/SMD
FB
BEAD/SMD/0603
CB40
0.1uF
C0603/SMD
CB19 0.1uF
C0603/SMD
CE19
27MHz
C12
33pF
GND
REXTA
R24
3.3k
GND
DA CFS
R27
560
GND
GND
+
C16
0.1uF
47uF/16v
LVDDA
0603 PUT ON NEARLY BGA
R19
Y1
2
R21
0
DV18A
CB21 0.1uF
C0603/SMD
GND
C28
3300pF
C0603/SMD
C29
3300pF
C0603/SMD
C30
3300pF
C0603/SMD
C31
3300pF
C0603/SMD
LVDDA
CB23 0.1uF
C0603/SMD
0603 PUT ON NEARLY BGA
GND
TP5
LVDDA
L15
FB
R25
50/47R
AUXTOP
R26
50/47R
AUXBOTTOM
TP6
1
1
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
MT8205 DECOUPOMG--ANALOG
Sheet
Wednesday, October 12, 2005
E
4
of
15
A
B
C
SDV25
4
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
3
3
3
3
3
A_RA3
A_RA2
A_RA1
A_RA0
RN1
7
5
3
1
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
V REF
RWR#
PCE#
F_OE#
F_ D[0..7]
F_A[0..20]
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
VREF
PWR#
PCE#
F_OE#
F_D[0..7]
F_A[0..20]
3
3
3
3
3
3
3
3
3
13
3
3
3
3
A_RA4
A_RA5
A_RA6
A_RA7
RN3
7
5
3
1
22x4
RN5
A_RA8
7
A_RA9
5
A_RA11 3
1
22x4
RN7
7
5
3
1
A_DQ4
A_DQ5
A_DQ6
A_DQ7
RN9
7
5
3
1
A_DQ8
A_DQ9
A_DQ10
A_DQ11
A_DQ12
A_DQ13
A_DQ14
A_DQ15
8
6
4
2
D_RA3
D_RA2
D_RA1
D_RA0
8
6
4
2
D_RA4
D_RA5
D_RA6
D_RA7
D _DQ3
D _DQ4
8
6
4
2
D_RA8
D_RA9
D_RA11
D _DQ7
22x4
A_RA10 R31
22
D _DQ0
D _DQ1
D _DQ2
D _DQ3
8
6
4
2
D _DQ4
D _DQ5
D _DQ6
D _DQ7
RN10 47x4
7
5
3
1
8
6
4
2
D _DQ8
D _DQ9
D_DQ10
D_DQ11
RN12 47x4
7
5
3
1
8
6
4
2
D_DQ12
D_DQ13
D_DQ14
D_DQ15
8
6
4
2
D_DQ16
D_DQ17
D_DQ18
D_DQ19
47x4
D _DQ1
D _DQ2
D _DQ5
D _DQ6
D_DQS0
D_DQM0
D _WE#
D_CAS#
D_RAS#
D_CS#
D_BA0
D_BA1
D_RA10
D_RA0
D_RA1
D_RA2
D_RA3
3
D_DQ14
D_DQ13
D_DQ12
D_DQ11
D_DQ10
D _DQ9
D _DQ8
D_DQS1
V REF
D_DQM0
D_CLK#
D_CLK
D_CKE
CB50
RN18 47x4
7
5
3
1
RN20 47x4
A_DQ28 7
A_DQ29 5
A_DQ30 3
A_DQ31 1
D_DQ16
D_DQ17
D_DQ18
8
6
4
2
D_DQ20
D_DQ21
D_DQ22
D_DQ23
D_DQ19
D_DQ20
8
6
4
2
D_DQ24
D_DQ25
D_DQ26
D_DQ27
D_DQ23
8
6
4
2
D_DQ21
D_DQ22
D_DQS2
D_DQ28
D_DQ29
D_DQ30
D_DQ31
D_DQM1
D _WE#
D_CAS#
D_RAS#
D_CS#
47x4
A_DQS0
R33
47
D_DQS0
A_DQS1
R34
47
D_DQS1
A_DQS2
R35
47
D_DQS2
A_DQS3
R36
47
D_DQS3
D_BA0
D_BA1
D_RA10
D_RA0
D_RA1
D_RA2
D_RA3
VDD
VSS
DQ0
DQ15
VDDQ
VSSQ
DQ1
DQ14
DQ2
DQ13
VSSQ
VDDQ
DQ3
DQ12
DQ4
DQ11
VDDQ
VSSQ
DQ5
DQ10
DQ6
DQ9
VSSQ
VDDQ
DQ7
DQ8
NC
NC
VDDQ
VSSQ
LDQS
UDQS
NC
NC
VDD
VREF
DNU
VSS
LDM
UDM
WE
CK
CAS
CK
RAS
CKE
CS
NC
NC
A12
BA0
A11
BA1
A9
A10/AP
A8
A0
A7
A1
A6
8M
x
16
A2
A5
DDR
A3
A4
VDD
VSS
D_DQ31
D_DQ30
D_DQ29
7
5
3
1
A_BA1
R38
A_BA0
R40
8
6
4
2
22x4
D_CS#
D_RAS#
D_CAS#
D _WE#
22
D_BA1
22
D_BA0
A_DQM0
R43
22
D_DQM0
A_DQM1
R45
22
D_DQM1
A_CKE
R47
22
D_CKE
A_CLK
R49
22
D_CLK
A_CLK#
R51
22
D_CLK#
7
5
3
1
D_DQ28
D_DQ27
D_DQ26
D_DQ25
D_DQ24
1
3
5
7
R30
10k
D _DQ0
D _DQ1
D _DQ2
D _DQ3
RN8
7
5
3
1
D _DQ4
D _DQ5
D _DQ6
D _DQ7
RN11
7
5
3
1
D _DQ8
D _DQ9
D_DQ10
D_DQ11
RN13
7
5
3
1
D_DQS3
V REF
CB79
8
6
4
2
0.1uF
PWR#
1
2
3
4
D1V25
V REF
TP7
GND
VTT
SD
PVIN
VSENSE AVIN
VREF
VDDQ
IC LP2996 DDR Termination SOP8
CB95
CB96
0.1uF
0.1uF
+
+
12
RESET
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A18
NC
WP/ACC
BYTE
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
16
13
14
47
VCC
37
GND1
GND2
27
46
F_ D0
F_ D1
F_ D2
F_ D3
F_ D4
F_ D5
F_ D6
F_ D7
DV33A
DV33A
R28
F_A0
F_A19
4
R29
0
10k
FLASHVCC
CB51
0.1uF
TSOP 48 pin
D1V25
CB52
0.1uF
CB53
0.1uF
CB54
0.1uF
CB55
0.1uF
CB56
0.1uF
CB57
0.1uF
CB58
0.1uF
CB59
0.1uF
CB77
0.1uF
CB61
0.1uF
CB62
0.1uF
CB63
0.1uF
CB64
0.1uF
CB65
0.1uF
CB66
0.1uF
CB67
0.1uF
CB78
0.1uF
75x4
8
6
4
2
D1V25
CB60
0.1uF
75x4
8
6
4
2
3
D1V25
75x4
1
3
5
7
CB68
0.1uF
CB69
0.1uF
CB70
0.1uF
CB71
0.1uF
CB72
0.1uF
CB73
0.1uF
CB74
0.1uF
CB75
0.1uF
CB76
0.1uF
75x4
1
3
5
7
D1V25
+ CE24
75x4
220uF/16v
2
4
6
8
C34
3300pF
C35
3300pF
C36
3300pF
C37
3300pF
C38
3300pF
C39
3300pF
C40
3300pF
C41
3300pF
CB81
0.1uF
CB82
0.1uF
CB83
0.1uF
CB84
0.1uF
CB85
0.1uF
CB86
0.1uF
CB87
0.1uF
CB89
0.1uF
CB90
0.1uF
C42
3300pF
C43
3300pF
C44
3300pF
C45
3300pF
C46
3300pF
C47
3300pF
C48
3300pF
C49
3300pF
CB97
0.1uF
CB98
0.1uF
CB99
0.1uF
CB100
0.1uF
CB101
0.1uF
CB102
0.1uF
CB103
0.1uF
CB104
0.1uF
75x4
2
4
6
8
75x4
D_RAS#
D_CS#
D_BA0
D_BA1
SDV25
8
7
6
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
RY/BY
A19
A20
CE
OE
WE
D1V25
8
6
4
2
RN22
D_DQ31 1
D_DQ30 3
D_DQ29 5
D_DQ28 7
4.7k
U12
D1V25
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
15
9
10
26
28
11
MX29LV160BT
SDV25
RN23
7
5
3
1
8
6
4
2
SDV25
SDV25
CB80
0.1uF
75x4
R41
F_A20
PCE#
F_OE#
DV33A
75x4
RN21
D_DQ27 1
D_DQ26 3
D_DQ25 5
D_DQ24 7
D_RA11
D_RA9
D_RA8
D_RA7
D_RA6
D_RA5
D_RA4
Del By Ada
75
RN19
D_DQ20 2
D_DQ21 4
D_DQ22 6
D_DQ23 8
D_DQM1
D_CLK#
D_CLK
D_CKE
DV33A
75x4
RN17
D_DQ16 2
D_DQ17 4
D_DQ18 6
D_DQ19 8
RN24
A_CS#
A_RAS#
A_CAS#
A_WE#
75x4
RN14
D_DQ12 7
D_DQ13 5
D_DQ14 3
D_DQ15 1
M13L128168 8Mx16-6/NC FOR ENTRY
2
RN4
8
6
4
2
D_RA10 R32
D_RA11
D_RA9
D_RA8
D_RA7
D_RA6
D_RA5
D_RA4
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
D_RA4
D_RA5
D_RA6
D_RA7
8
6
4
2
75x4
0.1uF
SDV25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
D_RA0
D_RA1
D_RA2
D_RA3
RN2
7
5
3
1
RN6
2
D_RA11 4
D_RA9
6
D_RA8
8
U11
RN16 47x4
A_DQ20 7
A_DQ21 5
A_DQ22 3
A_DQ23 1
A_DQ24
A_DQ25
A_DQ26
A_DQ27
D_DQ15
SDV25
RN15
7
5
3
1
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7
F_A8
F_A9
F_A10
F_A11
F_A12
F_A13
F_A14
F_A15
F_A16
F_A17
F_A18
D1V25
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
VSS
DQ0
DQ15
VDDQ
VSSQ
DQ1
DQ14
DQ2
DQ13
VSSQ
VDDQ
DQ3
DQ12
DQ4
DQ11
VDDQ
VSSQ
DQ5
DQ10
DQ6
DQ9
VSSQ
VDDQ
DQ7
DQ8
NC
NC
VDDQ
VSSQ
LDQS
UDQS
NC
NC
VDD
VREF
DNU
VSS
LDM
UDM
WE
CK
CAS
CK
RAS
CKE
CS
NC
NC
A12
BA0
A11
BA1
A9
A10/AP
A8
A0
A7
A1
A6
8M
x
16
A2
A5
DDR
A3
A4
VDD
VSS
M13L128168 8Mx16-6
47x4
A_DQ16
A_DQ17
A_DQ18
A_DQ19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
D _DQ0
D_RA10
8
6
4
2
E
U9
U10
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
A_DQ0
A_DQ1
A_DQ2
A_DQ3
D
SDV25
CE25
47uF/16v
CE26
220uF/16v
D_DQS2
R37
75
D_DQS3
R39
75
D_CAS#
R42
75
D _WE#
R44
75
D_DQM1
R46
75
D_DQS1
R48
75
D_DQS0
R50
75
D_DQM0
R52
75
2
SDV25
CB88
0.1uF
CB91
CB92
CB93
CB94
0.1uF
0.1uF
0.1uF
0.1uF
SDV25
SDV25
SDV25
SDV25
CB106
CB107
CB108
CB109
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VCC
U13
L16
V REF
3
VREF
1
FB
BEAD/SMD/0805
VREF DECOUPLING
+ CE31
V REF
220uF/16v
CB110
CB111
CB112
CB113
CB114
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
IN
ADJ/GND
CB105
CM1117-2.5V
OUT
2
+ CE27
220uF/16v
1
VREF
+ CE28
220uF/16v
+ CE29
220uF/16v
+ CE30
220uF/16v
SOT223/SMD
1
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
DDR MEMORY&FLASH
Wednesday, October 12, 2005
E
Sheet
5
of
15
A
B
C
D
E
VGA_IN_L
VGA_IN_R
HSYNC_VGA
VGAVSYNC#
RED_GND
GRN_GND
BLU_GND
R ED
GREEN
BLUE
RSRXD
RSTXD
P2
R
4
L
R56
15K
VGA_L
R58
15K
VGA_IN_R
VGA_IN_L
R59
75K
L17
D13
HSYN C#
VSYNC#
C51
5pF
VCC
3
SOT23/SMD
GRN_GND
2
BLUE
D15
SOT23/SMD
VGA_PLUGPWR
16
VGA_PLUGPWR
RSRXD
CB115
0.1uF
R53
10k
U14
1
2
3
4
NC
NC
NC
GND
VCC
WP
SCL
SDA
8
7
6
5
EEPROM 24C02
VGASCL
VGASDA
R54
10k
VGASDA
VGASCL
R55
R57
100
100
VGA_SDA
11
13
VSYNC#
14
VGA_SCL
15
3
VCC
D-SUB15 FEMALE
DSUB15/DIP/F
R ED
RED_GND
GREEN
GRN_GND
BLUE
BLU_GND
RSTXD
VGA_PWR
1
6
2
7
3
8
4
9
5
10
12
HSYN C#
BLU_GND
P3
1
VGA_PLUGPWR
2
VCC
SOT23/SMD
D17
GND
3
2
R62
2.2k
GREEN
D14
1
FB
BEAD/SMD/0603
VCC
2
HSYNC_VGA
3
HSYN C#
1
SOT23/SMD
RED_GND
3
D16
GND
VCC
SOT23/SMD
3
C50
0.1uF
Modified by Bin_wang.22/7/05
2
Change by MICO
L18
3
4
Change by MICO
1
R61
2.2k
12
12
3
3
8
8
8
8
8
8
1
1
R ED
VGAVSYNC#
FB
BEAD/SMD/0603
75K
2
VSYNC#
R60
1
PHONEJACK/DIP
VGA_R
K1
K2
K3
K4
K5
PHONEJACK STEREO
1
2
3
4
G
VGA_IN_L
VGA_IN_R
HSYNC_VGA
VGAVSYNC#
RED_GND
GRN_GND
BLU_GND
RED
GREEN
BLUE
RSRXD
RSTXD
VCC
DIODE SMD
1N4148/SMD
D3
VGA_PLUGPWR
D2
2
DIODE SMD
1N4148/SMD
17
GND
1
1
Title
Size
B
Date:
A
B
C
D
Doc Number
Rev
V1.2
VGA IN&PC AUDIO IN
Wednesday, October 12, 2005
Sheet
E
6
of
15
A
Y1SWB
ORO2
1
2
3
4
YPB PR1/R
YPB PR2/R
4
DVI/R
GND
DV I/L
GND
5
3
4
C53
0.1uF
1000uF/16v
J6
0 CR 1B
AV1_R
AV1_L
2
Y2_I NB
0 Y2B
CE37
22uF/10V
Y2SWB
R72
VCC
22uF/25v
75
Y2_ GNDB
CB2_INB
CB1_GNDB
0 CB2B CE39
R74
22uF/10V
CB2SWB
CE85
VCC
6
CE40
22uF/10V
CR 2SWB
3
C R1_GNDB
1
1
2
3
4
5
6
7
8
9
10
VCC
C124 4.7nF
0
C R2_GNDB
FB10
0
PH10/2.0
FB11
0
CB1_GNDB
FB12
0
C R1_GNDB
FB13
0
16
Y
X
3
13
INH
6
VEE
VSS
7
8
A V/R
AV/L
ADD BY MICO
AV1_L
R350
0/NC
AV/L
AV1_R
R351
0/NC
A V/R
R285
47k
22uF/25v
DV D/Y_IN
R78
0
Y3BCE34
22uF/10V
Y3SWB
2
2
R79
75
DV I_R
DVD/Y_GND
DV I/L
15K
R84
DVI_L
YPB PR2/R 15K
R97
Y PBPR2_R
YPBPR2/L 15K
R94
YPBPR2_L
A V/R
15K
R103
AV_R
AV/L
15K
R102
AV_L
YPB PR1/R 15K
R92
Y PBPR1_R
YPBPR1/L 15K
R87
YPBPR1_L
3
R86
1
15K
Y3_ GNDB
VCC
DVD /CB_IN
2
DVI/R
0 CB3B CE36
R85
22uF/10V
+12V
CB3SWB
D11
BAV99
R89
75
VCC
DVD /CB_GND
VCC
R98
DVD/CR_ IN
R118 R119 R120 R121 R122 R123 R124 R125
75K
75K
75K
75K
75K
75K
75K
75K
NEARLY YPBPR1-CON.
0 CR 3B CE38
22uF/10V
CR 3SWB
R267 R268
22K
22K
4
3
2
1
R269
10K
R100
75
D12
BAV99
DVD/CR _GND
VCC
CB3_GNDB
+
Y1_ GNDB
VCC
D VD/R
C R3_GNDB
GPIO
R95
1
4.7k
VCC
1
G2
S2
G1
S1
J9
L48
U26
D2
D2
D1
D1
DVD+5V
DVD+5V
DVD+5V
5
6
7
8
FB
BEAD/SMD/1206
5
4
3
2
1
GND
GND
IR7314
3
0
FB7
Y3 SOY
U17
0X
0Y
1X
1Y
2X
2Y
3X
3Y
A
B
CD 4052BC
SOP16/SMD
R283
47k
CE87
10x1 W/HOUSING
3
FB6
CB2_GNDB
3
CB116
0.1uF
12
1
14
5
15
2
11
4
10
9
OGO6
GPIO_DVD0
R280
47k
VCC
R282
47k
22uF/25v
C R2_GNDB
3
Y2_ GNDB
9/05
+
NEARLY YPBPR2-CON.
DV D/L
R77
75
D10
BAV99
0
CR
R281
47k
CE86
D9
BAV99
1
FB3
0
R279
47k
AV2_R
2
CR_GND
R314
R300
10K
10K
22uF/25v
CB2_GNDB
0 CR 2B
R76
1
0
CB
CRQ
+
0
FB4
0
+
FB5
R299
22uF/25v
CR 2_INB
IR
CB _GND
R313
R278
47k VCC
R75
75
VCC
2
Y_G ND
Y
C BQ
5x1 W/HOUSING R.A.
PH5/2.5
SOT-23
2N3904
Q2
2
1
SOY
0
L21
FB
AV2_L
D8
BAV99
5
DVD /CB_GND
DVD /CB_IN
DVD/Y_GND
DV D/Y_IN
DVD/CR _GND
DVD/CR_ IN
0
R312
R276
47k
2
4.7K
DVD_ IR
SOT-23
2N3904
Q3
R311
YQ
VCC
R277
47k
CE84
J7
2
GPIO_DVD2
3
R107
SO YQ
VCC
R275
47k
CE83
VCC
3 S Y_IN
4SY_ GND1
D VD/R
DV D/L
4
GN DS
SO YQ
Y3 SOY
SOY
CRQ
CR 3SWB
CR
AV1_R
+
8/18 modify by steven
R12
10k
16
15
14
13
12
11
10
9
VCC
E#
I0D
I1D
YD
I0C
I1C
YC
R274VCC
47k
22uF/25v
+
R11
10k/NC
VCC
S
I0A
I1A
YA
I0B
I1B
YB
GND
AV1_L
Y2 SOY
C123 4.7nF
D7
BAV99
Y1_ GNDB
R272
47k
CE82
+
VCC
L19
FB
U15
IDTQS3VH257/TIV330
TSSOP16/SMD
VCC
C R1_GNDB
R71
AV1_GND
JP1
CON\SVHS
7
C BQ
CB3SWB
CB
YQ
Y3SWB
Y
GN DS
22uF/10V CR 1SWB
CE35
R70
75
+
SC _IN
2
SC_GND1 1
GN DS
Y1 SOY
Y2 SOY
SO YQ
CR 1SWB
CR 2SWB
CRQ
1
2
3
4
5
6
7
8
IDTQS3VH257/TIV330
TSSOP16/SMD
AV1 & S-VIDEO AUDIO IN
4x1 W/HOUSING
DIP4/W/H/P2.0
GPIO_DVD0
+
TU_12V
C54
0.1uF
C52
100pF
AV2_IN
AV2_GND
AV2_L
AV2_R
1
2
3
4
L23
+ CE42
1000uF/16v
CR 1_INB
C R1_GNDB
RCA1X3
RCA2X2/6P/DIP
TUNER_12V
16
15
14
13
12
11
10
9
+
+
5
6
VCC
E#
I0D
I1D
YD
I0C
I1C
YC
CB1_GNDB
VCC
R69
VCC
3
4
Change by MICO
CB1SWB
+
RCA2
RCA2/4P/DIP
22uF/10V
CB1_GNDB
AV1_IN
1
2
CE33
R66
75
D6
BAV99
RCA2
RCA2X2/6P/DIP
2 DVI/R
TU_VCC
C128
100pF
YPBPR2/L
2
1DV I/L
L22
CE41
C127
100pF
CB1B
0
D5
BAV99
P6
P7
R65
CB1SWB
CB2SWB
C BQ
Y1SWB
Y2SWB
YQ
GN DS
S
I0A
I1A
YA
I0B
I1B
YB
GND
R67
10K
L20
FB
U16
1
2
3
4
5
6
7
8
+
3
3
3,10
3
3,11
9
7
CR 1_INB
C R1_GNDB
EMC Ready
RCA1X3
RCA5/9P/Y
P5
YPBPR1/L
3
1
CB1_INB
C117
100pF
3
J8
6
4
CB1_INB
CB1_GNDB
3
1,10,13,14
Y1_I NB
Y1_ GNDB
3
8
C131
100pF
VCC
2
Y1_ GNDB
3
1
R68
10K
3
5
CR 2_INB
3
1
1
12
12
12
12
12
12
C130
100pF
VCC
2
YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R
DVI_L
DVI_R
2
CB2_INB
2
3
12
12
C129
100pF
VCC
VCC
VCC
1
ORO2
AV_L
AV_R
FB
Y1_ GNDB
2
3,9,13
FB
3
22uF/10V
R64
75
D4
BAV99
1
Y2_I NB
1
4x1 W/HOUSING
DIP4/W/H/P2.0
VCC
CE32
COMPONENTS SWITCH.
CON12
PH12/2.0
TUNER_12V
OGO6
GPIO_DVD0
GPIO
GPIO_DVD2
IR
0 Y1B
R63
P4
OGO[0..6]
+12V
OGO6
GPIO_DVD0
GPIO
GPIO_DVD2
IR
TV_GND
TV
Y1_I NB
1
+12V
1
2
3
4
5
6
7
8
9
10
11
12
SDA
S CL
SIF1_OUT
AF1_OUT
Y1 SOY
C122 4.7nF
J5
TU_12V
E
+
YPBPR1_L
Y PBPR1_R
YPBPR2_L
Y PBPR2_R
DVI_L
DV I_R
8
8
1,10
1,10
D
+
OGO[0..6]
ORO2
AV_L
AV_R
SIF1_OUT
AF1_OUT
SCL
SDA
TU_VCC
TUNER IN
5
TUNER_12V
8
8
8
8
8
8
3
8
8
8
8
8,12
8
8,12
8
8,12
8
6
SIF1_OUT
AF1_OUT
S CL
SDA
Y
Y_GND
CB
CB_GND
CR
CR_GND
SOY
SY_IN
SY_GND1
SC_IN
SC_GND1
AV2_IN
AV2_GND
TV
TV_GND
AV1_IN
AV1_GND
C
+
4
Y
Y_G ND
CB
CB _GND
CR
CR_GND
SOY
S Y_IN
SY_ GND1
SC _IN
SC_GND1
AV2_IN
AV2_GND
TV
TV_GND
AV1_IN
AV1_GND
B
1
Change by MTK
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
VIDEO IN & TUNER IO
Wednesday, October 12, 2005
E
Sheet
7
of
15
A
B
C
D
E
R128
Y
VGASOG
RED+
R EDGREEN+
GREENBLUE+
4
BLUE-
VGASOG
3
RED+
3
RED-
3
GREEN+
3
R130
TV
R90
C57
CVBS0
18
22
GREEN-
3
BLUE+
3
BLUE-
3
R93
56
C59
330pF
R132
TV_GND
0
FB2
R133
CB
47nF
C RY+
YSY+
S YSC+
SCCVBS0+
CVBS0CVBS1+
CVBS1CVBS2+
3
CVBS2-
MPX1
MPX2
CB+
3
CB-
3
CR+
3
CR-
3
Y+
3
Y-
3
SY+
3
SY-
3
SC+
3
SC-
3
CVBS0+
3
CVBS0-
3
CVBS1+
3
CVBS1-
3
CVBS2+
3
CVBS2-
3
MPX1
3
MPX2
3
R135
AV1_IN
R80
CB
CB _GND
CR
CR_GND
SOY
S Y_IN
SY_ GND1
2
SC _IN
SC_GND1
C65
330pF
AV1_GND
CVBS1_GND
FB1
0
R140
AV2_IN
18
22
C71
330pF
R142
CVBS2_GND
FB8
0
0
R108
7
Y_GND
7
CB
7
CB_GND
7
CR
7
CR_GND
7
SOY
3,7
SY_IN
7
SY_GND1
7
SC_IN
7
SC_GND1
7
AV2_IN
7,12
AV2_GND
7
C70
C73
SY
CVBS2-
0
22
R110
75
47nF
C74
330pF
R144
Close to 8205.
SY_ GND1
SY_GND
FB9
C75
0
0
R147
CE43
SC_GND1
C78
C80
15pF/NC
C81
15pF/NC
R148
C79
0
FB14
0
Close to 8205.
47nF
L24
RED
RED_ IN
FB
BEAD/SMD/0603
47nF/NC
R151
39k
R150
C84
15pF
39k
C85
15pF
MPX2
C83
68
R152
C86
5pF
RED _GND
47uF/16v
RED+
47nF
75
CE44
R149
SC-
47nF
MPX1
C82
AF1_OUT
SC+
47nF
C77
330pF
SC _GND
47uF/16v /NC
8.2K
22
R116
75
3
C76
SC
0
S Y-
47nF
R145
R114
SC _IN
SY+
47nF
0
R146
C R-
47nF
R143
S Y_IN
C72
FROM Tuner
Y
R141
100
CVBS2+
CR+
47nF
C68
15pF
CR_GND
CB-
47nF
C66
47nF
R111
56
AV2_GND
CVBS1-
C69
CVBS2
R137
C64
100
47nF
0
R105
4
100
CR
C67
CB+
47nF
R136
CB _GND
CVBS1+
47nF
R138
SIF1_OUT
Y_G ND
22
R82
56
OUTPUT
Y
C63
CVBS1
18
C61
C62
15pF
+
CR+
Y-
47nF
100
+
CB-
C58
100
CVBS0-
Y+
47nF
R131
Y_G ND
47nF
C60
CVBS0_GND
C56
15pF
CVBS0+
0
CB+
C55
100
R153
C87
100
L25
R ED-
47nF
FB
C88
R154
0
R155
68
2
VGASOG
4.7nF
AV2_IN
AV2_GND
TV
TV_GND
AV1_IN
AV1_GND
SIF1_OUT
AF1_OUT
TV
7,12
TV_GND
7
AV1_IN
7,12
AV1_GND
7
SIF1_OUT
7
AF1_OUT
7
RED
6
GREEN
6
L26
GREEN
GREEN_IN
FB
BEAD/SMD/0603
R156
75
C89
C90
5pF
GRN_ GND
R157
C91
100
BLUE
RED _GND
GRN_ GND
BLU_GND
BLUE
6
RED_GND
6
GRN_GND
6
BLU_GND
6
GREEN-
47nF
L27
FB
L28
RED
GREEN
GREEN+
47nF
BLUE
BLUE_IN
FB
BEAD/SMD/0603
R159
75
BLU_GND
R158
C92
68
BLUE+
47nF
C93
5pF
R160
C94
100
BLUE-
47nF
L29
FB
1
Close VGA input interface
1
Close to MT8205
INPUT
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
AUDIO/VIDEO IN CIRCUIT
Wednesday, October 12, 2005
E
Sheet
8
of
15
A
D
E
VI[0..23]
VCC
C111
10uF/10v
C112
220pF
C113
10uF/10v
C100
220pF
C101
10uF/10v
C102
220pF
C103
10uF/10v
DDCD VISCL
DDCD VISDA
Add By MTK
2
D32
SOT23/SMD
GND
VCC
3
3
VCC
1
D31
SOT23/SMD
GND
1
3
VCC
DATA1+
DATA1-
3
DVIAVCC
DATA0+
DATA0CLOCK+
CLOCK-
R165
390
EXT_RST
D VIPVCC
R83
DVIP WR
D VIPVCC
C98
220pF
DVI_PLUGPWR
0.1uF
2
NC
NC
NC
GND
VCC
WP
SCL
SDA
8
7
6
5
TQFP100/SMD
2
DVIODCK0
CTL3
OCK_INV
HS_DJTR
DVI23
DVI22
DVI21
DVI20
DVI19
DVI18
DVI17
DVI16
DDCD VISCL
DDCD VISDA
OGO4
D35
SOT23/SMD
GND
VCC
VCC
DATA2+
D37
SOT23/SMD
GND
VCC
D38
SOT23/SMD
GND
VCC
3
DVIHSYN C0
DVIV SYNC0
DVIDE0
DVIODCK0
DVI15
DVI14
DVI20
DVI21
DVI22
DVI23
DVI16
DVI17
DVI18
DVI19
DVI12
DVI13
DVI14
DVI15
D VI4
D VI5
D VI6
D VI7
TP12
DVI_PLUGPWR
GND
VCC
CHANGE
0
EEPROM 24C02
GND
D36
SOT23/SMD
TP9
TP10
TP11
D VI8
D VI9
DVI10
DVI11
R166
D34
SOT23/SMD
DATA1+
TP8
R310
10k
R169
10k
1
DATA0+
DVIP WR
CHANGE
R168
10k
SiI 169
DVIP WR
DVI_PLUGPWR
U19
1
2
3
4
ADD BY MTK
DVIRST#
DVI_PLUGPWR
SiI 161B
DVIHSYN C0
DVIV SYNC0
DVIDE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C97
10uF/10v
QO22
QO21
QO20
QO19
QO18
QO17
QO16
GND
VCC
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
OGND
OVCC
QO7
QO6
QO5
QO4
QO3
QO2
C134
1uF/25V/NC R81
10k/NC
FB BEAD/SMD/0603
C99
DVISCL
+
L33
0/NC
U18
GND
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
2
DATA2+
DATA2-
D VIAVCC
QO1
QO0
HSYNC
VSYNC
DE
OGND
ODCK
OVCC
CTL3
CTL2
CTL1
GND
VCC
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
QE14
1
C96
220pF
DVICAB
DATA2-
D33
SOT23/SMD
M_S#
DVI8
DVI9
DVI10
DVI11
DVI12
DVI13
0.1uF
OGND
QO23
OVCC
AGND
RX2+
RX2AVCC
AGND
AVCC
RX1+
RX1AGND
AVCC
AGND
RX0+
RX0AGND
RXC+
RXCAVCC
EXT_RST
PVCC
PGND
RESERVED
OCK_INV
DVISTAG
DVISCDT
DVIPDO#
DVI0
DVI1
DVI2
DVI3
DVI4
DVI5
DVI6
DVI7
CB118
C95
10uF/10v
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
4
R164
100k
DATA1-
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FB BEAD/SMD/0603
DVIP WR
HS_DJTR
PD#
ST
PIXS
GND
VCC
STAG_OUT
SCDT
PDO
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
OVCC
OGND
OE8
QE9
QE10
QE11
QE12
QE13
D VIAVCC
CLOCK+
CLOCK-
Add By MTK
DATA0-
DVIPD#
DVISDA
DVIPIXS
L32
R163
10k
DVIP WR
0.1uF
DVIP WR
1N4148/SMD
2
DVIP WR
CB117
100uF/16v
D30
SOT23/SMD
GND
D22
DVI_PLUGPWR
DATA0DATA0+
2
+ CE45
VCC
31
34
32
D18
3
DVIP WR
FB
GND
3
DVIPWR
1
L31
1
D29
SOT23/SMD
DV33
29
33
30
DDC _SDA
2
DDC _SCL
2
CLOCK2
CLOCK+
13
14
15
16
17
18
19
20
21
22
23
24
3
C110
220pF
DVIPDO#
R
0 8205UP1_2
1
2
3
4
5
R161
100 DDC _SCL 6
R162
100 DDC _SDA 7
8
DATA19
DATA1+
10
11
12
1
C109
10uF/10v
DATA2DATA2+
2
C108
220pF
DVIPWR
3
C107
10uF/10v
DVIPWR
3
C106
220pF
DVIPWR
1
C105
10uF/10v
DVIPWR
2
C104
220pF
DVIPWR
1
DVIPWR
DIODE SMD
1N4148/SMD
27
25
DVIPWR
DVI-I DIP 34P
28
26
DVISCDT R167
DVICAB R177
P8
1
DVIODCK
DVIDE
DVIHSYNC
DVIVSYNC
8205UP1_2
OGO4
DVISCL
DVISDA
F_A21
3
4
C
3
VI[0..23]
DV IODCK
DV IDE
DV IHSYNC
DVIVSY NC
8205UP1_2
OGO4
DVISCL
DVISDA
F_A21
B
D VI0
D VI1
D VI2
D VI3
DVIPWR
2 RN25
4
6
8
1
3
5
7
33x4
DV IHSYNC
DVIVSY NC
DV IDE
DV IODCK
1
3
5
7
33x4
2 RN27
1
4
3
6
5
8
7
33x4
VI20
VI21
VI22
VI23
2 RN28
4
6
8
1
3
5
7
33x4
2 RN29
1
4
3
6
5
8
7
33x4
VI12
VI13
VI14
VI15
2 RN30
4
6
8
VI4
VI5
VI6
VI7
2 RN26
4
6
8
DVIPWR
R171
10k
DVIPD#
RED
VI16
VI17
VI18
VI19
DVIPDO#
R344
R176
R/NC
R/NC
GREEN
VI8
VI9
VI10
VI11
1
3
5
7
33x4
RN31
2
1
4
3
6
5
8
7
33x4
DVIPWR
R170
10k
WHEN USE Sil169//Sil161 ADD R175 , NC R345
WHEN USE Sil1169 ADD R345,NC R175
2
DVIPWR
R345
10k/NC
BLUE
VI0
VI1
VI2
VI3
Add by MTK
DVIPIXS
R175
0
R88
R322
4K7
R323
4K7
0/NC
R324
4K7
R325
4K7
DVIPWR
DVIPWR
R0603/SMD
R326
10K
QF3
DDCD VISCL
2
DVISCL
3
1
DV33A
MOSFET N 2N7002
SOT23/SMD
F_A21
QF4
2
DV33A
1
DVISDA
3
1
DDCD VISDA
R91
R330
0
R346
10k/NC
M_S#
DVIRST#
When Sil169/Sil161 R346 NC
Add R347
0/NC
R0603/SMD
R173
10k/NC
When use Sil169//Sil1169 R172 NC,Add R326
WHhen use Sil161 R326 NC,Add R172
DVIP WR
DVIPWR
DVISCL
R174
10k/NC
R347
10k/NC
R172
0.1uF
MOSFET N 2N7002
SOT23/SMD
WHEN USE Sil169/sil1169 ADD
DVIPWR
DVISDA
DVISCL REPLACE OCK_INV NET
DVISDA REPLACE ST
WHEN SIL161 ADD R173 R174
WHEN Sil169/ Sil1169 R173 R174 NC
R327
4.7K/NC
R328
4.7K/NC
R329
4k7/NC
HS_DJTR
OCK_INV
DVISTAG
R331
0
R332
0
R333
0
1
WHEN USE Sil1169 add R331 R332
WHEN USE Sil169 add R327 R332
WHEN USE Sil161 NC R331 R332
When use Sil169/Sil1161 ADD R333
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
DVI INPUT
Wednesday, October 12, 2005
Sheet
E
9
of
15
A
+12V
CLK1+
CLK1-
+12V
CLK1+
CLK1-
B
C
D
E
LVDS OUT(Include PDP and 32' LCD LVDS interface)
1,7,13,14
3
3
5VSB
DV33A
4
AP[0..7]
A N[0..6]
R
G
B
VS YNC
H SYNC
S CL
SDA
ORO6
GPIO
ORO1
ORO3
ORO5
8205UP1_4
SCL1
SDA1
SCL_8205
SDA_8205
AP[0..7]
AN[0..6]
R
G
B
VSYNC
HSYNC
3
3
3
3
3
3
3
SCL
SDA
ORO6
GPIO
1,7
1,7
3
3,7
ORO1
ORO3
3,14
3,14
ORO5
8205UP1_4
3
3
SCL1
SDA1
12
12
SCL_8205
SDA_8205
3
3
4
J10
R361 R362 R363
10K
10K
10K
R301
10K
ORO5 Repalce ADIN2
8205UP1_4 Repalce ADIN3
R302 R303
10K
10K
+12V
+
+12V
CE46
220uF/16v
A N6
R290
ORO5
R291
AP6
R292
8205UP1_4R293
0/NC
0/NC
0/NC
0/NC
AP7
R178
0/NC
GPIO
R179
0/NC
A N0
AP0
A N1
AP1
A N2
AP2
CPUGO
PDPGO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CLK1CLK1+
A N3
AP3
A N4
AP4
SEL_AP7_IRQ
A N5
AP5
VCC
5VSB
Change by MICO
DV33A
5VSB
R364
10K
F1
L34
BEAD/SMD/1206
BEAD/SMD/1206
LVDSVDD
FB
BEAD/SMD/1206
R184
10k
ORO6
2
L51
L52
4.7k
1
R189
4A/?v
FUSE/DIP/P10.0 +
CE47
330uF/25v
C330UF25V/D8H14
SOT23/SMD
2N3904
Q4
Change By MTK
Ada
R286
4.7k
DI SPEN_PDWN_READY R185
SCL_P
R186
SDA_P
R187
LVDSVDD
0
100/NC
100/NC
L49
FB
BEAD/SMD/1206
3
FB
FB
R180
4.7k/NC
DV33A
Change by MICO
FI-SE30P-HF
LVDS/30P/P1.25/S
3
3
+
WHEN USE
WHEN USE
WHEN USE
WHEN USE
CE48
220uF/16v
+
CE49
220uF/16v
CB119
0.1uF
CB120
0.1uF
LG V6 PDP ,ADD R185 R286 ,Must del R193 R194
LG V7 PDP ,ADD R185 R286 R179
SangsungSD1 PDP ,ADD R186 R187 R185 R286
Fujitsu 42 PDP ,ADD R179 R186 R187 R185 R286 R291 R293.REMOVE R178 R290 R292
WHEN NOT USE PDP ADD L49 R178 R290 R292
REMOVE R179 R185 R186 R187 R291 R293
3,14
3,14
4.7K REPALAC 47K
2
5VSB
DV33A
R181
4.7k
R183
4.7k
2
S CL
DV33A
5VSB
R191
4.7k
3
2
MOSFET N 2N7002
SOT23/SMD
DV33A
R352 R353
10K
10K
SDA_8205
3
DV33A
R348 R349
10K
SCL_8205
QF2
SDA
5VSB
R182
4.7k
QF1
1
ORO1
ORO3
1
ORO1
ORO3
MOSFET N 2N7002
SOT23/SMD
2
R
R188
0
SCL1
R192
0
SCL_P
R295
0
SDA1
R195
75 1%
R297
0
R
G
B
R196
75 1%
R298
0
R296
0
GND
SDA_P
B
10K
R193
0/NC
ORO3
R194
0/NC
H SYNC
VS YNC
1
2
3
4
5
6
7
8
GND
R197
75 1%
ORO1
CRT OUT J11
GND
G
8x1 W/HOUSING
DIP8/W/H/P2.54
GND
CHANGE
1
1
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
LVDS/CRT OUT
Wednesday, October 12, 2005
Sheet
E
10
of
15
A
IR
PWR_ GND
INVERTER_PWR
OBO0
OBO1
OBO2
4
OBO3
OBO4
OBO5
OBO6
OBO7
8205UP3_0
PWM0
8205UP1_2
IR
3,7
PWR_GND
1
INVERTER_PWR 1
OBO0
3
OBO1
3
OBO2
3
OBO3
3
OBO4
3
OBO5
3
OBO6
3
OBO7
3
8205UP3_0
3
PWM0
3,14
8205UP1_2
PWR_GND
D
E
3
PANEL INVERTER POWER
In verter_PWR
CE50
470uF/50v
+
+
CE51
470uF/50v
CB121
0.1uF
In verter_PWR
CB122
0.1uF
PWR_ GND
4
FOR AU 32" INVERTER CONNECTOR
VCC
J12
In verter_PWR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R199
10k
3,9
R200
1
2
PWR_ GND
OBO[0..7]
C
R201
4.7k
1
3
PWM0
Dimming
100k
Q5
2N3904
SOT23/SMD
CB123
0.1uF
PWR_ GND
VCC
14x1 W/HOUSING
DIP14/WH/P2.0/R
SELECT
R203
10k
Back Light circuit
8205UP3_0
1
3
4.7k
VCC
R202
R
R204
0
BL_ON/OFF
2
R205
R. ANGLE
OBO[0..7]
B
External PWM input
for dimming control
Q6
2N3904
SOT23/SMD
3
3
In verter_PWR
1
2
3
4
5
6
7
8
9
10
PWR_ GND
R. ANGLE
J13
10x1 W/HOUSING R.A.
DIP10/WH/P2.0/R
L35
FB
BEAD/SMD/1206
L36
FB
BEAD/SMD/1206
5VSB
R109
KEYPAD - MAX 8-KEYS
R320 R319R318R317 R316 R315
10K
10K
10K
10K 10K 10K
9/05
2
5VSB
R206
R209
R208
10K
R0603/SMD
510
510
5VSB
8205UP1_2
R210
0
L37
L38
L39
L40
L41
L42
POW
2
R207
10K
R0603/SMD
OBO0
OBO1
OBO2
OBO3
OBO4
OBO5
IR
LED_RED
LED_GRN
Q7
2N3906
1
R212
4.7K
Q8
2N3906
1
TV/AV
MENU
VOLVOL+
C HCH+
TV/AV
MENU
VOLVOL+
C HCH+
8205UP1_2
1
2
3
4
5
6
7
8
9
2
CON9
J20
IR
LED_RED
LED_GRN
POW
2
4.7K
FB
FB
FB
FB
FB
FB
DIP13/W/H/P2.0
13x1 W/HOUSING
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
3
OBO7
R211
3
OBO6
J19
J14
10K
DV33A
CONN RCPT 5
IR & POWER ON LED
1
1
Title
Size
C
Date:
A
B
C
D
Doc Number
Rev
V1.2
BACK_LIGHT/KEYPAD
Sheet
Wednesday, October 12, 2005
E
11
of
15
B
C
D
VCC
100k
10uF/25v
10uF/25v
R224
100k
R225
100k
R226
100k
10uF/25v
R227
100k
1
2
3
4
5
6
7
8
9
10
11
12
DACBCLK
DACMCLK
AOSDATA1
DACLRC
DACBCLK
DACMCLK
DOUT
AIN2L
AIN1R
AIN1L
DACBCLK
DACMCLK
DIN
DACLRC
ZFLAGR
ZFLAGL
ADCBCLK
ADCMCLK
DOUT
DACLRC
DACL RC
3
CODHPOUTR C125
C116
100pF
4
10uF/10v
HPV DD
+
CE62
10uF/25v
10uF/10v
CB125
0.1uF
Change
J15
AD CREFP
AD CREFP
VMIDADC
VMIDADC
+
H PVDD_
+
VMIDDAC
COD_VOUTR
COD_VOUTL
+
CE70
10uF/25v
CE69
10uF/25v
CE67
10uF/25v
CB127
0.1uF
CB126
0.1uF
GND
GND
AUSPR
GND
GND
AUSPL
GND
1
2
3
4
5
6
7
8
MUTE
R230
10k
CB128
0.1uF
CON8
5VSB
WM8776
CE71
COD_VOUTR
10uF/25V
AUSPR
R231
3
10k
GND
TO AUDIO BD
CODHPOUTL
DVDD
DV DD
36
35
34
33
32
31
30
29
28
27
26
25
CODHPOUTR
DV33
DV33
R14
33
AVDD
ADCREFP
ADCREFGND
VMIDADC
AUXL
AUXR
DACREFP
DACREFN
VMIDDAC
VOUTR
VOUTL
NC
13
14
15
16
17
18
19
20
21
22
23
24
R229
1k
L45
100 SDA14
CODHPOUTL C126
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
AIN5R
AINOPL
AINVGL
AINOPR
AINVGR
AGND
10uF/25v
100 SCL14
SDA1 R218
C115
100pF
ADCLRC
DGND
DVDD
MODE
CE
DI
CL
HPOUTL
HPGND
HPVDD
HPOUTR
NC
VGA_IN_L CE65
SCL1 R216
HPVDD
U20
VGA_IN_R CE64
50k
R222
50k
10uF/25v
10uF/25v
R221
100k
CB124
0.1uF
+
R220
R219
+
MUST USE SHIELD CABLE
FB
+
CE73
CE72
47uF/16v
COD_VOUTL
CB130
0.1uF
AUSPL
+
3
3
3
3
10
10
CE61
10uF/25v
+
ORO4
ORO7
OGO7
PWM1
SCL1
SDA1
CE60
AV_L
100k
+
3
3,11
1,7,10,13,14
7,8
7
7
7,8
7,8
AV_R
100k
R217
+
MUTE
PWM0
+12V
TV
AV_L
AV_R
AV1_IN
AV2_IN
CE59
R215
10uF/25v
HPV DD
C114
HPV DD
YPBPR1_L
10uF/25v
L43
FB
SDA14
SCL14
Y PBPR1_R CE57
3
3
3
3
3
3
100k
48
47
46
45
44
43
42
41
40
39
38
37
CE56
R214
DV DD
YPBPR2_L
10uF/25v
+
Y PBPR2_R CE55
100k
+
ORO4
ORO7
OGO7
PWM1
SCL1
SDA1
CE54
R213
+
MUTE
PWM0
+12V
TV
AV_L
AV_R
AV1_IN
AV2_IN
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1
AOSDATA3
DVI_L
10uF/25v
+
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1
AOSDATA3
6
6
7
7
7
7
7
7
CE53
+
4
VGA_IN_L
VGA_IN_R
YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R
DVI_L
DVI_R
DV I_R
+
VGA_IN_L
VGA_IN_R
YPBPR1_L
Y PBPR1_R
YPBPR2_L
Y PBPR2_R
DVI_L
DV I_R
E
+
A
TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h
10uF/25v
R232
10k
A/V Bypass
VCC
R233
0
R0805/SMD
DACVA
FB15
FB
BEAD/SMD/0805
+
2
CE74
100uF/16V
CB132
1uF
+
CE75
100uF/16V
VCC
CB131
0.1uF
R334
10K
AUDIO BYPASS.
R234
R235
R236
R237
33
33
33
33
1
2
3
4
VCC
R306
10K
TV
C118 1uF
AV1_IN
C119 1uF
SDATA
AOUTL
DEM#/SCLK
VA
LRCK
AGND
MCLK
AOUTR
R307
10K
U23
IN1 OUT
A
VCC
B
IN3
IN2 GND
BA7612F
R240
75/NC
L_BYPASS
DACVA
8
7
6
5
OGO7
PWM1
R_BYPASS
CS4334 2-CH AUDIO DAC
SOP8/SMD
1
2
3
4
ORO4
ORO7
R13
U22
8
7
6
5
CE76
OGO7 Repalce ADIN0 -----MTK
PWM1 Repalce ADIN1 -----MTK
J16
0 V_BYPASS
1
LINE_MUTE 2
3
SPK SWICTH(PDP) BY MICO
4
L_BYPASS
5
R_BYPASS
6
5x1 W/HOUSING
PH6/2.0
+
AOSDATA3
DACBCLK
DACLRC
DACMCLK
R10
10k
2
220uF/16v R238
VCC
V_BYPASS
43,1%
AV2_IN
R239
75
R241
75/NC
1
1
Title
Size
C
Date:
A
B
C
D
Doc Number
WM8776/WM8766/AUDIO CODEC
Wednesday, October 12, 2005
Sheet
E
12
of
Rev
V1.2
15
A
+12V
+12V
1,7,10,14
TXD
RXD
TXD
RXD
1,3
1,3
DVIVSYNC
DVI HSYNC
DVIDE
DVIODCK
8205UP1_3
DVIVSYNC
DVIHSYNC
DVIDE
DVIODCK
8205UP1_3
3,9
3,9
3,9
3,9
3
DACMCLK
DACBCLK
DACLRC
DACMCLK
DACBCLK
DACLRC
3,12
3,12
3,12
READY#
READY#
3
REQUEST#
REQUEST#
3
OGO4
OGO5
OGO6
VI[0..23]
VI[0..23]
OGO3
OGO1
OGO2
OGO0
SW
PCRXD
PCTXD
WE#
PWR#
CE77
WE#
PWR#
3
5
CB133
0.1uF
+
220uF/16v
CE78
+
Trace width of 12V>30mil
Trace width of 5V >40mil
VCC
D1
D1
D2
D2
1
2
3
4
S1
G1
S2
G2
+12V
G ND
5V
"GND Need Very Strong"
+12V
5VSB
R338
0/NC
DV33A
R339
0/NC
1
2
3
4
5
6
7
RXD_2
G ND
3
14
13
12
11
10
9
8
DV33A
R243
22k
C135
56pF
R244
10k
U28
TXD
R242
22k
U30
TXD_2
R245
RXD
OGO5
1
0
74HCT04A/NC
Q9
2N3904
SOT23/SMD
C120
1uF
OGO3
OGO1
OGO2
OGO0
C121
1uF
VI0
VI1
VI2
VI3
Add by MTK
VCC
GND
2G
1G
19
1
3
5
7
9
2Y4
2Y3
2Y2
2Y1
2A4
2A3
2A2
2A1
17
15
13
11
12
14
16
18
1Y4
1Y3
1Y2
1Y1
1A4
1A3
1A2
1A1
8
6
4
2
5VSB
DV33A
SW
R251
0
R253
10k
2
3
3x1
JP3/DIP/P2.54
U29
WE#
SW
PWR#
1
1
2
3
4
5
6
7
MTK Modify
JP3
1
L46
FB/NC
TXD_2
PCTXD
RXD
RXD_2
PCRXD
TXD
1
2
3
4
5
6
7
8
U25
S
I0A
I1A
YA
I0B
I1B
YB
GND
VCC
E#
I0D
I1D
YD
I0C
I1C
YC
16
15
14
13
12
11
10
9
R250
RXD_0
PCRXD
TXD_0
READY0#
1
3
5
7
9
2Y4
2Y3
2Y2
2Y1
2A4
2A3
2A2
2A1
17
15
13
11
VI8
VI9
VI10
VI11
12
14
16
18
1Y4
1Y3
1Y2
1Y1
1A4
1A3
1A2
1A1
8
6
4
2
SW
0
74LVC00A/NC
1
Function
PC <---> MT5351 U0
MT5351 U2 <---> MT8205
PC <---> MT8205
PC -----> MT5351 U0RX
DV33A
R254
10k
Q11
2N3904
SOT23/SMD
VI12
VI13
VI14
VI15
3
5
7
9
2Y4
2Y3
2Y2
2Y1
2A4
2A3
2A2
2A1
17
15
13
11
VI16
VI17
VI18
VI19
12
14
16
18
1Y4
1Y3
1Y2
1Y1
1A4
1A3
1A2
1A1
8
6
4
2
R255
10k
VI20
VI21
VI22
VI23
DVI HSYNC
DVIVSYNC
DVIDE
DVIODCK
J18
TXD_0
RXD_0
RXD_2
TXD_2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
8205UP1_3 46
READY0# 47
REQUEST0#48
49
50
74LVC244A
2G 19
1G 1
VCC
GND
U33
REQUEST#
14
13
12
11
10
9
8
U32
20
10
0/NC
DV33A
PCTXD
IDTQS3VH257
TSSOP16/SMD
DV33A
L47
FB
Q10
2N3904
SOT23/SMD
74LVC244A
2G 19
1G 1
20
10
VCC
GND
3
5
7
9
2Y4
2Y3
2Y2
2Y1
2A4
2A3
2A2
2A1
17
15
13
11
12
14
16
18
1Y4
1Y3
1Y2
1Y1
1A4
1A3
1A2
1A1
8
6
4
2
REQUEST0#
1
3
2
CON50
WHEN OGO4 HIGH , DVI OUPUT
WHEN OGO4 LOW ,ATSC OUPUT
R256
2
R252
10k/NC
R247
10k
READY#
3
DV33A
R249
10k/NC
2
R248
10k
R246
10k
ADD 22/9
0/NC
3
5VSB
2
5VSB
OGO4
U31 74LVC244A
VCC
2G 19
GND
1G 1
VI4
VI5
VI6
VI7
DV33A
DV33A
DIP8/W/H/P2.54
74LVC244A
20
10
20
10
DV33A
4
TXD_0:MT5351 Transmit
RXD_0:MT5351 Receiver
TXD_2:MT5351& MT8205 Communication
RXD_2:MT5351& MT8205 Communication
HI = > DTV BOARD POWER OFF
DV33A
J17
1
2
3
4
5
6
7
8
12V
IRF7314
SOIC8/SMD
CB134
0.1uF
220uF/16v
E
LO = > DTV BOARD POWER ON
3,9
3
3
3
3
3
1
1
8
7
6
5
12V
3,9
3
3,7
OGO3
OGO1
OGO2
OGO0
SW
PCRXD
PCTXD
D
U24
5V
2
OGO4
OGO5
OGO6
C
3
4
B
1
Title
Size
Doc Number
Custom
Date:
A
B
C
D
R ev
V1.2
ATSC INTERFACE
Sheet
Wednesday, October 12, 2005
E
13
of
15
A
B
C
4
D
DV33A
E
4
5VSB
CN2
ADIN4
1
2
3
4
5
6
7
1,7,10,13
3,10
3,10
3,11
3
RELAY_ON
5VSB
G ND
VS_ON
5VD
R287 R257
4.7k/NC
1k
RELAY_ON
R354
10K
2N3904
Q12
R259
1k
Q15
2N3904
R355
1
3
TP3
1
2
+12V
ORO1
ORO3
PWM0
ADIN4
2
+12V
ORO1
ORO3
PWM0
ADIN4
DV33A
ORO1
3
DIP7/P2.0
1k
DEL ACD Net--------MTK
R288
10k/NC
3
3
R356 0/NC
Change--------MTK
R340
USE WHEN LG V6
5VSB
PWM0
4.7k
DV33A
R294
R260
4.7k/NC
1k
VS_ON
2
R343
10k
Q13
2N3904
Q16
2N3904
1
R358
1k
3
3
2
1
1k
R262
R357
10K
2
5VD
DV33A
R360
+12V
VCC
+
CE80
220uF/16v
C220UF16V/D6H11
+
2
ORO3
R289
10k/NC
0/NC
USE WHEN LG V6
CE79
220uF/16v
C220UF16V/D6H11
1
1
Title
Size
Doc Number
A
Date:
A
B
C
Wednesday, October 12, 2005
D
Rev
V1.2
PDP interface
Sheet
of
14
E
15
A
4
B
C
D
E
From V0.1 To V1.2 change item:
4
1,Add R109-10K;R107-4.7K;C135-56pF;0603-R88,R91,R104,R106-0欧姆.0805-R96,R99,R101-0欧姆
2,Reset IC 增加5V Supply;DVI AUDIO ADD CONNECTOR J8.
3,ADIN4 CHANGE TO PWM0
3
3
2
2
1
1
Title
Size
Doc Number
A
Date:
A
B
C
Rev
V1.2
History
Wednesday, October 12, 2005
D
Sheet
of
15
E
15
1
2
3
4
5
6
8
7
C1
2
1
TUNER1 IN
22pF
2
AF1_OUT
TV_GND
56
TV
1
C53
1n
1C6
2
10nF
1
MUTEC
C41
BL1
1
J1
1
2
3
4
SIF1
2
1000UF/35V
1
2
3
4
5
EXTL
PGND
600 OHM
220
0R
1
2
3
1
1R12
1C9
82R
NC
+
CE6
10uF/25v
1
2
INTR
9V
TU_VCC
1N4148
R31
C56
100NF
X7R
R32
0R
5%
1
2
C2
4K7
1
R50
2
R53
R51
2
2
2
C45
5%
1n
2
C49
1
R52
22P
47K
1
2
1
1
R57
2
4K7
1
5%
LOUT
1n
2
2
4K7
1
5%
C48
1n
+
ROUT
2
6
R64
7
C43
2
R26
47K
10U/16V
-
47K
C50
22P
1
1
2
1K
2N3904
5%
10K
AGND
D7
4.7V
2
R34
1K
Q5
2N3904
1
5%
R43
4K7
Q4
1015
AGND
1
D5
SIF1_OUT
MUTEB
+
C18
SIF1_OUT
AUDIO GROUND
TU_12V
GND HOLE
GND HOLE
2
3
4
5
9
8
7
6
9
8
7
6
GND HOLE
2
3
4
5
2
3
4
5
1
2
5%
0
ROUT
10k
D9
GNDS
TU_VCC
1
R35
1K
+
5%
C51
1N4148
2
Q6
2N3904
AGND
220UF/25V
GND HOLE
TU_12V
AGND
Q7
1015
SIF1_OUT
TU_VCC
R28
1k
AGND
R30
1
2
3
4
5
2
R44
M4
9
8
7
6
NC
9
8
7
6
NC
GNDS
VIDEO GROUND
2
3
4
5
2
AF1_OUT
NC
GND V
AF1_OUT
0/NC
2
M3
2
3
4
5
1
02
1R16
1
9
8
7
6
1
02
1R15
1
SIF1_IN
9
8
7
6
1
1R14
1
SIF1
2
3
4
5
AGND
LOUT
1N4148
2
M2
2
3
4
5
1
AF1
9
8
7
6
NC
+
M1
9
8
7
6
MUTE
5%
NC
2
AF1
1
47K
AGND
NC
CE7
1
R29
1k
D8
R61
5%
2 AGND
5%
33uF/16V
2
1
5%
RC4558
1
Q3
Q2
2N3904
1
AGND
+
OUT
2
5%
X5R
R42
AGND
U5B
5
B
C37
10K
5%
R41
C42
100UF/25V
+24V
2
10K
R59
4K7
1
C47
100K
1
GND V
R58
2
5%
R60
10K
1
1k8
1
1
AF1_IN
22
1
1
1
AGND
1
1
10UF
X5R
2
2
R56
C59
2
1
AUSPR
2
CB7
0.1uF
2
CE9
220uF/16V
5%
GNDS
D6
R40
1N4148
22U/16V
2
SIF_12V
+
Q1
2N3906
5%
C44
MUTEC
R25
1UF
+24V
5%
1
2
CB6
0.1uF
2
CE8
100uF/16V
5%
47K
R63
1
1
5%
R65
2
2
3K
1
5%
5%
10K
SIF_12V
1
1
1
1
TU_12V
+
47K
2
5%
FB
R13
2 AGND
R62
1
1L6
2
10U/16V
RC4558
C46
1n
GNDS
TU_12V
2
OUT
4K7
1
5%
1
GNDS
4K7
1
5%
2
R49
2
5%
1
1k8
1
2
1
10UF
X5R
R24
2
1 C26
1
R48
C60
2
1
AUSPL
2
CB5
0.1uF
2
2
2
2
C13
100N
+
1
100uF/16V
2
2
2
2
CB4
0.1uF
+
1
CE5
+
100uF/16V
5%
CB3
0.1uF
2
CE3
100uF/16V
2
CE4
+
SDA
3
1
1
1
1
1
1
SCL
100
1
1
1
+24V
5%
22U/16V
2
2
2
5%
U5A
VCC
FB
R68
NC/0R
5%
10K
1
R55
2
1L5
100K
47pF
1
Q8
2N3904
2
5%
2
1
3K3
1
10K
100U/35V
1C3
X7R
1
1
2
PMUTE
C22
47pF
100NF
D10
C61
100n
C63
100U/16V
1
C62
330U/16V
1
1C2
C
C35
G6A-234P
GND V
1
2
FILM
NS
2
GND V
100
2
470NF
MBRS130LTR
2
1
Q9
7805
C58
100n
GND V
TU_VCC
1R6
D3
10K
390PF
+24V
1
2
R54
1
R23
10
C36
6.2V
INTR
INTL
INT: 0
EXT: 1
1
R22
D4
EXTL
J8
CON3
TU_SDA
X5R
C34
NS
10
2
GND V
GND V
TU_SCL
ROUT
2
1000UF/25V
R20
C33
INTL
EXTR
J7
2
2
GND V
GND V
B
1
ROUT
12
2
2
GND V
1R5
2
1UF
1
5%
C39
10uH
2
K1
1
1
1
1R11
L6
C32
1
5
1
1.5uH/1.2uH
1R10
BS
100UF/25V
1
6
LOUT
1L4
820pF/560pF
2
C25
A
4x1 W/HOUSING
2
1
2
1.5uH/1.2uH
1
820pF/560pF
1C8
EN
X7R
X7R
NPO
CON5
1L3
VPP
1UF
100NF
2
C23
1000UF/35V
AGND
C28
8
7
2
R38
5%
J2
EXTR
PGND
C57
+
SW
ATA-120
47K
1
1
1
10nF
1Q3
2N3904
2
+24V
2
L1
2
3.3UH(47uH/22uH)
1
2mH
+
2
1L2
1
R21
AGND
10K
D11 SR240
2
4
1
2
X5R
RC4558
1
1
1NF(22P/27P)
1
1C7
3
22pF
VCC
2
2
1C5
2
2
1
2
5%
1
2
-
4K7 5%
10K
PGND
NIN
5%
C52
1n
1UF
PIN
22
4K7
5%
26
2
1
R19
5%
100K
Audio Input
R39
1
1
1
4K7
5%
1
U3
2
1
2
1K8
5%
R46
21
1
R18
1
2
C40
10UF
R45
21
22
21
R33
2
C31
1
7
OUT
C29
X5R
C30
+
5%
1
NPO
4.7nF
U2B
AUDPR
+
4.7uF
5
SIF_12V
0
1
C27
+
1R9
2
1
+24V
2
5%
100K
100K
5%
10nF
2
2
10K
5%
1C4
1
2
22UF/16V
1
2
3
4
5
6
CON6
SIF1_IN
X7R
1
R17
5%
C19
J5
VIDEO OUT
LMUTE
PMUTE
AGND
AUSPL
AUSPR
4x1 W/HOUSING
2
100NF
NPO
5%
R16
1
1
2
10K
5%
J6
1
C16
R14
R36
R70
5%
0R/NC
1
2
3
4
AUDPL
1C1
470NF
1
22pF
2
+24V
AUDPR
1k
C11
MBRS130LTR
C21
2
CON6
MUTE
1R8
D1
10K
390PF
2
2
2
9V
1N4001
1
1.8K
R9
10
C17
6.2V
NPO
GNDS
1R7
LOUT
2
1000UF/25V
10
R8
D2
2
2
2
X5R
NC
82K
TUNER1 SIF1 BPF
NTSC 4.5MHz　PAL 6MHz
1
R6
1UF
C15
5%
R37
C
2
2
2
1
2
3
4
5
6
1N4001
D12
TU_CVBS
AF1_IN
1
5
BS
21
2
10K
47K
D
C38
10uH
C9
1
5%
22pF
FILM
L5
1
6
VPP
EN
100UF/25V
7
ATA-120
2
MUTEC
C24
J3
TU_12V
0
GNDS
SIF1_IN
AGND
R7
AGND
R15
1
FB1
0
TU_SDA
3
4
CON7
D13
TV_GND
FB2
TU_SCL
10K
X5R
SW
X7R
X7R
2
20
RC4558
NIN
1UF
100NF
2
1R41
R4
5%
100K
4K7
5%
4K7
5%
1UF
-
2
C6
8
1
GNDS
VIDEO OUT
C55
1n
22
1
5%
PGND
CON12
1
GNDS
12
GNDS
VCC
LOUT
4K7
5%
R12
11
2
PIN
1
TV
C54
1n
R67
21
2
1
2
SIF1_OUT
20
1K8
5%
C20
10UF
1
2
3
4
5
6
7
R66
21
1
1
1
1
1
TH3
TH4
1R21
1R3
R47
1
CVBS
VS_IF
AF /MPX
GND3
GND4
SCL
2
18
2
1
1
OUT
U1
2
5%
12
13
14
SDA
1R1
1
TU_CVBS
ROUT
1
2
3
4
5
6
7
8
9
10
11
12
AUDPL
C8
1
R3
5%
GND1
GND2
NC
NC
VS_TUNER
SCL
SDA
AS
NC
NC
AF-R
AF-L
2nd SIF OUT
TU_12V
J11
C3
5%
TH1
TH2
1
2
3
4
5
6
7
8
9
10
11
1J1
+
C4
C7
X5R
+
TU_VCC
+
4.7uF
NPO
4.7nF
3
AV , TUNER I/O
FQ1236-MK3
C5
100K
U2A
TU1
2
5%
100K
R5
100UF/25V
2
2
22UF/16V
D
+24V
R2
1
C10
C12
100NF
5%
10K
5%
+
10K
R10
C14
2
86
5%
C2
: NTSC TV
1
+24V
1
IF
R11
FQ1236 /
NPO
82K
TUNER
1
TUNER1
5%
R1
ADDRESS
GNDS
LMUTE
A
A
R27
1K
AGND
Title
Size
Number
Revision
D
Date:
File:
1
2
3
4
5
6
7
21-Sep-2005
Sheet of
D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By:
8
A
B
C
D
E
MT5351RA-V2
MT5111 / MT5351 REFERENCE DESIGN - 4 LAYERS
Rev
4
RA-V1
RA-V2
History
P#
INITIAL VERSION
J1
DATE
2005/06/15
ADDED AUDIO SWITCH / REFINE POWER CIRCUIT
2005/07/14
BEAD/SMD/1206
L1
FB
+12V
+ CE1
220uF/16v
C220UF16V/D6H11
1
2
3
4
5
6
7
8
L19
FB
L2
FB
BEAD/SMD/1206
CB142
0.1uF
C0603/SMD
+5V
8x1 W/HOUSING
DIP8/W/H/P2.54
+3.3V
GLOBAL SIGNAL
DV33
NS : NON-STUFF
AUD_CTRL
AO1SDATA0
AO1LRCK
AO1BCK
AO1MCLK
R1
4.7K
R0603/SMD
U1
1 S
15 OE
2
5
11
14
IA0
IB0
IC0
ID0
3
6
10
13
IA1
IB1
IC1
ID1
U0TX
U0RX
U2RX
U2TX
AO1MCLK
AO1BCK
AO1LRCK
AO1SDATA0
TYPE
DEVICE
+12V
+5V
POWER +12V
POWER +5V
POWER SUPPLY
POWER SUPPLY
+5V_tuner
DV33_DM
DV18
DV33
AV33
DV25
DV12
POWER +5V
POWER +3V3
POWER +1V8
POWER +3V3
POWER +3V3
POWER +2V5
POWER +1V2
TUNER POWER
MT5111 POWER
MT5111 POWER
MT5351 POWER
MT5351 ANALOG POWER
MT5351 DDR POWER
MT5351 POWER
GND
GROUND
GROUND
VOB0
VOB1
VOB2
VOB3
VOB4
VOB5
VOB6
VOB7
VOG0
VOG1
VOG2
VOG3
VOG4
VOG5
VOG6
VOG7
VOR0
VOR1
VOR2
VOR3
VOR4
VOR5
VOR6
VOR7
VO HSYNC
VOVSYNC
VODE
VOPCLK
6
3
2
1
7
6
IN
VCC
G
G
5
9
33
R0603/SMD
+5V
FB1
FB
BEAD/SMD/0603
1
ORESET#
R EADY#
REQUEST#
K2
9
R4
ASPDIF
K1
8
4
8
2
YA
YB
YC
YD
4
7
9
12
VCC
16
GND
8
P1
S/PDIF OUT
RCA/SPDIF/5P/DIP
5,8
5,8
5,8
5,8
DV33
CB1
0.1uF
C0603/SMD
5
5
5
5
5,8
5,8
5
HA1
7 RN1
5
3
1
33x4
R2
R3
R49
R50
8
6
4
2
RN0603/SMD
75
75
75
75
7 RN3
5
3
1
33x4
7 RN4
5
3
1
33x4
7 RN5
5
3
1
33x4
7 RN6
5
3
1
33x4
7 RN7
5
3
1
33x4
7 RN8
5
3
1
33x4
7 RN9
5
3
1
33x4
7 RN10
5
3
1
33x4
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
8
6
4
2
RN0603/SMD
U0RX
U0TX
U2TX
U2RX
U0RX
U0TX
U2TX
U2RX
3
UART (RS232)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VO HSYNC
VOVSYNC
VODE
VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOHSYNC
VOVSYNC
VODE
DIGITAL VIDEO OUTPUT
5
5
5
5
AO1MCLK
AO1LRCK
AO1BCK
AO1SDATA0
AO1MCLK
AO1LRCK
AO1BCK
AO1SDATA0
ASPDIF
5 ASPDIF
DIGITAL AUDIO INTERFACE
AUD_CTRL
5 AUD_CTRL
2
HEADER 50 SMD0.5 BOTTOM
H50S/P0.5
CB2
0.1uF
C0603/SMD
1
DIGITAL OUTPUT
SPDIF CIRCUIT
Title POWER
Size
A
ASPDIF
5 ASPDIF
NC/IDTQS3VH257
TSSOP16/P0.65/SMD
NAME
ORESET#
REQUEST#
R EADY#
4,5,8 ORESET#
5 REQUEST#
5 READY#
BOTTOM
3
01. INDEX AND INTERFACE
02. POWER
03. TUNER
04. MT5111 ASIC
05. MT5351 ASIC
06. MT5351 PERIPHERAL
07. DDR MEMORY
08. NOR FLASH / JTAG / UART
GND
2,3,4,5,6,7,8 GND
POWER INPUT FROM MAIN BOARD
4
+12V
+5V
DV33
2 +12V
2,6 +5V
2,5,6,8 DV33
+ CE2
220uF/16v
C220UF16V/D6H11
B
C
D
Date:
Rev
Document Number
E
Sheet
of
B
C
FB
+5V
9V
2
CB5
+ CE5
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
VOUT
4
L4
+ CE6
CB6
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
AP1084/TO220-DIP/5V
TO220/DIP
+5V_TUNER
IN
+ CE3
CB3
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
FB
BEAD/SMD/0805
E
BEAD/SMD/0805/NC
OUT
DV33
L3
2
AZ1117/adj
SOT223/SMD
1
OUT
IN
1
4
U3
ADJ
3
L17
U2
3
+12V
D
ADJ/GND
A
FB
R5
BEAD/SMD/0805
110
R0603/SMD
R6
180
R0603/SMD
POWER SUPPLY +5V FOR TUNER
+ CE4
CB4
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
+12V
+5V
DV33
1 +12V
1,6 +5V
1,5,6,8 DV33
1.25 x (1+180/110) = 3.3V
AV33
DV25
DV12
5,6 AV33
5,6,7 DV25
5,6 DV12
POWER SUPPLY +3V3 FOR MT5351
GND
1,3,4,5,6,7,8 GND
U4
3
BEAD/SMD/0805/nc
FB
IN
OUT
DV33_DM
L5
2
FB
R7
BEAD/SMD/0805
110
R0603/SMD
AZ1117/adj
SOT223/SMD
1
+ CE7
CB7
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
ADJ/GND
+5V
L18
R8
180
R0603/SMD
DV33
DV18
L7
2
R11
120
R0603/SMD
U6
3
FB
R9
BEAD/SMD/0805
270
R0603/SMD
AZ1117/adj
SOT223/SMD
+5V
+ CE12
CB12
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
IN
+ CE13
CB13
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
ADJ/GND
OUT
1
IN
ADJ/GND
U5
3
POWER SUPPLY +3V3 FOR MT5351 (ANALOG)
1
DV33_DM
OUT
AZ1117/adj
SOT223/SMD
FB
R10
BEAD/SMD/0805
100
R0603/SMD
R12
100
R0603/SMD
1.25 x (1+120/270) = 1.8V
DV33
U7
3
FB
BEAD/SMD/1206/NC
+ CE30
+ CE31
CB146
CB147
470uF/16v/NC
0.1uF/NC
470uF/16v/NC
0.1uF/NC
C220UF16V/D6H11 C0603/SMD
C220UF16V/D6H11 C0603/SMD
IN
CB15
+ CE15
0.1uF
220uF/16v
C220UF16V/D6H11 C0603/SMD
ADJ/GND
+5V_TUNER
L32
OUT
ADD
L33
GND
IN
EN
2
4
1
CB151
10uF
C0805/SMD
MP2105
SW
FB
4.7UH
FB
3
5
+ CE14
CB14
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
1.25 x (1+100/100) = 2.5V
AZ1117/adj
SOT223/SMD
DV12
L9
2
FB
R13
BEAD/SMD/0805
100
R0603/SMD
R14
0
R0603/SMD
2
U21
3
POWER SUPPLY +2V5 FOR MT5351 AND DDR
1
+5V
DV25
L8
2
POWER SUPPLY +1V8 FOR MT5111
+5V
GLOBAL SIGNAL
+ CE10
CB10
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
1.25 x (1+180/110) = 3.3V
POWER SUPPLY +3V3 FOR MT5111
3
AV33
L6
FB
+ CE9
BEAD/SMD/0805
CB9
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
+ CE8
CB8
220uF/16v
0.1uF
C220UF16V/D6H11 C0603/SMD
4
+5V_TUNER
DV33_DM
DV18
3,4 +5V_TUNER
4 DV33_DM
4 DV18
CB16
+ CE16
0.1uF
220uF/16v
C220UF16V/D6H11 C0603/SMD
2
1.25 x (1+0/100) = 1.25V
POWER SUPPLY +1V2 FOR MT5351
DV25
R112
499k
R0603/SMD
R113
249k
R0603/SMD
CB150
10uF
C0805/SMD
Compatible With U6
1
1
Title
POWER
Rev
1
Size Document Number
MT5351RA-V2
Custom
A
B
C
D
Date:
Monday, September 26, 2005
E
Sheet
2
of
TwinSon Chan
8
A
B
C
D
E
U8
L10
4
GND
GND
Outdoor PS
VS_splitter_+5V
OOB_OP
NC
RF_AGC
NC
AS
SCL
SDA
NC
VS_Tuner_+5V
Broad_IF_OP
IF_AGC
Narrow_IF_OP1
Narrow_IF_OP2
GND
GND
TH1
TH2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TH3
TH4
CB17
0.1uF
C0603/SMD
R17
R18
R19
NS
100
100
+5V_TUNER
FB
+ CE17
BEAD/SMD/0805
10uF/16v
C10UF16V/D5H11
+5V_TUNER
4
R15
10K
R0603/SMD
R0603/SMD
R0603/SMD
R0603/SMD
R16
10K
R0603/SMD
TUNER_SCLO
TUNER_SDAO
L11
+5V_TUNER
FB
CB18
+ CE18
BEAD/SMD/0805
0.1uF
10uF/16v
C0603/SMD C10UF16V/D5H11
R20
4.7K
R0603/SMD
C3
10nF
C0603/SMD
PORT TUNER TD1336/FGHP
3
IF_AGC
3
+5V_TUNER
2,4 +5V_TUNER
+5V_TUNER
C4
1nF
C0603/SMD
R22
510/1%
R0603/SMD
GLOBAL SIGNAL
C5
0.1uF
C0603/SMD
2nd_IF-
R21
510/1%
R0603/SMD
1
2
3
U9
IN+
IN-
OUT+
OUT-
5
4
GND
PORT SAW FILTER X6965D SIP5K
SIP5K/DIP
2
C6
1uF
C0603/SMD
L12
NS
L/IND/SMD/0805
C7
1uF
C0603/SMD
IF SAW FILTER AND AMPLIFIER
ROUTE SYMMETRICALLY
1
2
3
4
G ND
1,2,4,5,6,7,8 GND
U10
VCC_+5V GND
IN_1
OUT_1
IN_2
OUT_2
VAGC
GND
RF_AGC
IF_AGC
4 RF_AGC
4 IF_AGC
2nd_IF+
2nd_IF-
4 2nd_IF+
4 2nd_IF-
8
7
6
5
2nd_IF+
TUNER_SCLO
TUNER_SDAO
4 TUNER_SCLO
4 TUNER_SDAO
upc3218
TSSOP8/SMD
C8
10nF
C0603/SMD
2
TUNER INTERFACE
RF_AGC
R23
4.7K
R0603/SMD
1
1
Title
TUNER
R ev
1
Size Document Number
MT5351RA-V2
Custom
A
B
C
D
Date:
Monday, September 26, 2005
E
Sheet
3
of
TwinSon Chan
8
A
B
C
D
E
+5V_TUNER
DV33_DM
DV18
2,3 +5V_TUNER
2 DV33_DM
2 DV18
GND
1,2,3,5,6,7,8 GND
1,5,8 ORESET#
C13
1uF
C0603/SMD
C14
C15
C17
REFTOP
FB2
FB
BEAD/SMD/0603
3
Y1
25MHz
CRYS/DIP/SMD
REFBOT
VCMEXT
C16
10uF/10v
C0805/SMD
0.1uF
C0603/SMD
DVDD18
AVDD33
AVDD33
0.1uF
C0603/SMD
0.1uF
C0603/SMD
C18
0.1uF
C0603/SMD
C19
18pF
C0603/SMD
C20
18pF
C0603/SMD
AVDD33
AVDD3
AVDD33
XTAL2
XTAL1
AVDD33
DVDD33
DVDD18
DVDD33
DVDD18
DVDD18
DGND
RF_AGC
IF_AGC
DGND
DVDD33
TUNER_CLK
TUNER_DATA
SA1
SA0
DGND
DVDD18
DGND
ANTIF
DGND
DVDD33
NC
NC
NC
DGND
DVDD18
NC
NC
DVDD33
DGND
ADVDD33
NC
NC
AVSS
AVDD
ININ+
AVDD
NC
AVSS
REFBOT
VCMEXT
REFTOP
AVSS
AVDD18
AVDD
AVDD
AVDD
AVSS
AVSS
XTAL2
XTAL1
AVSS
AVDD
AVSS
NC
NC
RESET_
HOST_CLK
DGND
DVDD18
HOST_DATA
DGND33
DVDD33
DGND
DVDD18
TS_ERR
TS_VAL
TS_CLK
DGND
DVDD33
TS_SYNC
TS_DATA0
TS_DATA1
DGND
DVDD18
TS_DATA2
TS_DATA3
DGND
DVDD33
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
5
5
5
5
5
ORESET#
OSCL_MST
TS INPUT
DV DD18
DV DD33
DV DD18
DV DD33
1 RN11
2
3
4
5
6
7
8
33x4
RN0603/SMD
TS1ERROR
TS1VALID
TS1CLK
TS1SYNC
1 RN12
2
3
4
5
6
7
8
33x4
RN0603/SMD
TS1DATA0
TS1DATA1
TS1DATA2
TS1DATA3
3
MODIFIED IN V3
DV33_DM
D
3
CLK
1
1
3
5
7
VCC
Q
Q
14
5
6
GND
7
TS1CLK#
12
D
11
CLK
TS1DATA7_T
TS1DATA6
TS1DATA5
TS1DATA4
74HC74
SOP14/SMD
U12B
VCC
Q
Q
14
9
8
GND
7
13
4
2
TS1CLK
PR
TS1SYNC
CB148
0.1uF
C0603/SMD
U12A
CL
RN13
33x4
RN0603/SMD
OSDA_MST
OSCL_MST
6 OSDA_MST
6 OSCL_MST
DV DD33
2
4
6
8
DVDD33
DVDD18
ADVDD33_2
AVDD33
AVDD33
TS1DATA[0..7]
TS1SYNC
TS1VALID
TS1ERROR
TS1CLK
TS1DATA[0..7]
TS1SYNC
TS1VALID
TS1ERROR
TS1CLK
DV DD18
OSDA_MST
1
2
3
4
5
6
7
8
9
10
11
AVDD5
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R28
1M
R0603/SMD
U11
MT5111AE
10
L13
C12
NS/220nH
NS/47pF
L/IND/SMD/0805 C0603/SMD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TUNER INTERFACE
PR
2nd_IF+
ADVDD33_1
C11
1uF
C0603/SMD
TUNER_SCLO
TUNER_SDAO
3 TUNER_SCLO
3 TUNER_SDAO
NC
NC
AVDD
NC
NC
NC
AVSS
NC
NC
AVDD
AVSS
AVDD
NC
NC
ADVDD33
DGND
DVDD33
DVDD18
DGND
NC
NC
TS_DATA7
TS_DATA6
TS_DATA5
TS_DATA4
2nd_IF-
4
2nd_IF+
2nd_IF-
3 2nd_IF+
3 2nd_IF-
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Close to MT5111
R F_AGC
IF_AGC
3 RF_AGC
3 IF_AGC
CL
IF_AGC
C10
47nF
C0603/SMD
100-LQFP
R26
1K
R0603/SMD
GLOBAL SIGNAL
MT5111AE
MT5111_IF_AGC
R F_AGC
C9
47nF
C0603/SMD
DVDD33
TUNER_SCL
TUNER_SDA
R27 4.7K R0603/SMD
R25 4.7K R0603/SMD/NC
R24
1K
R0603/SMD
DVDD18
MT5111_RF_AGC
MT5111_RF_AGC
MT5111_IF_AGC
DVDD33
4
ORESET#
TS1DATA7_T
74HC74
SOP14/SMD
TS1DATA7
R111
NS/0
R0603/SMD
DV33_DM
7
+ CE19
10uF/16v
C10UF16V/D5H11
CB22
0.1uF
C0603/SMD
DVDD18
CB19
0.1uF
C0603/SMD
AVDD33
CB23
0.1uF
C0603/SMD
CB24
0.1uF
C0603/SMD
CB25
0.1uF
C0603/SMD
CB20
0.1uF
C0603/SMD
CB21
0.1uF
C0603/SMD
Digital 1.8V Bypass Caps
AVDD33
DV33_DM
L15
FB
BEAD/SMD/0805
DVDD33
+ CE20
10uF/16v
C10UF16V/D5H11
CB28
0.1uF
C0603/SMD
DVDD33
CB29
0.1uF
C0603/SMD
CB30
0.1uF
C0603/SMD
CB31
0.1uF
C0603/SMD
CB32
0.1uF
C0603/SMD
CB33
0.1uF
C0603/SMD
Digital 3.3V Bypass Caps
L16
FB
BEAD/SMD/0805
AVDD33
+ CE21
10uF/16v
C10UF16V/D5H11
CB40
0.1uF
C0603/SMD
AVDD33
CB35
0.1uF
C0603/SMD
CB83
0.1uF
C0603/SMD
FB4
FB
BEAD/SMD/0603
AVDD33
FB5
FB
BEAD/SMD/0603
1
DV33_DM
FB3
FB
BEAD/SMD/0603
CB36
0.1uF
C0603/SMD
CB37
0.1uF
C0603/SMD
CB38
0.1uF
C0603/SMD
Analog 3.3V Bypass Caps
CB39
0.1uF
C0603/SMD
AVDD33
FB6
FB
BEAD/SMD/0603
AVDD3
R29
10K
R0603/SMD
AVDD5
R31
4.7K
R0603/SMD
CB34
0.1uF
C0603/SMD
74HC00
SOP14/SMD
9
TS1ERROR
8
74HC00
SOP14/SMD
B
12
U20D
11
13
2
TS1DATA7
74HC00
SOP14/SMD
R32
4.7K
R0603/SMD
TUNER_SCL
2N7002
N-MOSFET
1
ADVDD33_2
TUNER_SDA1
CB41
0.1uF
C0603/SMD
TUNER_SCL1
R33
10
R0603/SMD
R34
10
R0603/SMD
TUNER_SDAO
TUNER_SCLO
Title
MT5111 ASIC
Size
C
A
14
U20C
10
2N7002
N-MOSFET
3 QF2 1
SIF LEVEL SHIFTER
6
TUNER_SDA
3 QF1 1
TUNER_SCL1
ADVDD33_1
U20B
5
DV33_DM
R30
10K
R0603/SMD
TUNER_SDA1
CB27
0.1uF
C0603/SMD
4
14
14
+5V_TUNER
CB26
0.1uF
C0603/SMD
TS1CLK#
TS1DATA7_T
74HC00
SOP14/SMD
2
DVDD18
L14
FB
BEAD/SMD/0805
3
2
DV18
U20A
2
7
TS1CLK
7
1
2
7
14
CB149
0.1uF
C0603/SMD
C
D
Date:
Document Number
MT5351RA-V2
TwinSon Chan
Monday, September 26, 2005
E
Sheet
4
of
Rev
1
8
5
4
3
2
1
U0TX
U0RX
U1TX
U1RX
U2TX
U2RX
U2CTS
TUNER_SW
F3
F2
F1
G4
G3
G2
G1
H4
U0TX
U0RX
U1TX
U1RX
U2TX
U2RX
U2CTS
U2RTS
ASPDIF
AUD_CTRL
H3
H2
H1
J4
J3
J2
J1
K1
K2
K3
K4
L3
L4
AO1SDATA3
AO1SDATA2
AO1SDATA1
AO1SDATA0
AO1LRCK
AO1BCK
AO1MCLK
AO2SDATA0
AO2LRCK
AO2BCK
AO2MCLK
ASPDIF
ASPDIF2
VOB0
VOB1
VOB2
VOB3
VOB4
VOB5
VOB6
VOB7
VOG0
VOG1
VOG2
VOG3
VOG4
VOG5
VOG6
VOG7
VOR0
VOR1
VOR2
VOR3
VOR4
VOR5
VOR6
VOR7
VOPCLK
VOH SYNC
V OVSYNC
VODE
L2
L1
M4
M3
M2
M1
N4
N3
N2
N1
P4
P3
P2
P1
T1
T2
T3
T4
U1
U2
U3
U4
V1
V2
V3
V4
W1
W2
VOB0
VOB1
VOB2
VOB3
VOB4
VOB5
VOB6
VOB7
VOG0
VOG1
VOG2
VOG3
VOG4
VOG5
VOG6
VOG7
VOR0
VOR1
VOR2
VOR3
VOR4
VOR5
VOR6
VOR7
VOPCLK
VOHSYNC
VOVSYNC
VODE
W3
W4
Y1
Y2
Y3
Y4
OPWM1
OPWM0
B14
A14
A15
B15
C15
D15
A16
B16
C16
D16
A17
B17
C17
D17
A18
B18
C18
D18
A19
B19
C19
D19
A20
B20
C20
D20
A21
B21
C21
D21
A22
B22
C22
D22
A23
B23
C23
D23
A24
B24
C24
D24
A25
B25
C25
A26
B26
A27
A28
D9
C9
B9
A9
D10
C10
B10
A10
D11
C11
B11
A11
D12
C12
B12
A12
D13
C13
B13
A13
D14
C14
T1DATA7
T1DATA6
T1DATA5
T1DATA4
T1DATA3
T1DATA2
T1DATA1
T1DATA0
T1VALID
T1SYNC
T1CLK
T0DATA7
T0DATA6
T0DATA5
T0DATA4
T0DATA3
T0DATA2
T0DATA1
T0DATA0
T0VALID
T0SYNC
T0CLK
D7
A8
B8
C7
C8
D8
M5
N5
U5
E10
E19
M24
N24
U24
AE14
AE15
PDA22
PDA21
PDA20
PDA19
PDA18
PDA17
PDA16
PDA15
PDA14
PDA13
PDA12
PDA11
PDA10
PDA9
PDA8
PDA7
PDA6
PDA5
PDA4
PDA3
PDA2
PDA1
PDA0
PD D7
PD D6
PD D5
PD D4
PD D3
PD D2
PD D1
PD D0
TS1DATA7
TS1DATA6
TS1DATA5
TS1DATA4
TS1DATA3
TS1DATA2
TS1DATA1
TS1DATA0
TS1VALID
T S1SYNC
TS1CLK
TS1ERROR
OPWM0
FS
C3
B3
A3
C4
B4
A4
C5
B5
B6
A5
A6
B7
A7
C6
D6
A2
B2
OXTALO
OXTALI
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
B27
B28
C26
C27
C28
D25
D26
PARB#
PARE#
PACE#
PACLE
PAALE
PAWE#
D27
D28
E25
E26
E27
E28
ELREQ
ECLK
ECNTL0
ECNTL1
EDATA0
EDATA1
EDATA2
EDATA3
EDATA4
EDATA5
EDATA6
EDATA7
ELPS
ELINKON
F25
F26
F27
F28
G25
G26
G27
G28
H25
H26
H27
H28
J25
J26
ORESET#
OIRI
OIRO
J27
J28
K25
ICS1#
ICS0#
IDA2
IDA0
IDA1
IINTRQ
IDMACK#
IIORDY
IDIOR#
IDIOW#
IDMARQ
IDD15
IDD0
IDD14
IDD1
IDD13
IDD2
IDD12
IDD3
IDD11
IDD4
IDD10
IDD5
IDD9
IDD6
IDD8
IDD7
IRESET#
K26
K27
K28
L25
L26
L27
L28
M25
M26
M27
M28
N25
N26
N27
N28
P25
P26
P27
P28
T28
T27
T26
T25
U28
U27
U26
U25
V28
DDETECT
DCLK
DCMD
DDATA0
DDATA1
DDATA2
DDATA3
V27
V26
V25
W28
W27
W26
W25
MDETECT
MCLK
MBS
MDATA0
MDATA1
MDATA2
MDATA3
Y28
Y27
Y26
Y25
AA28
AA27
AA26
STSCLK
STSDOUT
STSDIN
SPWRSEL
SDETECT
SCMDVCC
SRST
SCLK
SDATA
AA25
AB28
AB27
AB26
AB25
AC28
AC27
AC26
AC25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE8
AE9
AE20
AE21
A
E4
D4
E5
D5
D1
D2
C2
B1
A1
D3
C1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVREF2
DVREF0
DVREF1
DVREF3
L14
L15
L16
L17
L18
M14
M15
M16
M17
M18
N14
N15
N16
N17
N18
P11
P12
P13
P14
P15
P16
P17
P18
R11
R12
R13
R14
R15
R16
R17
R18
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
OPWM0
6 OPWM0
POWE#
POCE0#
POOE0#
POCE1#
POOE1#
POCE2#
POOE2#
OXTALI
OXTALO
6 OXTALI
6 OXTALO
POWE#
POCE0#
POOE0#
D
OSDA0
OSCL0
6 OSDA0
6 OSCL0
VCXO0
6 VCXO0
GLOBAL SIGNAL
VCXO0
VCXO1
TP4
VCXO1
TP/SMD/D1.0
TEST PURPOSE
4
4
4
4
4
TS1DATA[0..7]
TS1SYNC
TS1VALID
TS1ERROR
TS1CLK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]
RBA[0..1]
RCLK0
RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE
RCLK1
RCLK1#
RVREF
TS1DATA[0..7]
TS1SYNC
TS1VALID
TS1ERROR
TS1CLK
TS INPUT
DV33
R35
4.7K
R0603/SMD
ORESET#
OI RI
TP5
IR
TP/SMD/D1.0
RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]
RBA[0..1]
RCLK0
RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE
RCLK1
RCLK1#
RVREF
DDR MEMORY
+ CE22
47uF/16v
C10UF16V/D5H11
C
POCE0#
POOE0#
POWE#
8 POCE0#
8 POOE0#
8 POWE#
PDA[0..22]
PD D[0..7]
8 PDA[0..22]
8 PDD[0..7]
FLASH INTERFACE
AO1MCLK
AO1LRCK
AO1BCK
AO1SDATA0
1 AO1MCLK
1 AO1LRCK
1 AO1BCK
1 AO1SDATA0
ASPDIF
1 ASPDIF
AUDIO INTERFACE
8
8
8
8
8
8
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
JTAG PORT
1,8
1,8
8
8
1,8
1,8
U0RX
U0TX
U1RX
U1TX
U2TX
U2RX
U0RX
U0TX
U1RX
U1TX
U2TX
U2RX
6 OIRI
6 U2CTS
OI RI
U2CTS
UART (RS232)
DONE
REQUEST#
REA DY#
FS
6 FS
DVDDKP
6 DVDDKP
R36
330
R0603/SMD
T11
T12
T13
T14
T15
T16
T17
T18
U11
U12
U13
U14
U15
U16
U17
U18
V11
V12
V13
V14
V15
V16
V17
V18
LED1
LED DIP2.54
LED/DIP/P2.54
AVDDBGKP
A VDDYKP
AVDDRKP
2,6 AVDDBGKP
2,6 AVDDYKP
2,6 AVDDRKP
2,6
2,6
2,6
2,6
2,6
6
6
6
6
AVDD_DMPLL0
AVDD_DMPLL1
AVDD_VPLL
AVDD_APLL1
AVDD_APLL0
CAPVPLL
CAPVGND
APLLCAP1
APLLCAP0
AVDD_DMPLL0
AVDD_DMPLL1
AVDD_VPLL
AVDD_APLL1
AVDD_APLL0
CAPVPLL
CAPVGND
APLLCAP1
APLLCAP0
1
1
1
1
1,8
1,8
1
VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOHSYNC
VO VSYNC
VODE
VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOH SYNC
V OVSYNC
VODE
B
DIGITAL VIDEO OUTPUT
1 AUD_CTRL
AUD_CTRL
ATP1
ATP2
6 ATP1
6 ATP2
ANALOG PART
DV12
C116
0.1uF
C0603/SMD
C117
0.1uF
C0603/SMD
C118
0.1uF
C0603/SMD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
ORESET#
REQUEST#
REA DY#
1,4,8 ORESET#
1 REQUEST#
1 READY#
MT5351
BGA471/SMD
A
Add by Ada
RVR EF
DV25
R CLK0
RCLK0#
RD Q0
RD Q1
RD Q2
RD Q3
RD Q4
RD Q5
RD Q6
RD Q7
RDQS0
RDQM0
RDQM1
RDQS1
RD Q8
RD Q9
R DQ10
R DQ11
R DQ12
R DQ13
R DQ14
R DQ15
RW E#
R CAS#
R RAS#
RC S#
RBA0
RBA1
RA10
R A0
R A1
R A2
R A3
R A4
R A5
R A6
R A7
R A8
R A9
RA11
RA12
RA13
RC KE
R DQ16
R DQ17
R DQ18
R DQ19
R DQ20
R DQ21
R DQ22
R DQ23
RDQS2
RDQM2
RDQM3
RDQS3
R DQ24
R DQ25
R DQ26
R DQ27
R DQ28
R DQ29
R DQ30
R DQ31
R CLK1
RCLK1#
B
MT5351
G ND
1,2,3,4,6,7,8 G ND
DV12
AA4
AB4
AC4
AD4
AE4
AE5
AE6
AE7
AE10
AE11
AE12
AE13
AE16
AE17
AE18
AE19
AE22
AE23
AE24
AE25
AD25
AO1SDATA0
AO1LRCK
AO1BCK
AO1MCLK
PDENPOD
PDCD2#
PDIOIS16#
PDREG#
PDINPACK#
PDWAIT#
PDRESET
PDIREQ#
PDWE#
PDIOWR#
PDIORD#
PDOE#
PDCE2#
PDCE1#
PDA25
PDA24
PDA23
PDA22
PDA21
PDA20
PDA19
PDA18
PDA17
PDA16
PDA15
PDA14
PDA13
PDA12
PDA11
PDA10
PDA9
PDA8
PDA7
PDA6
PDA5
PDA4
PDA3
PDA2
PDA1
PDA0
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDCD1#
OSDA0
OSCL0
OSDA1
OSCL1
ORTCVDD
ORTCI
ORTCO
ORTCVSS
E1
F4
E3
E2
AVDDRKP
IOR_Y6
IOB_Y5
IOG_Y4
IOX_Y3
IOY_Y2
IOC_Y1
AVDDYKP
AVDDBGKP
NC
FS
DACVREF
CIN_Y0
DVDDKP
NC
OSDA0
OSCL0
RDQ32
RDQ33
RDQ34
RDQ35
RDQ36
RDQ37
RDQ38
RDQ39
RDQS4
RDQM4
RDQM5
RDQS5
RDQ40
RDQ41
RDQ42
RDQ43
RDQ44
RDQ45
RDQ46
RDQ47
RCLK0
RCLK0#
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS0
RDQM0
RDQM1
RDQS1
RDQ8
RDQ9
RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15
RWE#
RCAS#
RRAS#
RCS#
RBA0
RBA1
RA10
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA11
RA12
RA13
RCKE
RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23
RDQS2
RDQM2
RDQM3
RDQS3
RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31
RCLK1
RCLK1#
RDQ48
RDQ49
RDQ50
RDQ51
RDQ52
RDQ53
RDQ54
RDQ55
RDQS6
RDQM6
RDQM7
RDQS7
RDQ56
RDQ57
RDQ58
RDQ59
RDQ60
RDQ61
RDQ62
RDQ63
TP6
TUNER_SW
TP/SMD/D1.0
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
AA1
AA2
AA3
AB1
AB2
AB3
AC1
AC2
AC3
AD1
AD2
AD3
AE1
AE2
AE3
AF1
AF2
AF3
AG1
AG2
AH1
AH2
AH3
AG3
AH4
AG4
AF4
AH5
AG5
AF5
AH6
AG6
AF6
AH7
AG7
AF7
AH8
AG8
AF8
AH9
AG9
AF9
AH10
AG10
AF10
AH11
AG11
AF11
AH12
AG12
AF12
AH13
AG13
AF13
AH14
AG14
AF14
AH15
AG15
AF15
AH16
AG16
AF16
AH17
AG17
AF17
AH18
AG18
AF18
AH19
AG19
AF19
AH20
AG20
AF20
AH21
AG21
AF21
AH22
AG22
AF22
AH23
AG23
AF23
AH24
AG24
AF24
AH25
AG25
AF25
AH26
AG26
AH27
AH28
AG28
AG27
AF28
AF27
AF26
AE28
AE27
AE26
AD28
AD27
AD26
C
P5
R1
R2
R3
R4
R5
T5
E11
E12
E13
E14
E15
E16
E17
E18
P24
R24
R25
R26
R27
R28
T24
APLLCAP0
APLLCAP1
CAPVGND
CAPVPLL
ATP2
ATP1
AVDD_APLL0
AVDD_APLL1
AVDD_VPLL
AVDD_DMPLL1
AVDD_DMPLL0
L11
L12
L13
M11
M12
M13
N11
N12
N13
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DV33
DV33
DV25
DV12
1,2,6,8 DV33
2,6,7 DV25
2,6 DV12
D
U14
R
B
G
8 R
8 B
8 G
DV DDKP
AV DDYKP
AVDDBGKP
AVDDRKP
R
B
G
OXTALO
OXTALI
APLLCAP0
APLLCAP1
CAPVGND
CAPVPLL
ATP2
ATP1
AVDD_APLL0
AVDD_APLL1
AVDD_VPLL
AVDD_DMPLL1
AVDD_DMPLL0
TP1
IOR _Y6
TP/SMD/D1.0
TP2
IOB_Y5
TP/SMD/D1.0
TP3
IOG_Y4
TP/SMD/D1.0
Title
MT5351 ASIC
Size Document Number
MT5351RA-V2
Custom
5
4
3
2
D ate:
Monday, September 26, 2005
1
TwinSon Chan
Sheet
5
of
R ev
1
8
5
4
3
2
1
FS
R37
NS/560
R0603/SMD
R38
NS/10M
R0603/SMD
Y2
OXTALI
D
CAPVPLL
C23
TP7
CAPVGND
TP/SMD/D1.0
5600pF
C0603/SMD
APLLCAP1
C24
1500pF
C0603/SMD
CAPVGND
AV33
APLLCAP0
C25
1500pF
C0603/SMD
NS/27MHz
CRYS/DIP/SMD
AV33
R40
NS/50
R0603/SMD
ATP1
C21
NS/20pF
C0603/SMD
R41
NS/50
R0603/SMD
DV33
4
CB42
0.1uF
1
C0603/SMD
OXTALO
VCC
OUT
3
NC
GND
2
R39
NS/10
R0603/SMD
U2CTS
1,2,5,8
2,5
2,5,7
2,5
DV33
AV33
DV25
DV12
DV33
AV33
DV25
DV12
GND
1,2,3,4,5,7,8 GND
ATP2
OSDA0
OSCL0
5 OSDA0
5 OSCL0
OPWM0
DV33
C29
10uF/10v
C0805/SMD
CB44
4.7uF
C0603/SMD
CB45
0.1uF
C0603/SMD
CB46
0.1uF
C0603/SMD
LEFT SIDE
CB47
4.7uF
C0603/SMD
CB48
0.1uF
C0603/SMD
CB49
0.1uF
C0603/SMD
RIGHT SIDE
CB50
4.7uF
C0603/SMD
CB51
0.1uF
C0603/SMD
CB52
0.1uF
C0603/SMD
CB53
0.1uF
C0603/SMD
R42
8.2K
R0603/SMD
1
C26
10nF
C0603/SMD
C27
1nF
C0603/SMD
C28
47pF
C0603/SMD
DV33
X1
CVIN
2
TRI-STATE
3
GND
6
VDD
NC
5
OUT
4
VCXO FR270003
OSC/6P/SMD/7X5
CB54
0.1uF
C0603/SMD
GLOBAL SIGNAL
OXTALI
R43
10
R0603/SMD
TOP SIDE
C138
4.7uF
C0603/SMD
C140
0.1uF
C0603/SMD
CB57
4.7uF
C0603/SMD
C183
0.1uF
C0603/SMD
LEFT SIDE
C184
0.1uF
C0603/SMD
C185
0.1uF
C0603/SMD
C186
0.1uF
C0603/SMD
C104
0.1uF
C0603/SMD
C179
0.1uF
C0603/SMD
BOTTOM SIDE
R45
4.7K
R0603/SMD
2,5
2,5
2,5
2,5
2,5
5
5
5
5
IR1
NS/IR
IR
R46
4.7K
R0603/SMD
DV12
O IRI
C31
10uF/10v
C0805/SMD
CB65
0.1uF
C0603/SMD
CB66
0.1uF
C0603/SMD
CB67
0.1uF
C0603/SMD
LEFT SIDE
DV12
FB7
CB68
0.1uF
C0603/SMD
CB70
0.1uF
C0603/SMD
RIGHT SIDE
DVDDKP
FB
BEAD/SMD/0603
CB69
0.1uF
C0603/SMD
CB71
0.1uF
C0603/SMD
CB72
0.1uF
C0603/SMD
CB73
0.1uF
C0603/SMD
TOP SIDE
B
L31
CB80
0.1uF
C0603/SMD
C129
0.1uF
C0603/SMD
C128
0.1uF
C0603/SMD
OSDA_MST
R47
100
R0603/SMD
OSCL0
OSCL_MST
R48
100
R0603/SMD
1
2
3
4
U13
NC
NC
NC
GND
VCC
WP
SCL
SDA
8
7
6
5
C
ANALOG PART
CB77
0.1uF
C0603/SMD
MEM_VREF
RV REF
7 MEM_VREF
5 RVREF
OPWM0
5 OPWM0
OXTALI
OXTALO
5 OXTALI
5 OXTALO
VCXO0
U2CTS
O IRI
5 OIRI
CB81
0.1uF
C0603/SMD
AVDD_DMPLL0
AVDD_DMPLL1
AVDD_VPLL
AVDD_APLL1
AVDD_APLL0
CAPVPLL
CAPVGND
APLLCAP1
APLLCAP0
ATP1
ATP2
5 ATP1
5 ATP2
+5V
2
2x1
JP2/DIP/P2.54
AVDD_DMPLL0
AVDD_DMPLL1
AVDD_VPLL
AVDD_APLL1
AVDD_APLL0
CAPVPLL
CAPVGND
APLLCAP1
APLLCAP0
5 U2CTS
CB82
0.1uF
C0603/SMD
RV REF
FB
L0603/SMD
OSDA0
AVDDBGKP
AV DDYKP
AVDDRKP
5 VCXO0
AV DDYKP
MEM_VREF
CB76
0.1uF
C0603/SMD
JP1
DV33
AVDDBGKP
CB79
0.1uF
C0603/SMD
CB75
0.1uF
C0603/SMD
BOTTOM SIDE
AV33
CB78
4.7uF
C0603/SMD
CB74
0.1uF
C0603/SMD
1
D VDDKP
2,5 AVDDBGKP
2,5 AVDDYKP
2,5 AVDDRKP
DV33
1
2
3
C101
10uF/10v
C0805/SMD
FS
5 FS
5 DVDDKP
VCXO0
R44
NS/10
R0603/SMD
DV25
C
OSDA_MST
OSCL_MST
4 OSDA_MST
4 OSCL_MST
CB43
0.1uF
C0603/SMD
D
+5V
1,2 +5V
OSC1
NS/74.25MHz
OSC/SMD/A
C22
NS/20pF
C0603/SMD
OSCL_MST
OSDA_MST
EEPROM 24C16
SOP8/SMD/NC
B
AVDDRKP
CB85
0.1uF
C0603/SMD
MT5351 SYSTEM EEPROM
AVDD_DMPLL0
CB86
0.1uF
C0603/SMD
AVDD_DMPLL1
CB87
0.1uF
C0603/SMD
AVDD_VPLL
CB88
0.1uF
C0603/SMD
AVDD_APLL1
CB89
0.1uF
C0603/SMD
A
A
AVDD_APLL0
CB90
0.1uF
C0603/SMD
Title
MT5351 PERIPHERAL
Size Document Number
MT5351RA-V2
Custom
5
4
3
2
Date:
TwinSon Chan
Monday, September 26, 2005
1
Sheet
6
of
Rev
1
8
5
4
3
+1V25_DDR
D
RW E#
RCAS#
R CS#
RBA0
RA10
RA0
RA2
RA3
RA5
RA6
RA8
RA9
7 RN14
5
3
1
7 RN18
5
3
1
7 RN22
5
3
1
8 22x4 MEM_WE#
MEM_CAS#
6
MEM_CS#
4
MEM_BA0
2
8 22x4 MEM_ADDR10
MEM_ADDR0
6
MEM_ADDR2
4
MEM_ADDR3
2
8 22x4 MEM_ADDR5
MEM_ADDR6
6
MEM_ADDR8
4
MEM_ADDR9
2
RA12
R63
22
MEM_ADDR12
MEM_ADDR12 R64
75
RA13
R65
22
MEM_ADDR13
MEM_CAS#
75
7 RN15
5
3
1
7 RN19
5
3
1
7 RN23
5
3
1
R66
1 RN30
3
5
7
RA7
R67
22
RA11
R71
22
MEM_ADDR11
R77
22
MEM_CLKEN
MEM_CLKEN
NS/75
MEM_ADDR7
MEM_BA1
MEM_BA0
MEM_CS#
MEM_RAS#
1 RN31
3
5
7
MEM_ADDR3
R68
75
MEM_ADDR11 R72
75
CLOSED TO MT5351
R78
2 75x4
4
6
8
CLOSED TO DDR
RCLK0
R102
47
R0603/SMD
RCLK0#
R105
47
R0603/SMD
RCLK1
R106
47
R0603/SMD
1
+1V25_DDR
8 75x4
6
4
2
8 75x4
6
4
2
8 75x4
6
4
2
RRAS#
RBA1
RA1
RA4
R CKE
2 22x4 MEM_RAS#
MEM_BA1
4
MEM_ADDR1
6
MEM_ADDR4
8
MEM_ADDR5
MEM_ADDR4
MEM_ADDR13
MEM_WE#
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
2
RD Q0
RD Q1
RD Q2
RD Q3
RD Q4
RD Q5
RD Q6
RD Q7
RDQS0
RDQM0
RDQM1
RDQS1
RD Q8
RD Q9
RDQ10
RDQ11
RDQ12
RDQ13
RDQ14
RDQ15
7 RN16
5
3
1
7 RN20
5
3
1
R55
R57
R59
R61
7 RN24
5
3
1
7 RN26
5
3
1
8 47x4 MEM_DQ0
MEM_DQ1
6
MEM_DQ2
4
MEM_DQ3
2
8 47x4 MEM_DQ4
MEM_DQ5
6
MEM_DQ6
4
MEM_DQ7
2
MEM_DQS0
47
MEM_DQM0
47
MEM_DQM1
47
MEM_DQS1
47
8 47x4 MEM_DQ8
MEM_DQ9
6
MEM_DQ10
4
MEM_DQ11
2
8 47x4 MEM_DQ12
MEM_DQ13
6
MEM_DQ14
4
MEM_DQ15
2
7 RN17
5
3
1
7 RN21
5
3
1
R56
R58
R60
R62
7 RN25
5
3
1
7 RN27
5
3
1
8 75x4
6
4
2
8 75x4
6
4
2
75
75
75
75
8 75x4
6
4
2
8 75x4
6
4
2
RDQ16
RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23
RDQS2
RDQM2
RDQM3
RDQS3
RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31
7 RN28
5
3
1
7 RN32
5
3
1
R69
R73
R75
R79
7 RN34
5
3
1
7 RN36
5
3
1
8 47x4 MEM_DQ16
MEM_DQ17
6
MEM_DQ18
4
MEM_DQ19
2
8 47x4 MEM_DQ20
MEM_DQ21
6
MEM_DQ22
4
MEM_DQ23
2
MEM_DQS2
47
MEM_DQM2
47
MEM_DQM3
47
MEM_DQS3
47
8 47x4 MEM_DQ24
MEM_DQ25
6
MEM_DQ26
4
MEM_DQ27
2
8 47x4 MEM_DQ28
MEM_DQ29
6
MEM_DQ30
4
MEM_DQ31
2
7 RN29
5
3
1
7 RN33
5
3
1
R70
R74
R76
R80
7 RN35
5
3
1
7 RN37
5
3
1
8 75x4
6
4
2
8 75x4
6
4
2
75
75
75
75
8 75x4
6
4
2
8 75x4
6
4
2
DV25
DV25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQS0
MEM_ADDR13
MEM_DQM0
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
U15
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
DV25
MEM_DQ15
MEM_DQ16
MEM_DQ14
MEM_DQ13
MEM_DQ17
MEM_DQ18
MEM_DQ12
MEM_DQ11
MEM_DQ19
MEM_DQ20
MEM_DQ10
MEM_DQ9
MEM_DQ21
MEM_DQ22
MEM_DQ8
MEM_DQ23
MEM_DQS1
MEM_DQS2
MEM_ADDR13
MEM_VREF
MEM_DQM1
MEM_CLKA#
MEM_CLKA
MEM_CLKEN
DV25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
MEM_DQM2
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP
U18
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
MEM_DQ31
MEM_DQ30
MEM_DQ29
G ND
1,2,3,4,5,6,8 GND
MEM_DQ26
MEM_DQ25
D
GLOBAL SIGNAL
MEM_DQ24
MEM_DQS3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
MEM_VREF
MEM_DQM3
MEM_CLKB#
MEM_CLKB
MEM_CLKEN
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]
RBA [0..1]
RCLK0
RCLK0#
R CS#
RRAS#
RCAS#
RW E#
R CKE
RCLK1
RCLK1#
MEM_VREF
RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]
RBA[0..1]
RCLK0
RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE
RCLK1
RCLK1#
MEM_VREF
DDR MEMORY
EQUAL LINE LENGTH
16M x 16 DDR TSOP-66
TSOP_0D65_22D6LX9D7W_66SP
DDR#1
DV25
2,5,6 DV25
MEM_DQ28
MEM_DQ27
DDR#2
MEM_CLKA
CLOSED TO MT5351
R103
100
R0603/SMD
MEM_CLKA#
CLOSED TO DDR
C
C
RCLK1#
MEM_CLKB
R107
100
R0603/SMD
MEM_CLKB#
R108
47
R0603/SMD
CLOSED TO MT5351
+1V25_DDR
CB91
0.1uF
C0603/SMD
CLOSED TO DDR
+1V25_DDR
C168
0.1uF
C0603/SMD
CB95
0.1uF
C0603/SMD
C171
0.1uF
C0603/SMD
C170
0.1uF
C0603/SMD
C180
0.1uF
C0603/SMD
C181
0.1uF
C0603/SMD
C141
0.1uF
C0603/SMD
C142
0.1uF
C0603/SMD
C143
0.1uF
C0603/SMD
C144
0.1uF
C0603/SMD
C145
0.1uF
C0603/SMD
C147
0.1uF
C0603/SMD
C148
0.1uF
C0603/SMD
C150
0.1uF
C0603/SMD
C151
0.1uF
C0603/SMD
C160
0.1uF
C0603/SMD
C161
0.1uF
C0603/SMD
C162
0.1uF
C0603/SMD
C163
0.1uF
C0603/SMD
C164
0.1uF
C0603/SMD
C165
0.1uF
C0603/SMD
C166
0.1uF
C0603/SMD
+1V25_DDR
C146
0.1uF
C0603/SMD
+1V25_DDR
B
CB133
0.1uF
C0603/SMD
+ CE25
220uF/16v
C220UF16V/D6H11
C153
0.1uF
C0603/SMD
C154
0.1uF
C0603/SMD
C155
0.1uF
C0603/SMD
C156
0.1uF
C0603/SMD
C157
0.1uF
C0603/SMD
C158
0.1uF
C0603/SMD
C159
0.1uF
C0603/SMD
C172
0.1uF
C0603/SMD
1
2
3
4
CB125
0.1uF
C0603/SMD
CB126
0.1uF
C0603/SMD
C173
0.1uF
C0603/SMD
C174
0.1uF
C0603/SMD
C175
0.1uF
C0603/SMD
C176
0.1uF
C0603/SMD
C177
0.1uF
C0603/SMD
C178
0.1uF
C0603/SMD
U19
GND
VTT
SD
PVIN
VSENSE AVIN
VREF
VDDQ
DV25
8
7
6
5
IC LP2996 DDR Termination SOP-8
SOP8/SMD
C139
0.1uF
C0603/SMD
C152
0.1uF
C0603/SMD
+ CE24
47uF/16v
C47UF16V/D5H5
BYPASS CAP. FOR DIMM
+1V25_DDR FOR DDR TERMINATOR
MEM_VREF FOR DDR AND MT5351 VREF
FOR DDR#1
DV25
+ CE26
220uF/16v
C220UF16V/D6H11
BYPASS CAP. FOR TERMINATOR
(EVERY 2 RESISTOR PUT 1 BYPASS CAP.)
C167
0.1uF
C0603/SMD
R104
4.7K
R0603/SMD
MEM_VREF
DV25
C169
0.1uF
C0603/SMD
+ CE23
220uF/16v
C220UF16V/D6H11
FOR DDR#2
B
+1V25_DDR
BYPASS CAP. FOR DDR
DV25
C102
0.1uF
C0603/SMD
C105
0.1uF
C0603/SMD
C106
0.1uF
C0603/SMD
C107
0.1uF
C0603/SMD
C108
0.1uF
C0603/SMD
C109
0.1uF
C0603/SMD
C110
0.1uF
C0603/SMD
C111
0.1uF
C0603/SMD
C103
0.1uF
C0603/SMD
+ CE28
220uF/16v
C220UF16V/D6H11
C182
0.1uF
C0603/SMD
+ CE29
220uF/16v
C220UF16V/D6H11
ADD by Ada
A
A
Title
DDR MEMORY
Size Document Number
MT5351RA-V2
C ustom
5
4
3
2
Date:
TwinSon Chan
Monday, September 26, 2005
1
Sheet
7
of
R ev
1
8
5
D
DV33
R87
4.7K
R0603/SMD
ORESET#
C33
10pF
C0603/SMD
R88
0
R0603/SMD
4
PDA1
PDA2
PDA3
PDA4
PDA5
PDA6
PDA7
PDA8
PDA9
PDA10
PDA11
PDA12
PDA13
PDA14
PDA15
PDA16
PDA17
PDA18
PDA19
PDA20
PDA21
PDA22
POCE0#
POOE0#
POWE#
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13
26
28
11
NOR_RST#
12
U17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
CE
OE
WE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15/A-1
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
WP/ACC
RY/BY
BYTE
14
15
47
VCC
37
GND1
GND2
27
46
3
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
2
DV33
DV33
R82
NS/4.7K
R0603/SMD
PDA0
R84
0
R0603/SMD
PDA0
NOR_WP#
NOR_R Y_BY0#
GLOBAL SIGNAL
FLASH INTERFACE
DV33
5
5
5
5
5
5
RESET
IC FLASH MX29LV320 32Mb TSOP-48
TSOP48/SMD
R89
4.7K
R0603/SMD
NOR FLASH #0
R90
4.7K
R0603/SMD
1
2
3
4
U0RX
U0TX
CLI OUTPUT
J2
4x1 W/HOUSING
DIP4/W/H/P2.0
1,5
1,5
5
5
1,5
1,5
R92
4.7K
R0603/SMD
JRTCK
JTDO
R96
R97
R93
4.7K
R0603/SMD
TVTREF#1
JTRST#
JTDI
JTMS
JTCK
0
R0603/SMD
0
R0603/SMD
JTAG_DBGRQ
JTAG_DBGACK
R98
4.7K
R0603/SMD
R99
4.7K
R0603/SMD
J3
2
4
6
8
10
12
14
16
18
20
R94
4.7K
R0603/SMD
R95
4.7K
R0603/SMD
1
2
3
4
U1RX
U1TX
5
5
5
1,5
1,5
J4
R
B
G
VOHSYNC
VOVSYNC
R
B
G
VOHSYNC
VOVSYNC
4x1 W/HOUSING
DIP4/W/H/P2.0
SOFTWARE DEBUG PORT
10x2
DIP10X2/W/H/IDE/P2.54
DV33
R100
4.7K
R0603/SMD
R101
4.7K
R0603/SMD
1
2
3
4
U2RX
U2TX
B
C
UART (RS232)
DV33
1
3
5
7
9
11
13
15
17
19
U0RX
U0TX
U1RX
U1TX
U2TX
U2RX
U0RX
U0TX
U1RX
U1TX
U2TX
U2RX
2
4
6
8
RN38
1Kx4
RN0603/SMD
1
3
5
7
R91
1K
R0603/SMD
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO
JTAG PORT
DV33
C
PD D[0..7]
PDA[0..22]
5 PDD[0..7]
5 PDA[0..22]
DV33
D
POCE0#
POOE0#
POWE#
5 POCE0#
5 POOE0#
5 POWE#
FB
BEAD/SMD/0603
+ CE27
10uF/16v
C10UF16V/D5H11
CB145
0.1uF
C0603/SMD
ORESET#
1,4,5 ORESET#
PDA2
R85
NS/4.7K
R0603/SMD
C32
NS/10pF
C0603/SMD
FB9
G ND
1,2,3,4,5,6,7 GND
R83
NS/4.7K
R0603/SMD
PDA1
TRAP CIRCUIT
NS/4.7K
R0603/SMD
+5V
DV33
1,2,6 +5V
1,2,5,6 DV33
ORESET#
R86
1
FOR SOFTWARE LINK
J5
B
4x1 W/HOUSING
DIP4/W/H/P2.0
J6
R
B
G
VOHSYNC
VOVSYNC
ADD
1
2
3
4
5
6
7
8
CON8
A
A
Title
NOR FLASH / JTAG / UART
Size Document Number
MT5351RA-V2
Custom
5
4
3
2
Date:
Monday, September 26, 2005
TwinSon Chan
1
Sheet
8
of
R ev
1
8
Basic Operations & Circuit Description
MODULE
There are 1 pcs panel and 8 pcs PCB including 2 pcs Y/Z Sustainer board, 2 pcs Y Drive
board, 2 pcs X (left and right) Extension PCB, 1 pcs Control (Signal Input) and 1 pcs Power
board in the Module.
SET
There are 6 pcs PCBs including 1 pcs Tuner/Audio board, 1 pcs Keypad board, 1 pcs
Remote Control Receiver board, 1 pcs L/R Speakers and 1 pcs Main (Video) board, 1 pcs ATSC
1 pcs ATSC board in the SET.
Parts position
Internal Speaker (Right)
Power Supply
Internal Speaker (Left)
Y-Drive Top
Z-Sustainer
Y-Sustainer
Y-Drive
Bottom
External Speaker
Terminal
X Left
Extension
Power SW
ATSC
Local Key
remote control
receiver
EMI Filter + AC Inlet
Main
Tuner/Audio
Control (Signal Input)
X Right Extension
PCB function
1. Power:
(1). Input voltage: AC 110V~240V, 47Hz~63Hz.
Input range: AC 90V(Min)~265V(Max) auto regulation.
(2). To provide power for PCBs.
2. Main board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.
3. Control board: Dealing with the digital signal for output to panel.
4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.
5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning waveform to the panel.
6. X (left and right) extension board: Output addressing signals.
: Amplifying the audio signal to the internal or external speakers
7. Tuner/Audio Board:
of which selected.
To convert TV RF signal to video and SIF audio signal to Main board.
8. ATSC Board: Receiver and converter ATSC TV signal to transmit to main board.
PCB failure analysis
1. CONTROL:
2. MAIN :
a. Abnormal noise on screen. b. No picture.
a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.
3. POWER: No picture, no power output.
4. Z - Sustainer: a. No picture.
b. Color not enough.
c. Flash on screen.
5. Y - Sustainer: Darker picture with signals.
6. Tuner/Audio : a. No voice. (Make sure status: Mute / Internal, External speaker)
b. Noise
c. No ATV signals
7. Y/Z - Sustainer: The component working temperature is about 55oC.
If the temperature rises abnormal, this may be a error point.
8. ATSC: a. No ATSC TV signal
Basic operation of Plasma Display
1. After turning on power switch, power board sends 5Vst-by Volt to Main
IC MT8205 waiting for ON signals from Key Switch or Remote Receiver.
2. When the ON signal from Key Switch or Remote Receiver is detected, MT8205 will send
ON Control signals to Power. Then Power sends (5Vsc, 9Vsc, 12Vsc, 24V and RLY
ON, Vs ON) to PCBs working. This time VIF will send signals to display back light,
OSD on the panel and start to search available signal sources. If the audio signals
input, them will be amplified by Audio AMP and transmitted to Speakers.
3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.
Main IC Specifications
-
MT8205
SiI169
M13S128168A
MP7720
MT8205/8203
Application Notes
Specifications are subject to change without notice
History
2004/09/12
2004/09/30
2004/09/30
2004/10/01
2004/10/18
2004/10/20
2004/10/21
2004/11/04
Runma Chen
Dragon Chen
Runma Chen
Runma Chen
Dragon Chen &
Wen Hsu
Dragon Chen
Dragon Chen
Dragon Chen
2004/11/05
Dragon Chen
for customer design-in
Add feature list
Modify for PIP/POP 444 support
PIP/POP hardware limitation-I
PIP/POP hardware limitation-II & video front end component
V1.0
V1.1
V1.2
V1.3
V1.4
Update functional block
Correct function block fault to V1.4
1. Delete power spec. (About power spec, please reference another document)
2. Add AC & DC characteristics
3. Add pin description
4. Add audio out mapping rule
Descript more detail for pin power initial state & remove some description to
another document (MT8205 product brief)
V1.5
V1.6
V1.7
Page 1
V1.8
October, 2004
MT8205/8203
Application Notes
Specifications are subject to change without notice
MT8205/8203 Application Notes
MT8205/8203 is a highly integrated single chip for LCD TV supporting video input and output format up to HDTV.
It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals. On-chip
advanced motion adaptive de-interlacer converts accordingly the interlace video into progressive one with overlay
of a 2D Graphic processor. Optional 2nd HDTV or SDTV inputs allows user to see multi-programs on same screen.
Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio
processor decodes analog signals from Tuner with lip sync control, delivering high quality post-processed sound
effect to customers. On-chip microprocessor reduces the system BOM and shortens the schedule of UI design by
high level C program. MT8205/8203 is a cost-effective and high performance HDTV-ready solution to TV
manufactures.
FEATURES
Video Input
Input Multiplexing:
Without external switch, it supports
1x Component,
1x S-video,
1x VGA/Component, (dual function ports)
1x Digital and
3x Composite inputs
All the input sources can be flexibly routed to Main/PIP internally
Input Formats:
Support VGA input up to SXGA (1280x1024@60Hz) including SOG VGA
Support HDTV 480p/720p/1080i input
Support DVI 24-bit RGB digital input
Support CCIR-656/601 digital input
TV decoder
For PIP/POP:
Dual identical TVD on chip (Single on MT8203)
3D-Comb for both path.
Dual VBI decoders for the application of V-Chip
Supporting formats:
Support PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43, SECAM
Automatic Luma/Chroma gain control
Automatic TV standard detection
NTSC/PAL Motion Adaptive 3D comb filter
Motion Adaptive 3D Noise Reduction
VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
Macrovision detection
Page 2
October, 2004
MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
2D-Graphic/OSD processor
Two OSD planes. (For example, Teletext and V-Chip will occupy one planes)
Support alpha blending among these two planes and video
Support Text/Bitmap decoder
Support line/rectangle/gradient fill
Support bitblt
Support color Key function
Support Clip Mask
65535/256/16/4/2-color bitmap format OSD,
Automatic vertical scrolling of OSD image
Support OSD mirror and upside down
Host Micro controller
Turbo 8032 micro controller
Built-in internal 373 and 8-bit programmable lower address port
2048-bytes on-chip RAM
Up to 4M bytes FLASH-programming interface
Supports 5/3.3-Volt. FLASH interface
Supports power-down mode
Supports additional serial interface
IR control serial input
Support RS232 interface
Support single interface directly supporting SD/MS/MMC memory card
Support 2 PWM output
Support DDC2Bi/DDC2B/DDC1/DDCCI
Maximum 48 programmable GPIO pins
DRAM Controller
Supports up to 32M-byte SDR/DDR DRAM
Supports 16 bit DDR or 32 bit SDR/DDR bus interface
Build in a DRAM interface programmable clock to optimize the DRAM performance
Programmable DRAM access cycle and refresh cycle timings
Maximum DRAM clock rate is 166MHz
Support 3.3/2.5-Volt SDR/DDR Interface
Video Processor
Color Management
Flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
Gamma/anti-Gamma correction
Color Transient Improvement (CTI)
Saturation/hue adjustment
Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
White peak level limiter
Adaptive Luma/Chroma management
De-interlacing
Automatic detect film or video source
Page 3
July, 2004
MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
3:2/2:2 pull down source detection
Advanced Motion adaptive de-interlacing
Scaling
Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X
Advanced linear and non-linear Panorama scaling.
Programmable Zoom viewer
Picture-in-Picture (PIP)
Picture-Out-Picture (POP)
Display
12/10, 10/8, 8/6 Dithering processing for LCD display
10bit gamma correction
Support Alpha blending for Video and two OSD planes
Frame rate conversion
Audio Input/Output
2 path TV audio in.
Support AF/SIF decode from Tuner.
2 channel audio L/R digital line in.
Total support 12 channel digital outputs optional for general stereo, 2.1 channel with subwoofer, 5.1 channel, and
headphone out.
Audio Features
Support BTSC/EIAJ/A2/NICAM decode
Stereo demodulation, SAP demodulation
Mode selection (Main/SAP/Stereo)
Equalizer
Sub-woofer/Bass enhancement
MTK proprietary 3D surround processing (Virtual surround)
Audio and video lip synchronization
Support Reverberation
JPEG Decoder
Decode base-line/progressive JPEG file thru memory card i/f
SD/MS/MMC, Maximum 1000 files (depend on DRAM size), FW is not finished yet. (10/E will be ready)
Video Output
480i/576i/480p/576p/720p/1080i
Up to (1280x1024@75Hz) (1366x768@60Hz)
Dual-channel 6/8-bit LVDS/TTL output
Support video output mirror and upside down
DRAM Usage
For features of 8205, 2pcs of 8x16 DDR166 is necessary
For features of 8203, 2/1pcs of 8x16 DDR (limited PIP/POP features)
Here is a comparison chart between (2xDDR) and (1xDDR)
Page 4
July, 2004
MT8205
DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE
NR
3D-Comb
MDDi
PIP
POP
Display
DDR*1(16Mb)
Y
Y
480i/576i
*Y
*Y
1024x768
MTK CONFIDENTIAL, NO DISCLOSURE
DDR*2(32Mb)
Y
Y
1080i
Y
Y
1920x1080
For 1080i input, 8203 only support bob mode de-interlacing.
With single DDR, we could support very limited PIP/POP mode.
Flash Usage
Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma..
In our demo system, we can support 2-4 languages within 1MB flash.
For single country, we need around 20KB to store font data.
For more bitmaps, we need more flash space to store them.
2Mbytes is recommended to build a general TV model.
Outline
388-pin BGA package
3.3/1.8-Volt. Dual operating voltages
0.18um UMC process
Page 5
July, 2004
MT8205
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
BLOCK DIAGRAM
CVBS (AV)
(x3)
S
YPbPr
3D TVD
ADC
3D TVD
ADC
HDTVD
ADC
VGAD
Analog Path
Digital
Digital Path
Main Path
MDDi
DS
MLC
PIP Path
PLC
DS
DI
2D Graph
OSD
Merge
Control Signal (GPIO, …)
TTL
LVDS
8032
LVDS Tx
Gamma
Dithering
Page 6
DRAM
VGA (aRGB)
ADC
MUX
(Customer)
External
Switches
Analog Front End
OSD
Color
US
DSP
July, 2004
®
Technology
SiI 169
HDCP PanelLink Receiver
Data Sheet
Document # SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet
Silicon Image, Inc.
SiI-DS-0049-B
August 2002
Application Information
To obtain the most updated Application Notes and other useful information for your design, contact your local
Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Trademark Acknowledgment
®
®
Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are registered trademarks of
TM
®
Silicon Image, Inc. TMDS is a trademark of Silicon Image, Inc. VESA is a registered trademark of the Video
Electronics Standards Association. All other trademarks are the property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
Revision History
Revision
A
B
Date
07/18/2002
08/14/2002
Comment
Release to Production with complete parametric information.
Correction to DDC bus voltage level-shifting diagram; add Pb-free part number.
© 2002 Silicon Image. Inc.
ii
SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet
TABLE OF CONTENTS
Functional Description .................................................................................................................................... 2
PanelLink TMDS Core ................................................................................................................................ 2
2
I C Interface and Registers ......................................................................................................................... 2
HDCP Decryption Engine and XOR Mask .................................................................................................. 3
HDCP Keys EEPROM................................................................................................................................. 3
Panel Interface Logic and Configuration Logic ........................................................................................... 3
Electrical Specifications .................................................................................................................................. 4
Absolute Maximum Conditions.................................................................................................................... 4
Normal Operating Conditions...................................................................................................................... 4
DC Specifications ........................................................................................................................................ 5
AC Specifications ........................................................................................................................................ 6
Timing Diagrams ......................................................................................................................................... 8
Input Timing ............................................................................................................................................. 8
Output Timing .......................................................................................................................................... 8
Pin Descriptions .............................................................................................................................................11
Digital Output Pins......................................................................................................................................11
Configuration Pins ......................................................................................................................................11
HDCP Pins ................................................................................................................................................ 12
Power Management Pins .......................................................................................................................... 12
Differential Signal Data Pins...................................................................................................................... 12
Reserved Pin............................................................................................................................................. 12
Power and Ground Pins ............................................................................................................................ 13
Feature Information ...................................................................................................................................... 14
HSYNC De-jitter Function ......................................................................................................................... 14
Clock Detect Function ............................................................................................................................... 14
Sync Detect Function ................................................................................................................................ 14
OCK_INV Function.................................................................................................................................... 14
TFT Panel Data Mapping .......................................................................................................................... 16
Power Management .................................................................................................................................. 22
HDCP Operation ....................................................................................................................................... 23
HDCP Authentication............................................................................................................................. 23
SiI 169 HDCP Implementation .............................................................................................................. 24
2
HDCP DDC / I C Interface..................................................................................................................... 24
2
Video Requirement for I C Access ........................................................................................................ 25
2
I C Registers.......................................................................................................................................... 25
Using SiI 169 in SiI 161B Designs ............................................................................................................ 28
EXT_RES Resistor Choice ....................................................................................................................... 29
Power Control............................................................................................................................................ 30
Receiver DDC Bus Level-Shifting ............................................................................................................. 30
Voltage Ripple Regulation ......................................................................................................................... 31
Decoupling Capacitors .............................................................................................................................. 32
ESD Protection.......................................................................................................................................... 32
Receiver Layout ........................................................................................................................................ 33
EMI Considerations ................................................................................................................................... 33
PCB Thermal Design ................................................................................................................................ 33
Determining Heat Dissipation Requirements ........................................................................................ 33
Implementation Guidelines for Thermal Land Design ........................................................................... 34
Board Mounting Guidelines ................................................................................................................... 36
Stencil Design........................................................................................................................................ 37
Package........................................................................................................................................................ 38
Ordering Information..................................................................................................................................... 38
SiI-DS-0049-B
iii
SiI 169 HDCP PanelLink Receiver
Data Sheet
LIST OF TABLES
Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16
TM
Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2 Compliant.................... 17
Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18
Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode...................... 19
Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode...................... 20
Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode.......................................... 21
Table 8. Power Management Functionality Table ......................................................................................... 22
2
Table 9. I C Register Mapping ...................................................................................................................... 26
2
Table 10. I C Register Definitions ................................................................................................................. 27
Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29
Table 12. Power Consumption Characteristics ............................................................................................. 30
Table 13. Recommended Components ........................................................................................................ 32
LIST OF FIGURES
Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1
Figure 2. Functional Block Diagram................................................................................................................ 2
Figure 3. Channel-to-Channel Skew Timing ................................................................................................... 8
Figure 4. Digital Output Transition Times ....................................................................................................... 8
Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8
Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9
Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9
Figure 8. Output Signals Disabled Timing from Input Clock Inactive.............................................................. 9
Figure 9. Input Clock Active to Output Active ................................................................................................ 9
Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10
Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram .................................................... 10
2
Figure 12. I C Data Valid Delay (driving Read Cycle data) ........................................................................... 10
Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15
Figure 14. HDCP System Architecture ........................................................................................................ 23
2
Figure 15. I C Byte Read .............................................................................................................................. 24
2
Figure 16. I C Byte Write .............................................................................................................................. 24
Figure 17. Short Read Sequence ................................................................................................................. 25
Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29
Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30
Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31
Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31
Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32
Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................ 32
Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33
Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34
Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35
Figure 27. Thermal Pad Via Grid .................................................................................................................. 36
Figure 28. Recommended Stencil Design .................................................................................................... 37
Figure 29. Package Diagram ........................................................................................................................ 38
iv
SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet
General Description
Features
The SiI 169 Receiver uses PanelLink Digital
technology to support HDTV and high-resolution
digital displays for DTV and PC applications. It
features High-bandwidth Digital Content Protection
(HDCP) for secure delivery of high-definition video in
consumer electronics products.
•
Integrated 25-165MHz PanelLink core to support
VGA to UXGA resolutions
Supports HDTV resolutions (720p/1080i)
Integrated HDCP decryption engine for viewing
protected content
Pre-programmed HDCP keys provide highest
level of key security, simplify manufacturing
Enhanced jitter tolerance
Time staggered data output for reduced ground
bounce
High Skew Tolerance: 1 full input clock cycle
(6ns at 165MHz)
Backwards compatible with SiI 161B
Sync Detect for “Hot Plugging”
Flexible low power modes with automatic power
down when input clock is inactive
Low power 3.3V core operation
Compliant with DVI 1.0
Standard and Pb-free packages (see page 38).
•
•
•
The SiI 169 comes with integrated, pre-programmed
HDCP keys, greatly simplifying manufacturing and
providing the highest level of security. For improved
ease of use, the SiI 169 has enhanced jitter
tolerance and a low-power standby mode.
•
•
•
•
•
•
PanelLink Digital technology is the world’s leading
DVI solution, providing a digital interface solution that
is easy to implement and cost-effective. PanelLink
further simplifies the display interface design by
resolving many of the system level issues associated
with high-speed mixed signal circuits.
•
•
•
QE17
QE16
OVCC
31
30
29
QE14
QE18
32
26
QE19
33
OGND
QE20
34
QE15
QE21
35
27
QE22
36
25
QE13
52
24
QE12
QO4
53
23
QE11
QO5
54
22
QE10
QO6
55
21
QE9
QO7
56
20
QE8
OVCC
57
19
OGND
OGND
58
18
OVCC
QO8
59
17
QE7
16
QE6
15
QE5
14
QE4
13
QE3
12
QE2
QE1
QO9
60
QO10
61
QO11
62
QO12
63
SiI 169
100-pin TQFP
(Top View)
QO13
64
QO14
65
11
QO15
66
10
VCC
67
9
PDO#
SCDT
QE0
1
93
94
95
96
97
98
99
RXC+
RXC-
AVCC
EXT_RES
PVCC
PGND
RESERVED
100
92
AGND
Figure 1. SiI 169 Pin Diagram
PLL
SCL
90
91
89
AGND
RX0-
88
AVCC
RX0+
86
87
RX1-
AGND
RESET#
85
PD#
1
84
2
75
RX1+
74
QO22
AVCC
QO21
82
SDA
83
3
AVCC
73
AGND
PIXS
QO20
80
GND
4
81
5
72
RX2-
71
QO19
RX2+
QO18
79
VCC
AGND
6
78
70
OVCC
STAG_OUT
QO17
76
7
77
8
69
QO23
68
CONFIG. PINS
GND
QO16
DIFFERENTIAL SIGNALS
SiI-DS-0049-B
28
VCC
QE23
GND
37
HS_DJTR
40
39
38
CTL3
OCK_INV
41
OVCC
42
ODCK
43
DE
OGND
46
45
HSYNC
VSYNC
47
QO0
49
48
QO1
50
51
QO3
OGND
ODD 8-bits GREEN
QO2
EVEN 8-bits BLUE
ODD 8-bits RED
EVEN 8-bits RED
EVEN 8-bits GREEN
ODD 8-bits BLUE
CONTROLS
44
OUTPUT
CLOCK
SiI 169 Pin Diagram
SiI 169 HDCP PanelLink Receiver
Data Sheet
Functional Description
The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection
(HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP
keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys,
program EEPROMs, or cure epoxy coating.
PDO#
PD#
HS_DJTR
RESET#
PIXS
OCK_INV
STAG_OUT
Figure 2 shows the functional blocks of the chip.
Registers
-------------Configuration Logic
HDCP
Decryption
Engine
HDCP
Keys
EEPROM
I2C
Slave
SCLS
SDAS
CTL3
PanelLink
TMDSTM
Digital
Core
RXC±
RX0±
RX1±
RX2±
QE[23:0]
24
/
encrypted
data
XOR
Mask
24
/
unencrypted
data
control
Panel
Interface
Logic
QO[23:0]
ODCK
DE
HSYNC
VSYNC
EXT_RES
SCDT
Figure 2. Functional Block Diagram
PanelLink TMDS Core
The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high
when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the
PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video
signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to
PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.
2
I C Interface and Registers
2
The SiI 169 uses a slave I C interface, capable of running at 400kHz, for communication with the host. HDCP
2
authentication is managed by reading and writing to registers through the I C interface. This bus, called DDC in
the DVI specification, is also tied to the EDID EEPROM that contains information about the display’s capabilities
2
(resolution, aspect ratio, etc.). The I C address of the SiI 169 is 74h as specified by HDCP. This interface is not
5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector
as the DDC bus is specified to support 5V signaling.
2
SiI-DS-0049-B
SiI 169 HDCP PanelLink Receiver
Data Sheet
HDCP Decryption Engine and XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-bypixel basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the
SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI 169 is ready
to decrypt the incoming video via the XOR mask.
Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the
CTL3 signal to indicate to the SiI 169 receiver whether the incoming video is encrypted or not.
HDCP Keys EEPROM
The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the
keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all
aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from
the licensing authority. For security reasons, the keys cannot be read out of the device.
Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP specification.
These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request
either “Public” or “Production” keys when requesting samples. Before receiving samples of the SiI 169 with
production keys a customer must have signed the HDCP license agreement.
Panel Interface Logic and Configuration Logic
Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this
interface is affected by several of the externally strapped configuration logic options as follows.
•
The data output can be presented in either one pixel per clock or two pixels per clock format, depending on
the PIXS configuration setting.
•
The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking
through the OCK_INV configuration setting.
•
Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to
reduce EMI.
•
The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.
•
The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.
The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its
primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip
power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted. If it is
necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the
software reset feature located at bit 0 of register 0xFF by setting it to “1”.
SiI-DS-0049-B
3
ESMT
M13S128168A
Revision History
Revision 0.1 (15 Jan. 2002)
- Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1
Revision 0.2
M13S128168A - 5T
M13S128168A - 6T
M13S128168A - 6T
M13S128168A - 7.5AB
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2004
Revision : 1.3
1/48
ESMT
M13S128168A
DDR SDRAM
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V
Auto & Self refresh
7.8us refresh interval
SSTL-2 I/O interface
66pin TSOPII package
Operating Frequencies :
PRODUCT NO.
MAX FREQ
M13S128168A -5T
200MHz
M13S128168A -6T
166MHz
Elite Semiconductor Memory Technology Inc.
VDD
PACKAGE
2.5V
TSOPII
Publication Date : Mar. 2004
Revision : 1.3
2/48
ESMT
M13S128168A
Functional Block Diagram
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Mode Register &
Extended Mode
Register
Bank A
CAS
WE
DM
Column Decoder
Latch Circuit
RAS
Column
Address
Buffer
&
Refresh
Counter
Control Logic
CS
Command Decoder
Sense Amplifier
Data Control Circuit
CLK, CLK
DLL
Input & Output
Buffer
Address
Row Decoder
CLK
CLK
CKE
DQS
DQ
DQS
Pin Arrangement
x16
VDD
DQ 0
VDDQ
DQ 1
DQ 2
VSSQ
DQ 3
DQ 4
VDDQ
DQ 5
DQ 6
VSSQ
DQ 7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
Elite Semiconductor Memory Technology Inc.
x16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ 9
VDDQ
DQ 8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Publication Date : Mar. 2004
Revision : 1.3
3/48
MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION
General Description
Features
The MP7720 is a mono 20W Class-D Audio
Amplifier. It is one of MPS’ second generation
of fully integrated audio amplifiers which
dramatically reduces solution size by
integrating the following:

180mΩ power MOSFETs
Start up / shut down pop elimination
Short circuit protection circuits
Mute / Stand By
The MP7720 utilizes a single ended output
structure capable of delivering 20W into 4Ω
speakers. MPS Class-D Audio Amplifiers
exhibit the high fidelity of a Class A/B amplifier
at efficiencies greater than 90%. The circuit is
based on the MPS’ proprietary variable
frequency topology that delivers excellent
PSRR, fast response time and operates on a
single power supply.
Ordering Information
Part Number ∗
MP7720DS
MP7720DP
EV0030
20W output at VDD=24V into a 4Ω load
THD+N = 0.04% @ 1W, 8Ω
93% efficiency at 20W
Low noise (190µV typical)
Switching Frequency to 1MHz
9.5V to 24V operation from single supply
Integrated Start Up and Shut Down
Pop Elimination Circuit
Thermal protection
Integrated 180mΩ switches
Mute / Standby-mode (Sleep)
Tiny 8 Pin SOIC or PDIP Package
Evaluation Board Available

Applications
Surround Sound DVD Systems
Televisions
Flat Panel Monitors
Multimedia computers
Home stereo

Package
Temperature
SOIC8
-40°C to + 85°C
PDIP8
-40°C to + 85°C
Evaluation Board
∗ For Tape & Reel use suffix - Z (e.g. MP7720DS-Z)
∗ For Lead Free use suffix - LF (e.g. MP7720DS-LF)
20
VDD
7.5V to 24V
10
5
ON
OFF
VDD
2
EN
PGND
NIN
8Ω
1
PIN
BS
%
AGND
4Ω
0.5
0.2
SW
0.1
0.05
0.02
Audio
Input
0.01
60m
100m
200m
500m
1
2
5
10
20
30
W
4 Ω or 8 Ω
Figure 2: THD+N vs. Power (24V, 1KHz)
Figure 1: Typical Application Circuit
MP7720 Rev 1.5 06/17/04
www.monolithicpower.com
1
MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION
Absolute Maximum Ratings
(Note 1)
26V
Supply Voltage VDD
BS Voltage
VSW-0.3V to VSW+6.5V
-0.3V to 6V
Enable Voltage VEN
-1V to VDD+1V
VSW, VPIN, VNIN
AGND to PGND
-0.3V to 0.3V
Junction Temperature
150°C
Lead Temperature
260°C
Storage Temperature
-65°C to 150°C
Recommended Operating Conditions (Note 2)
9.5V to 24V
Supply Voltage VDD
Operating Temperature TA
-40°C to 85°C
Package Thermal Characteristics
Thermal Resistance ΘJA (SOIC8)
Thermal Resistance ΘJC (SOIC8)
Thermal Resistance ΘJA (PDIP8)
Thermal Resistance ΘJC (PDIP8)
105°C/W
50°C/W
95°C/W
55°C/W
Table 1: Electrical Characteristics (VDD=24V, VEN=5V, TA=25°C)
Parameters
Supply Current
Standby Current
Quiescent Current
Output Drivers
SW On Resistance
Short Circuit Current
Inputs
PIN, NIN Input Common Mode
Voltage Range
PIN, NIN Input Current
EN Enable Threshold Voltage
EN Enable Input Current
Thermal Shutdown
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
Condition
Typ
VEN = 0V
1
1.5
Sourcing and Sinking
Sourcing and Sinking
0.18
5.0
0
VPIN=VNIN=12V
VEN Rising
VEN Falling
VEN = 5V
TJ Rising
0.4
VDD
2
1
1.4
1.2
1
Max
Units
5
3.0
µA
mA
Ω
A
VDD-1.5
V
5
2.0
µA
V
V
µA
150
30
°C
°C
Table 2: Operating Specifications (Circuit of Figure 3, VDD=24V, VEN=5V, TA=25°C)
Standby Current
Quiescent Current
Power Output
THD+ Noise
Efficiency
Maximum Power Bandwidth
Dynamic Range
Noise Floor
Power Supply Rejection
VEN = 0V
f=1KHz, THD+N = 10% , 4Ω Load
f=1KHz, THD+N = 10% , 8Ω Load
POUT=1W, f=1KHz, 4Ω Load
POUT=1W, f=1KHz, 8Ω Load
f =1KHz, POUT=1W, 4Ω Load
f =1KHz, POUT=1W, 8Ω Load
A-Weighted
f=1KHz
130
13
20
10
0.08
0.04
90
95
20
93
190
60
µA
mA
W
W
%
%
%
%
KHz
dB
µV
dB
Note 1. Exceeding these ratings may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
MP7720 Rev 1.5 06/17/04
www.monolithicpower.com
2
MP7720
20W Class D Mono
Single Ended Audio Amplifier
Monolithic Power Systems
PRELIMINARY INFORMATION
R3
100KΩ
VDD
ON
OFF
PGND
MP7720
R1, 10KΩ
C1
1µF, 16V
C9
1000µF
25V
C7, 0.1µF
D2, 6.2V
BS
L1, 10µH
AGND
SW
C2
4.7µF,
16V
Audio Input
VDD
9.5 to 24V
PIN
NIN
R2
100KΩ
C5
1µF, 35V
EN
C3, 5.6nF
C6
470µF, 35V
R6
10KΩ
R4, 82KΩ
C4
10pF
C10
390pF
D1
1A, 30V
C8
0.47µF
50V Metal
RL
4Ω
R5
10kΩ
Figure 3: 20W Mono Typical Application Circuit
MP7720 Rev 1.5 06/17/04
www.monolithicpower.com
3
Product Specification of PDP Module
0. Warnings and Cautions
9 WARNING indicates hazards that may lead to death or injury if ignored.
9 CAUTION indicates hazards that may lead to injury or damage to property if ignored.
WARNING
1)
This product uses a high voltage (450 V max.). Do not touch the circuitry of this product with your hands when
power is supplied to the product or immediately after turning off the power. Be sure to confirm that the voltage
is dropped to a sufficiently low level.
2)
Do not supply a voltage higher than that specified to this product. This may damage the product and may cause a
fire.
3)
Do not use this product in locations where the humidity is extremely high, where it may be splashed with water,
or where flammable materials surround it. Do not install or use the product in a location that does no satisfy the
specified environmental conditions. This may damage the product and may cause a fire.
4)
If a foreign substance (such as water, metal, or liquid) gets inside the product, immediately turn off the power.
Continuing to use the products it may cause fire or electric shock.
5)
If the product emits smoke, an abnormal smell, or makes an abnormal sound, immediately turn off the power. If
noting is displayed or if the display goes out during use, immediately turn off the power. Continuing to use the
product as it is may cause fire or electric shock.
6)
Do not disconnect or connect the connector while power to the product is on. It takes some time for the voltage
to drop to a sufficiently low level after the power has been turned off. Confirm that the voltage has dropped to a
safe level before disconnecting or connecting the connector. Otherwise, this may cause fire, electric shock, or
malfunction.
7)
Do not pull out or insert the power cable from/to an outlet with wet hands. It may cause electric shock.
8)
Do not damage or modify the power cable. It may cause fire or electric shock.
9)
If the power cable is damaged, or if the connector is loose, do not use the product; otherwise, this can lead to fire
or electric shock.
10)
If the power connector or the connector of the power cable becomes dirty or dusty, wipe it with a dry cloth.
Otherwise, this can lead to fire.
Product Specification of PDP Module
USE
1)
Because this product uses a high voltage, connecting or disconnecting the connectors while power is supplied to
the product may cause malfunctioning. Never connect or disconnect the connectors while the power is on.
Immediately after power has been turned off, a residual voltage remains in the product. Be sure to confirm that
the voltage has dropped to a sufficiently low level.
2)
Watching the display for a long time can tire the eyes. Take a break at appropriate intervals.
3)
PDP ’s brightness and contrast ratio is lower than that of the CRT. The picture is dimmer with surrounding light
and better for viewing in dark condition.
4)
Do not cover or wrap the product with a cloth or other covering while power is supplied to the product.
5)
Before turning on power to the product, check the wiring of the product and confirm that the supply voltage is
within the rated voltage range. If the wiring is wrong or if a voltage outside the rated range is applied, the
product may malfunction or be damaged.
6)
Do not store this product in a location where temperature and humidity are high. This may cause the product to
malfunction. Because this product uses a discharge phenomenon, it may take time to light (operation may be
delayed) when the product is used after it has been stored for a long time. In this case, it is recommended to light
all cells for about 2hours (aging).
7)
If the glass surface of the display becomes dirty, wipe it with a soft cloth moistened with a neutral detergent. Do
not use acidic or alkaline liquids, or organic solvents.
8)
Do not tilt or turn upside down while the module package is carried, the product may be damaged.
9)
This product is made from various materials such as glass, metal, and plastic. When discarding it, be sure to
contact a professional waste disposal operator.
Repair and Maintenance
Because this product combines the display panel and driver circuits in a single module, it cannot be repaired or
maintained at user’s office or plant. Arrangements for maintenance and repair will be determined later
Product Specification of PDP Module
1. GENERAL DESCRIPTION
DESCRIPTION
The PDP42V6#### is a 42-inch 16:9 color plasma display module with resolution of 852(H) × 480(V) pixels.
This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.
FEARURES
High peak brightness (1000cd/m2 Typical) and high contrast ratio (3000:1 Typical) enables user to create
high performance PDP SETs.
APPLICATIONS
9 Public information display
9 Video conference systems
9 Education and training systems
Product Specification of PDP Module
ELECTRICAL INTERFACE OF PLASMA DISPLAY
The PDP42V6#### requires only 8bits of digital video signals for each RGB color.
In addition to the video signals, six different DC voltages are required to operate the display.
The PDP42V6#### is equipped with P-CUBE function which analyzes display signals to optimize system
control factor for showing the best display performance.
GENERAL SPECFICATIONS
9 Model Name
9 Number of Pixels
9 Pixel Pitch
9 Cell Pitch
9 Display Area
9 Outline Dimension
9 Pixel Type
9 Number of Gradations
9 Weight
9 Aspect Ratio
9 Peak Brightness
9 Contrast Ratio
9 Power Consumption
9 Life-time
: PDP42V6#### (42V6#### Model)
: 852(H) × 480(V) (1pixel=3 RGB cells)
: 1080㎛ (H) × 1080㎛ (V)
: 367㎛ (H) × 1080㎛ (V) (Green Cell basis)
: 920.1(H) × 518.4(V) ±0.5mm
: 1005(H) × 597(V) × 61(D)±1mm
: RGB Closed type
: (R)256 × (G)256 × (B)256 (16.7 Mega colors)
: 14.8 Kg ± 0.5 Kg (Net 1EA)
111 Kg ± 5 Kg (5EA/1BOX)
: 16:9
: Typical 1000cd/㎡ (1/25 White Window)
: Average 60:1 (In a bright room with 150Lux at center)
: Typical 3000:1 (In a dark room 1/25 White Window pattern at center)
: Typical 220 W (Full White)
: more than 60,000 Hours of continuous operation
☞ Life-time is defined as the time when the brightness level becomes half of its initial value.
9 Display Dot Diagram
1st
pixel
column
Pixel Pitch(width)
2nd
pixel
column
Cell pitch
1.080㎜
1st pixel
row
2nd pixel
row
851th
pixel
column
R:0.338㎜
G:0.367㎜
B:0.374㎜
852th
pixel
column
cell
R G B R G B
R G B R G B
R G B R G B
R G B R G B
479th pixel
row
R G B R G B
R G B R G B
480th pixel
row
R G B R G B
R G B R G B
3rd pixel
row
1.080㎜
R G B R G B
pitch(height)
R G B R G B
pixel
Product Specification of PDP Module
7. CONNECTORS and CONNECTIONS
Power Input Connector
¾ Connector P3001 Pin Assignment
Pin No.
Symbol
Pin No.
Symbol
1
Vs
5
GND
2
Vs
6
Va
3
nc
7
GND
4
GND
8
+5V
8
7
6
5
4
3
2
1
1-1123723-8 Pin numbers
(Top View, viewed from the pin connection side)
9 Module side connector : 1-1123723-8 (Header)
9 Mating Connector
: 1-1123722-8 (Housing)
9 Connector Supplier
: AMP
¾ Connector P2005 Pin Assignment
Pin No.
Symbol
Pin No.
Symbol
1
VS
6
GND
2
VS
7
GND
3
VS
8
GND
4
nc
9
nc
5
GND
10
nc
9 Module side connector : 1-1123723-10 (Header)
9 Mating Connector
: 1-1123722 –10 (Housing)
9 Connector Supplier
: AMP
10
9
8
7
6
5
4
3
2
1
1-1123723-10 Pin numbers
(Top View, viewed from the pin connection side)
¾ Connector P2006 Pin Assignment
Pin No.
Symbol
Pin No.
Symbol
1
GND
3
5V
2
GND
4
5V
9 Module side connector : 1-1123723-4 (Header)
9 Mating Connector
: 1-1123722-4 (Housing)
9 Connector Supplier
: AMP
4
3
2
1
1-1123723-4 Pin numbers
(Top View, viewed from the pin connection side)
¨ Pin Assignment
Product Specification of Power Supply Unit
8. Input/Output pin assignment & specification
CN808
1
2
3
4
5
6
7
8
CN804
1
2
3
4
5
6
7
8
9
CN803
1
2
3
4
5
6
7
8
9
10
11
12
CN805
#1 ~ #4
: +5Vctrl
#5 ~ #8
: GND
#1 ~ #3 : 5Vsc
#4 ~ #6 : GND
#7, #8 : 12Vsc
#9, #10 : GND
#11, #12 : NC
CN802
1
2
3
4
CN801
1
2
3
4
5
6
7
#1 : 9Vsc
#2: GND
#1 ~#2
: 30V or 24V
#3 ~ #4
: GND
Selection S/W
24V 30V
#1 : ACD
#2 : RLY ON
#3 : 5Vst_by
#4 : GND
#5 : Vs ON
#6 : 5VD
#7 : NC
8 7 6 5 4 3 2 1
#1 : Va
#2 : Va
#3 : GND
#4 : GND
#5 : GND
#6 : GND
#7 : NC
#8 : Vs
#9 : Vs
#10 : Vs
#1 ~#2
: 5Vctrl
#3 ~ #4
: GND
#1 : 9Vsc
#2 : 9Vsc
#3 : GND
#4 : 5Vsc
#5 : 5Vsc
#6 : 5Vsc
#7 : GND
#8 : GND
#9 : GND
CN807
CN806
4 3 2 1
CN809
1
2
10 9 8 7 6 5 4 3 2 1
#1 : Vs
#2 : Vs
#3 : NC
#4 : GND
#5 : GND
#6 : Va
#7 : GND
#8 : +5V
Location No.
Specification
Vendor
CN01
3-176976-2(Red)
AMP
CN02
3-176976-1(Natural)
AMP
CN03
3-176976-1(Natural)
AMP
CN801
171825-7
AMP
CN802
171825-4
AMP
CN803
1-171825-2
AMP
CN804
171825-9
AMP
CN805
1-1123723-4
AMP
CN806
1-1123723-0
AMP
CN807
1-1123723-8
AMP
CN808
171825-8
AMP
CN809
171825-2
AMP
* PSU operation method S/W
1
2
Auto : Automatic On/Off
without Vsc B/D
Normal : On/Off with Vsc B/D
CN01
1
CN02
2
Before connecting with S/W
Live
2
2
Neutral
1
Live
1
From inlet
CN03
Neutral
After connecting with S/W
¨ Adjustment detail
Product Specification of Power Supply Unit
9. Adjustment detail
CN808
CN805
1
2
3
4
5
6
7
8
10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Vs adj.
CN804
1
2
3
4
5
6
7
8
9
CN807
CN806
4 3 2 1
* Vs Voltage Variabe Resistor
- Turn right, increase Voltage
Turn left, decrease Voltage
Selection S/W
Va adj.
CN803
24V 30V
1
2
3
4
5
6
7
8
9
10
11
12
* Va Voltage Variabe Resistor
- Turn right, increase Voltage
Turn left, decrease Voltage
* You can select output Audio Voltage(24V or 30V)
CN809
Selection S/W
1
2
CN802
1
2
3
4
Normal
(Mode1)
Auto
(Mode2)
* PSU driving method S/W
Auto(Mode2) : Driving without
1
2
interface B/D
CN801
1
2
3
4
5
6
7
Normal(Mode1) : Driving with interface B/D
* Connect with Noisefilter Cable
2
Neutral
CN03
Live
2
Live
* Connect with S/W Cable
1
2
CN02
1
1
* Connect with S/W Cable
Neutral
CN01
※ The color of CN01 is red.(The color of CN02, CN03 are natural.)
Product Specification of PDP Module
8. LABEL
LABEL Sticking Position
Coner Plate
E/X Tube
ⓐ
ⓑ
ⓒ
ⓓ
ⓔ
ⓕ
ⓖ
3211QKE008A
Z - SUS
Y-SUS
CONTROLLER
Signal Input
(R,G,B,H/Vsync.)
X left
X right
Identification Label : LABEL ⓐ
7.0 ㎝
①
②
2.5 ㎝
③
⑦
④
⑤
⑥
① Model Name
② Bar Code (Code 128, Contains the manufacture No.)
③ Manufacture No.
④ The trade name of LG Electronics
⑤ Manufactured date (Year & Month)
⑥ Manufactured place
P/N
(carved)
Trouble Shooting Manual of PDP Module
-
Introduction
Precautions
Basic
Trouble shooting
1. Introduction
COMPOSITION OF PDP BOARDS
PSU
42” V6 MODEL.
Y-DRIVE
Z-SUS B/D
TOP
Y-SUS
B/D
IPM
IPM
Y-DRIVE
BOTTOM
X-LEFT B/D
COF
COF
CONTROL B/D
X-RIGHT B/D
1. Introduction
Definitions
■ Definition of MODULE position
long 1
* Back side of module
Exhaust
hole
short 1
long 2
COF long2-1
••••••••
short 2
COF long 2-7
■ Identification label
①
②
③
6####
402K242V6000266.ASLGA ⑦
2004.02
④
⑤
⑥
① Model Name
② Bar Code (Code 128, Contains the manufacture No.)
③ Manufacture No.
④ The trade name of LG Electronics
⑤ Manufactured date (Year & Month)
⑥ The place Origin
⑦ Model Suffix
1. Introduction
■ Voltage label (Attached on back side of module)
Vsetup
-Vy
■ Part No. label (Attached on board)
Vsc
BOARD ASS`Y
PART NO.
BOARD NAME
BOARD SERIAL NO.
PCB PART NO.
■ COF serial No. label (attached on COF)
COF SERIAL NO.
1. Introduction
■ Terms of defect
Term
Appearance
Add short (line on)
Add open (line off)
Sus short (line on)
Sus open (line off)
8 /40
2. Precaution
Safety precautions
Be sure to read this before service. When using/ handling this PDP module, Please pay attention to the
below warning and cautions.
1. Before repairing there must be a preparation for 10 min.
2. Do not impress a voltage that higher than represented on the product.
3. Since PDP module uses high voltages, Be careful a electric shock
and after removing power some current remains in drive circuit.
so you can touch circuit after 1 min.
4. Drive circuits must be protected from static electricity.
5. The PDP module must be Moved by two man.
6. Be careful with short circuit of PDP boards when measuring any voltages.
Before request service
1. Check panel surface and appearance of B/D.
2. Check the model label. Whether it is boards of same model with label.
3. Before requesting Service, please inform us a detail defect phenomenon and history of module.
it can be helpful to us for a smooth sevice.
Ex) COF long 2-1 fail ,address 1 line open, Y b/d problem , mis-discharge.
9 /40
2. Precaution
Handle with care (COF)
COF is the most important component in the PDP module.
Even a little imperfection of COF can make a serious screen problem.
SCRATCHING
BENDING
TEARING
CHOPING
BEING PUSHED
3. Basic
1. X B/D
: receiving LOGIC signal from CONTROL B/D and make ADDRESS
PULSE(generates Address discharge)by ON/OFF operation,
and supplies this waveform to COF(data)
Signal part
Power part
X RIGHT B/D
X LEFT B/D
<COF Separating>
Lift up lock as shown
in narrow.
Pull COF
as shown in narrow.
3. Basic
2. Z sustain B/D
: make SUSTAIN PULSE and ERASE PULSE that generates
SUSTAIN discharge in panel by receiving LOGIC signal from
CONTROL B/D.
this waveform is supplied to panel through FPC(Z).
*composed with IPM,FET,DIODE, electrolytic capacitor ,E/R coil.
* IPM (Intelligent Power Module)
<FPC Separating>
Separate the fixed Screw of Z-Board.
Pull out Lock as shown in arrow.
E/R(Energy recovery)
Condition in Lock part is pulled
12 /40
Pull FPC Connector
as shown in arrow.
3. Basic
3. Y drive B/D
1) This is a path to supply SUSTAIN ,RESET waveform which made
from Y SUSTAIN B/D to panel through SCAN DRIVER IC.
2) Supply a wave form that select Horizontal electrode (Y SUSTAIN electrode)
sequentially.
- potential difference is 0V between GND and Vpp of DRIVER IC
in SUSTAIN period.
- being generated potential difference between GND and Vpp only
in SCAN period.
* In case of 42” V6 use DRIVER IC IC 8 EA (TOP, BOTTOM: each 4EA)
13 /40
3. Basic
4. Y sustain B/D
: generates SUSTAIN,RESET waveform, Vsc(SCAN)voltage.
and supplies it Y DRIVER B/D.
* Composed with IPM,DIODE, electrolytic capacitor ,FET.
5. Control Board
: creates signal processing (Contour noise,reduction ISM,..)
and an order of many FET on/off of each DRIVER B/D with
R,G,B each 8bit input.
* Use 3.3V/5V 2 kinds of power .
14 /40
3. Basic
DC/DC con.
part
6. DC/DC Converter part
: Being impressed 5V, Va ,Vs,
DC/DC converter makes
5V,Va,Vs,Vset_up,Vsc
which is essential for each B/D.
There is no DC/DC B/D in
model 40 〞 /42 〞(1 POWER B/D).
* 50 〞 60 〞embedded DC/DC B/D
separately because of high power
consumption.
15 /40
3. Basic
7. FPC (Flexible Printed Circuit)
: supply a driving waveform to PANEL by connecting a PAD
electrode of PANEL with PCB(Y and Z).
* there is two type of this for Y B/D. One is single-sided,
another is double-side. These are having pattern on it
* for Z B/D, there is no pattern , single-sided, and Beta
type(all of copper surface).
8. FFC (Flat Flexible Cable)
: for connecting a Logic signal between B/D and B/D.
*There is 0.5mm pitch,50pin type
1mm pitch ,30pin type.
16 /40
3. Basic
9. COF (Chip On Film)
: supply a waveform which made from X B/D to panel and select
a output pin that is controlled by COF when be on or off.
96 output pin per IC.
─ the more the resolution higher, the less spare space where
can set IC on it in B/D. without using IC PACKAGE,
we can use a BARE IC , so we can get IC with LOW COST
─ because we do not solder IC on PCB directly,
a soldering defect rate decrease.
* composition
Bare IC
1) FPC + Heat /Sink
⇒ FPC for COF must have a Low Spec decline with getting damp
2) CHIP resistor + CHIP CAPACITOR
3) BARE IC (STV7610A/WAF) + GOLD WIRE/AL WIRE
4) EPOXY MOLDING
* 42 V6 COF is the same as 42V5.
3. Basic
10. IPM(Intelligent Power Module)
: composition
HEATSINK,CAPACITOR
DIODE
IC LINEAR
RESISTORTANSISTOR,FETS.
: description
Attached at Z B/D and Y B/D, make Sustain waveform.
Sustainer : supply a square wave to panel to make a video.
IPM
18 /40
4. Trouble shooting.
Fast check
updefect?
what
kind of
defect
Check model No. of module ,all connectors and cables.
No display?
Check panel appearance
Check Y, Z b/dinput voltage
Replace Y, Z b/d
Replace ctrl b/d
vertical defect?
Check panel appearance
Horizontal defect?
Check FPC
Mis –discharge
on screen?
Check PSU output (Va,Vs,5v)
Check COF
Replace Y drv b/d
Replace Y drv b/d
Replace Y sus b/d
Replace Y sus b/d
19 /40
Replace X b/d
Replace ctrl b/d
Replace ctrl b/d
Replace ctrl b/d
4. Trouble shooting.
Logical
judgment
what
kind
of defect?
What kind of defect ?
No display?
vertical defect?
Please follow the no display trouble shooting.
Bar defect appeared?
Please follow bar defect trouble shooting.
Line defect
Horizontal defect?
Please follow the line defect trouble shooting.
Mis –discharge
on screen?
Please follow the mis discharge trouble shooting.
20 /40
4. Trouble shooting.
No display
Check each section with following method if there is problem, replace or repair that part.
If not go to the next section.
1. Connector
Confirm every Connector (PSU, Y-SUS, CTRL, Z-SUS)
⇒ module may not be normal by mis-connection which can not send signal and power.
Also Mis connection for a long time has a specific b/d failed.
CTRL B/D + Y-SUS
CTRL B/D + Z-SUS
CTRL B/D + X-B/D
21 /40
Signal input(LVDS)
4. Trouble shooting.
2. Exhaust tip Crack
Confirm exhausting Tip and find Crack with naked eyes to check vacuum state.
If there is problem replace the module .
⇒ in case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.
(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )
NORMAL
CRACKED
22 /40
4. Trouble shooting.
3. PSU(Power Supply Unit)
1. Check each unit part of PSU inside with naked eyes.
(capacitor, FET, a kind of IC, resistor)
2. Check FUSE and SW1 (on Normal).
3. Check Output voltage which is converted from AC V
SW1 Normal
to DC V.
voltage Check (5V, Va, Vs)
※ When PSU Protection occurred. Check Short
between Y-SUS, Z-SUS B/D .
Confirm
input voltage
if not same
Multi-meter Touch point
(5V, Va ,Vs must accord with Module Label)
Fuse open check
Adjust
voltages
Vs Voltage ADJ
(Vs : About 180 ~195 V)
Va, 5V(VCC) Voltage ADJ
■ Va : About 55 ~65 V
■ 5V(VCC) : 5V~5.5V)
4. Trouble shooting.
4. Ctrl B/D
Diode
1. Confirm LED D17(flashing) ,13 lighting
2. If not CHECK OSC X1 output.
Input voltage
3. Check CTRL input voltage
(CONNECTOR P300)
4. CHECK 3.3V, 5V,15V.
5. Check IC 11 3.3V
IC 3 2.5V
OSC(X1)
Probe
Touching
point
Check IC 11,13
DMM +
Check oscillating state.
(normal 100 MHZ)
Be careful with physical shock.
DMM – (GND)
4. Trouble shooting.
5. Y-sus B/D
1. Check FUSE [FS1(5v) ,FS2(Vs)].
Vscw
FS2
2. Check voltages(Vsetup,-Vy, Vscw)
Vsetup
3. Check DIODE between GND and Y SUS output.
setdn
[SUSUP(OC2) SUSDN(OC1)].
forward=0.4 ,reverse=OVERLOAD.
4. Check whether output voltages agrees
setup
with voltage that represented in label.
-Vy
FS1
25 /40
4. Trouble shooting.
■ Check whether output voltages agrees with voltage that represented in label.
■ Check diode value GND between Y-SUS output.
Normal diode value= 0.4 (forward)
Normal diode value = OL (reverse)
4. Trouble shooting.
6. Z-sus B/D
1. Check the FUSE.
2. Check input voltages.(Va, 5V,15V)
3. Check FPC out put diode value.
4. Check ramp waveform.
■ Check input voltages
■ Check the FUSE
5V FUSE
Va FUSE 6.3A
Vs FUSE 2A or 4A
4. Trouble shooting.
■ Variable resistance of Z RAMP
waveform slope.
■ Check FPC output diode value.
caution: check certainly after removing FPC.
Normal diode value=0.375(forward)
Normal diode value=OVER LOAD(reverse)
4. Trouble shooting.
◎
Power protection
It is power protection when power is off automatically within 2~3 min. from power on.
Power protection function protect the boards when occurred short on circuits of PDP module or power problem.
If can not impress power even after replacing PSU, find out where the short occurred.
* PSU makers.
DAEGIL PSU
UNICON PSU
29 /40
4. Trouble shooting.
Vertical defect (bar)
Check each section with following method if there is problem, replace or repair that part.
If not go to the next section.
1. Connector
Check here
Bar
Check COF connector.
If not connected well,it will Make a bar defect .
Check here
Off
2. Checking COF
Confirm whether COF was torn. And then check input of COF resistor and IC.
COF 6 is torn partly
Tearing
30 /40
4. Trouble shooting.
◎
Checking address COF input of resistor and IC
■ COF resistor checking
Check the both side of resistor With Digital multi meter(DMM) .
If the resistor is normal, the resistor value will be 10.2 ~ 10.8 Ω
But if not, the value will be 0 or infinity and replace the resistor.
31 /40
4. Trouble shooting.
◎
Checking address COF input of resistor and IC
■ IC input checking
Inside of IC , there is 4 ea diodes which separated in 2 series .
(input 2, output 2)
*how to check
1.contact DMM - terminal to a right terminal of condenser(GND)
and DMM + terminal to a right terminal of IC, normal value 0.66 (fig.1)
2.contact DMM - terminal to Output terminal of resistor, and
DMM + terminal to a right terminal of IC , normal value 0.73 (fig.2)
Fig. 2
Fig. 1
DMM(- terminal)
`
DMM (+ terminal)
DMM (- terminal)
DMM( + terminal)
4. Trouble shooting.
3. Ctrl B/D
CTRL B/D supplies video signal to COF. So if there is a bar defect on screen,
It may be the ctrl b/d problem.
<Diagram of ctrl b/d>
A flow of address signal
In this figure, we can easily suppose
MCM
what will be appeared on screen when a specific part failed.
Buffer
IC
Array저항
각각 16 line
COF IC1
96 output
COF IC2
COF IC3
COF IC4
4. Trouble shooting.
Vertical defect (line)
In case of 1 line open or short , check foreign substances in COF connector.
First blow up foreign substances with your mouth. And then if the same line appears, replace the panel.
1 line open or short
This phenomenon is due to COF IC inside short or adherence part of the Film and rear panel electrode problem.
In this case, replace the panel.
1 electrode open
1 line open
Line open or short with same distance.
This is MCM of Ctrl b/d defect. MCM can not be replaced separately. So replace the ctrl b/d.
MCM (Multi Chip Module)
4. Trouble shooting.
line defect from each parts
• Case 1: Buffer IC fail
16 line open
COF IC 1,2 ⇒ 192 line(96+96) open.
COF IC 3,4 ⇒ 64 line open (with fixed interval there is on,off ……. Repetition)
• case 2 : Array resistor fail
COF IC1 ⇒ 16 line , COF IC2 ⇒ 16 line open
• case3 : COF IC fail
96 line open
96 line open.
/40
4. Trouble shooting.
Horizontal (bar)
Most horizontal defects can be repaired. In case of adherence part of the Film and rear panel
electrode defect or panel electrode open,short , replace the panel.
1. Connector
It can make a horizontal bar that connector on Y b/d and Z b/d did not plugged well. Because sustain voltage
can not be supplied to panel. So check connectors (FPC, Y drv –Y drv) first.
Disconnected
Disconnected
Horizontal bar
Screen off
4. Trouble shooting.
2. Scan IC check
Check diode value of the right side part of output pin.
Normal diode value. (in case of Panasonic IC=1.035)
Defect diode value= 0.018
* It can be different from each IC Maker. (in case of TI IC= 0.6~0.7)
DMM +
DMM -
Check here with DMM(either forward or reverse is ok)
37 /40
4. Trouble shooting.
Horizontal (line)
1. Check FPC
In case of horizontal 1 or more line, it is due to FPC or panel inside .
ctrl b/d, Y b/d is just normal.
FPC electrode open
Panel electrode
Insulation break down
2. Check scan IC
Check with same method that presented in Horizontal (bar).
38 /40
Horizontal 1 line.
4. Trouble shooting.
◎
How to check IPM
Forward : test 1 GND(＋) , Sus-out(－)
2 Sus-out(＋),Vs(－)
3 ER-DN(－),ER-COM(＋)
4 ER-COM(－),ER-UP(＋)
when each 4 TEST Diode value is over 0.4V => OK
Reverse : test 1 GND(－) , Sus-out(＋)
2 Sus-out(－),Vs(＋)
3 ER-DN(＋),ER-COM(－)
4 ER-COM(＋),ER-UP(－)
when each 4 nodes TEST Diode value is infinity => OK
※ Specially, the value of ER-UP,COM,DN in the Y/Z board, should be
checked all of them. but, the terminal of Vs,Sus-out,GND,
we must aware to know after check one of IPM because it is parallel.
Æ
if no problems, check 15V(Y,Z B/D) with GND, Î Forward value 0.3V,
Reverse value infinite. If no problems,
40 /40
Product Specification of PDP Module
CAUTION
General
1)
Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.
2)
When moving the product, be sure to turn off the power and disconnect all the cables. While moving the
product, watch your step. The product may be dropped or fall, leading to injuries of electric shock.
3)
Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as an
inclined surface. The product may fall off or fall over, causing injuries.
4)
Before disconnecting cable from the product, be sure to turn off the power. Be sure to hold the connector when
disconnecting cables. Pulling a cable with excessive force may cause the core of the cable to be exposed or
break the cable, and this can lead to fire or electric shock.
5)
This product should be moved by two or more persons. If one person attempts to carry this product alone, he/she
may be injured.
6)
This product contains glass. The glass may break, causing injuries, if shock, vibration, heat, or distortion is
applied to the product.
7)
The temperature of the glass surface of the display may rise to 80°C or more depending on the conditions of use.
If you touch the glass inadvertently, you may be burned.
8)
Do not poke or strike the glass surface of the display with a hard object. The glass may break or be scratched. If
the glass breaks, you may be injured.
9)
If you glass surface of the display breaks or is scratched, do not touch the broken pieces or the scratches with
bare hands. You may be injured.
10)
Do not place an object on the glass surface of the display. The glass may break or be scratched.
Spare Part List for PDP4210EA
Part Number
Part Description
Item
Usage
/ Unit
Unit
1
E6205-001003
42” ED PDP Module
1
Piece
2
900-420103-01B
42” Glass Filter
1
piece
3
E7801-100001
Main PCBA
1
set
4
E7801-100002
Audio PCBA
1
set
5
771S42D101-01
ATSC PCBA
1
set
7
771-42D111-01
Control PCBA
1
set
8
771-42D111-02
IR PCBA
1
set
9
E4101-027001
Power Switch
1
piece
10
E4801-116002
Speaker
2
piece
11
E3301-028005
Speaker Terminal (without cable)
1
piece
12
E3404-157004
AC Power Cord
1
piece
13
E3421-926080
LVDS Cable
1
piece
14
E3421-925049
Connection Cable 1
1
piece
15
E3421-926083
Connection Cable 3
1
piece
16
E3421-926084
Connection Cable 4
1
piece
17
E3421-927001
Power Switch Cable 1
1
piece
18
E3421-927002
Power Switch Cable 2
1
piece
19
E3421-926081
Control PCBA Cable
1
piece
20
E3421-926094
IR PCBA Cable
1
piece
21
E7501-051007
Remote Control
1
set
22
E7301-010002
AAA size Battery
1
pair
Spare Part List for PDP4210EA
Part Number
Part Description
Item
Usage
/ Unit
Unit
23
200-42D131-MTK02AV Front Plastic Frame
1
piece
24
277-42D101-01S
Function Knob
1
piece
25
263-42D101-01S
Power Lens
1
piece
26
269-42D101-01L
IR Lens
1
piece
27
481-42D107-01S
PCBA Shield Box
1
piece
28
483-42D103-01
PCBA Shield Top Cover
1
piece
29
436-42D118-01S
Terminal Frame
1
piece
30
402-42D114-01S
Metal Back Cover
1
piece
31
423-42D11E-01S
Power Switch Metal Frame
1
piece
32
510-42D101-MTU02K
Top Carton Box
1
piece
33
511-42D111-01K
Bottom Carton Box
1
piece
34
300-42D106-02C
Top Cushion
1
piece
35
300-42D105-02C
Bottom Cushion
1
piece
36
244-34B811-01
Carton Box Handle
2
piece
37
310-504004-01
Poly bag for Main Unit
1
piece
38
310-111404-07V
Poly bag for Instruction Manual
1
piece
39
580-P42AAEM-TU02L
Instruction Manual
1
piece
40
388-42SB04-01H
Power Socket Plate
1
piece
41
388-42D103-01H
Caution Plate
1
piece
42
387-42AA01-MTU02H
Model Plate
1
piece
43
388-42SB02-01H
Speaker Terminal Plate
1
piece
44
384-42D103-MTU01H
Terminal Plate
1
piece
45
590-42AA01-04
Warranty Sheet
1
piece
Spare Part List for PDP4210EA
Part Number
Part Description
Item
Usage
/ Unit
Unit
46
579-42D102-09
Model Plate Serial Number
1
piece
47
579-42AA01-05
Bar Code Label
1
pair
48
579-42D103-02
ON/OFF Label
1
piece
49
568-P46T02-02
Warning Label
1
piece
50
734-BP0302-01
Duck Feet Stand
1
set
Exploded View
If you forget your V-Chip Password
- Omnipotence V-Chip Password: 8205.
Using the “Change Password” item
When enter the “Parental” menu, select “Change Password”.
Press ▲ or ▼ button to highlight the “Change Password” item.
Press Enter button to conﬁrm and pop up a menu.
Use 0~9 buttons input the omnipotence password(8205), then Press Enter button to enter and
pop up a menu.
Use 0~9 buttons input your new password.
Press ▼ button to move to conﬁrm blank.
Use 0~9 buttons input your new password again.
Press Enter button to conﬁrm
-Suggest: Change to your familiar Password again.
Software upgrade
Process of update MT8205AE
Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC .
Downloading :
3) Turn on AC power and wait TV entering standby mode, while the color of the power
indicator is Red.
4) Execute MTKtool and select the chipset as MT8205. (the software of MTKtool will be sent to
your side)
5) Select current COM port. (please try to check the COM port of your PC).
6) Choose the bit rate as 115200.
7) Select the update binary by pressing browse button. For exemple,the binary file name is
PDP4210EA_VIORE_XXXXXX_XXXX_VXX.bin. (this update firmware will be sent
to your side)
8) Press Upgrade button and start update process.
9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.
Checking
It is needed to check the version of the firmware for MT8205AE which has been
download into the Plasma TV .
Press Menu button of the remote control for a little long time and the OSD menu
for Factory Setting is appeared on the screen .
Use the remote control and select the mode of the Factory Setting then enter the
mode of the Factory Setting .
Use the remote control and select the mode of Firmware Version and then enter the
mode of Firmware Version . It is easy to be found the version of the current firmware
for MT8205AE is as the following : “Firmware Version : VXX ”
Process of update MT5351AG
Preparing :
1) Connect RS232-VGA download line, One connector is connected to VGA connect port of
Plasma TV while another side is connected to PC COM port.
2) Store the MtkTool into the PC
Downloading :
3) Turn on AC power switch of the Plasma TV and then press the button “standby” of the remote
control . The image could be found on the screen of the Plasma TV while the color of the
power indicator is green . (the mode of the Plasma TV will be standby mode if after turn on
the main power switch only . )
4) Execute MTKtool and select the chipset as MT5351AG. (the software of MTKtool will be sent
to your side)
5) Select current COM port. (please try to check the COM port of your PC).
6) Choose the bit rate as 115200.
7) Select the update binary by pressing browse button. For exemple,the binary file name is
XXXX_PDP4210EA_ATSC_IT_000000XX_X_P.bin. (this update firmware will be sent
to your side)
8) Press Upgrade button and start update process.
9) The update process is successful as the progress bar is 100%. After the update process is ok,
turn off power and wait indicator light is off. Turn on power and TV can work.
Checking :
It is needed to check the version of the firmware for MT5351AG which has been
download into the Plasma TV .
Press Menu button of the remote control and the main OSD menu is appeared on
the screen .
Use the remote control and select the mode of the adjustment .
Use the remote control and select the mode of DTV
Entry the mode of DTV
Input “0000” (zero , zero , zero , zero) of the remote control while the Plsama TV is
under the above condition . Then enter the mode of factory after input the digits .
It is easy to be found the version of the current firmware for MT5351AG is
“XXXX_PDP4210EA_ATSC_IT_000000XX_X_P”under the mode of factory .
PC
RS232-VGA download line
RXD
TXD
GND
2
3
5
D-Sub 9(RS232)
PDP
11
4
5
RXD
TXD
GND
D-Sub 15A(VGA)