Download LED LCD TV SERVICE MANUAL

Internal Use Only
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Europe/Africa
Asia/Oceania
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LED LCD TV
SERVICE MANUAL
CHASSIS : LD03R
MODEL: 42LX6500/650N
MODEL: 42LX6800/6900
42X6500/650N-ZD
42X6800/6900-ZD
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P
P/NO : MFL63748401 (1006-REV01)
OK
MENU
INPUT
Printed in Korea
CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION ................................................................ 8
BLOCK DIAGRAM.................................................................................. 17
EXPLODED VIEW .................................................................................. 19
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-2-
LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-3-
To Instrument's
exposed
METALLIC PARTS
0.15 uF
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
1.5 Kohm/10W
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1 Ω
*Base on Adjustment standard
LGE Internal Use Only
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
3. Test method
1. Application range
This specification is applied to the LCD TV used LD03R
chassis.
2. Requirement for Test
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC :CE, IEC
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC
2) Relative Humidity : 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Module General Specification
No.
Item
Specification
Remark
1
Display Screen Device
107 cm(42 inch) wide color display module
2
Aspect Ratio
16:9
3
LCD Module
107 cm(42 inch) TFT LCD FHD 240 Hz(Edge)
4
Operating Environment Temp. : 0 deg ~ 50 deg
Humidity : 20 % ~ 90 %
5
Storage Environment
Temp. : -20 deg ~ 60 deg
Humidity : 10 ~ 90 %
6
Input Voltage
AC 100-240V~, 50 / 60Hz
7
Power Consumption
Power on (White)
LGD
LCD (Module) + Backlight(EDGE LED)
Typ : 112.2(Edge)
8
Module Size
973.2 (H) x 566.2 (V) x 10.8 mm(D)
8
Pixel Pitch
0.4845 (H) x 0.4845 (V)
9
Back Light
LED(EDGE)
10
Display Colors
1.06 B(true) colors
11
Coating
3H
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-4-
LGE Internal Use Only
5. Module optical specification
No.
Item
Specification
1.
Viewing Angle [CR>10]
Right/Left/Up/Down
2.
Luminance
2D
Min.
Typ.
89
Luminance (cd/m2)
450
48
61
3.
Contrast Ratio
CR
4.
3D Cross talk
%
1000
1300
5.
CIE Color Coordinates
White
1.3
Luminance (cd/m2)
14
Wx
0.279
Wy
0.292
RED
Xr
Green
Blue
Remark
CR > 10
360
Variation
3D
Max.
MAX /MIN
18
0.642
Yr
Typ.
0.335
Typ.
Xg
-0.03
0.308
+0.03
Yg
0.602
Xb
0.156
Yb
0.061
1) Standard Test Condition(The unit has been ‘ON’).
2) Stable for approximately 60 minutes in a dark environment at 25 ºC.
3) The values specified are at approximate distance 50 cm from the LCD surface.
6. Component Video Input (Y, CB/PB, CR/PR)
Specification
No.
Resolution
1.
720x480
Remark
H-freq(kHz)
15.73
V-freq(Hz)
60.00
SDTV,DVD 480i
2.
720x480
15.63
59.94
SDTV,DVD 480i
3.
720x480
31.47
59.94
480p
4.
720x480
31.50
60.00
480p
5.
720x576
15.625
50.00
SDTV,DVD 625 Line
6.
720x576
31.25
50.00
HDTV 576p
7.
1280x720
45.00
50.00
HDTV 720p
8.
1280x720
44.96
59.94
HDTV 720p
9.
1280x720
45.00
60.00
HDTV 720p
10.
1920x1080
31.25
50.00
HDTV 1080i
11.
1920x1080
33.75
60.00
HDTV 1080i
12.
1920x1080
33.72
59.94
HDTV 1080i
13.
1920x1080
56.250
50
HDTV 1080p
14.
1920x1080
67.5
60
HDTV 1080p
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-5-
LGE Internal Use Only
7. RGB (PC)
Specification
No.
Resolution
H-freq(kHz)
V-freq(Hz)
Pixel Clock(MHz)
Proposed
Remarks
Input 848*480 60 Hz, 852*480 60 Hz
1.
720*400
31.468
70.08
28.321
2.
640*480
31.469
59.94
25.17
VESA
For only DOS mode
3.
800*600
37.879
60.31
40.00
VESA
4.
1024*768
48.363
60.00
65.00
VESA(XGA)
5.
1280*768
47.78
59.87
79.5
WXGA
6.
1360*768
47.72
59.8
84.75
WXGA
7.
1280*1024
63.595
60.0
108.875
SXGA
FHD model
8.
1920*1080
66.587
59.93
138.625
WUXGA
FHD model
-> 640*480 60 Hz Display
8. HDMI Input
(1) DTV Mode
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
59.94 /60
Pixel clock(MHz)
27.00/27.03
Proposed
1.
720*480
31.469 /31.5
2.
720*576
31.25
50
54
SDTV 576P
3.
1280*720
37.500
50
74.25
HDTV 720P
4.
1280*720
44.96 /45
59.94 /60
74.17/74.25
HDTV 720P
5.
1920*1080
33.72 /33.75
59.94 /60
74.17/74.25
HDTV 1080I
6.
1920*1080
28.125
50.00
74.25
HDTV 1080I
7.
1920*1080
26.97 /27
23.97 /24
74.17/74.25
HDTV 1080P
8.
1920*1080
33.716 /33.75
29.976 /30.00
74.25
HDTV 1080P
9.
1920*1080
56.250
50
148.5
HDTV 1080P
10.
1920*1080
67.43 /67.5
59.94 /60
148.35/148.50
HDTV 1080P
Remark
SDTV 480P
(2) PC Mode
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
70.08
Pixel clock(MHz)
Proposed
720*400
31.468
2.
640*480
31.469
59.94
25.17
VESA
HDCP
3.
800*600
37.879
60.31
40.00
VESA
HDCP
4.
1024*768
48.363
60.00
65.00
VESA(XGA)
HDCP
5.
1280*768
47.78
59.87
79.5
WXGA
HDCP
6.
1360*768
47.72
59.8
84.75
WXGA
HDCP
7.
1280*1024
63.595
60.0
108.875
SXGA
HDCP/FHD model
8.
1920*1080
67.5
60.00
138.625
WUXGA
HDCP/FHD model
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
28.321
Remark
1.
-6-
HDCP
LGE Internal Use Only
9. 3D Mode - HDMI & USB
(1) HDMI Input (1.4)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
3D input proposed mode
1
1920*1080
53.95 / 54
23.98 / 24
148.35/148.5
HDTV 1080P
Frame packing
2
1280*720
89.9 / 90
59.94/60
148.35/148.5
HDTV 720P
Frame packing
3
1280*720
75
50
148.5
HDTV 720P
Frame packing
4
1920*1080
67.5
60
148.5
HDTV 1080P
Side by Side(half), Top and bottom
5
1920*1080
56.3
50
148.5
HDTV 1080P
Side by Side(half), Top and bottom
6
1280*720
45
60
74.25
HDTV 720P
Side by Side(half), Top and Bottom
7
1280*720
37.5
50
74.25
HDTV 720P
Side by Side(half), Top and Bottom
8
1920*1080
33.7
60
74.25
HDTV 1080i
Side by Side(half), Top and Bottom
9
1920*1080
28.1
50
74.25
HDTV 1080i
Side by Side(half), Top and Bottom
10
1920*1080
27
24
74.25
HDTV 1080P
Side by Side(half), Top and Bottom
11
1920*1080
33.7
30
89.1
HDTV 1080P
Side by Side(half), Top and Bottom
(2) HDMI Input (1.3)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
3D input proposed mode
1
1280*720
45.00
60.00
74.25
HDTV 720P
Side by Side, Top & Bottom
2
1280*720
37.500
50
74.25
HDTV 720P
Side by Side, Top & Bottom
3
1920*1080
33.75
60.00
74.25
HDTV 1080I
Side by Side, Top & Bottom
4
1920*1080
28.125
50.00
74.25
HDTV 1080I
Side by Side, Top & Bottom
5
1920*1080
27.00
24.00
74.25
HDTV 1080P
Side by Side, Top & Bottom,
Checkerboard
6
1920*1080
33.75
30.00
74.25
HDTV 1080P
Side by Side, Top & Bottom,
Checkerboard
7
1920*1080
67.50
60.00
148.5
HDTV 1080P
Side by Side, Top & Bottom,
Checkerboard, Single Frame Sequential
8
1920*1080
56.250
50
148.5
HDTV 1080P
Side by Side, Top & Bottom,
Checkerboard, Single Frame Sequential
(3) USB Input
No.
1.
Resolution
1920*1080
H-freq(kHz)
33.75
V-freq.(Hz)
30.000
Pixel clock(MHz)
3D input proposed mode
74.25
Side by Side
Remark
HDTV 1080P
Top & Bottom
Checkerboard
(4) 3D Input mode
No.
Side by Side
Top & Bottom
Checkerboard
Single Frame Sequential
Frame Packing
1.
L
R
L
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-7-
LGE Internal Use Only
ADJUSTMENT INSTRUCTION
(3) Adjustment
1) Adjustment method
- Using RS-232, adjust items listed in 3.1 in the other
shown in “3.1.(3).3)”
1. Application Range
This specification sheet is applied to all of the LCD TV with
LD03R chassis.
2) Adj. protocol
2. Designation
Protocol
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~ 50 / 60Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
Command
aa 00 00
a 00 OK00x
Source change
xb 00 40
b 00 OK40x (Adjust 480i, 1080p Comp1 )
xb 00 60
b 00 OK60x (Adjust 1920*1080 RGB)
Begin adj.
ad 00 10
Return adj. result
OKx (Case of Success)
NGx (Case of Fail)
Read adj. data
Confirm adj.
(main)
000000000000000000000000007c007b006dx
(sub)
(Sub)
ad 00 21
000000070000000000000000007c00830077x
ad 00 99
NG 03 00x (Fail)
NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)
End adj.
In case of keeping module is in the circumstance of below 20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
aa 00 90
a 00 OK90x
Ref.) ADC Adj. RS232C Protocol_Ver1.0
3) Adj. order
- aa 00 00 [Enter ADC adj. mode]
- xb 00 04 [Change input source to Component1(480i&1080p)]
- ad 00 10 [Adjust 480i Comp1]
- xb 00 06 [Change input source to RGB(1024*768)]
- ad 00 10 [Adjust 1024*768 RGB]
- ad 00 90 End adj.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3.2. MAC Address
3.1. ADC Adjustment
(1) Overview
ADC adjustment is needed to find the optimum black level
and gain in Analog-to-Digital device and to compensate
RGB deviation.
(2) Equipment & Condition
1) Jig (RS-232C protocol)
2) MSPG-925 Series Pattern Generator(MSPG-925FA,
pattern - 65)
- Resolution : 480i Comp1
1080P Comp1
1920*1080 RGB
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level : 0.7±0.1 Vp-p
- Image
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
(main)
ad 00 20
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours
3. Automatic Adjustment
Set ACK
Enter adj. mode
-8-
(1) Equipment & Condition
- Play file: Serial.exe
- MAC Address edit
- Input Start / End MAC address
(2) Download method
1) Communication Prot connection
PCBA
PC(RS-232C)
RS-232C Po rt
Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
LGE Internal Use Only
2) MAC Address Download
- Com 1,2,3,4 and 115200(Baud rate)
- Port connection button click(1)
3.4. LAN PORT INSPECTION(PING TEST)
Connect SET -> LAN port == PC -> LAN Port
SET
PC
(1) Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
Program.
*IP Number : 12.12.2.2
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE
- Load button click(2) for MAC Address write.
- Start MAC Address write button(3)
- Check the OK Or NG
3.3. LAN
(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig
(2) LAN inspection solution
A LAN Port connection with PCB
A Network setting at MENU Mode of TV
A setting automatic IP
A Setting state confirmation
-> If automatic setting is finished, you confirm IP and
MAC Address.
3.5. V-COM Adjust(Only LGD(M+S) Module)
- Why need Vcom adjustment?
A The Vcom (Common Voltage) is a Reference Voltage of
Liquid Crystal Driving.
-> Liquid Crystal need for Polarity Change with every frame.
Circuit Block
Ga mma
Re f e r e nce V o ltage
Data (R ,G,B ) &
Cont rol si gnal
Y
Da t a I n p u t
S
In t e r f a ce
S
Ti m i n g
Co nt r o ll e r
Power
Po w e rInput
I nput
Po w e r
Blo ck
V COM
Gat e Driv e IC
E
Gamm a Reference
Volta ge
Cont rol si gnal
So urce D r i v e I C
T
M
Data (R ,G,B ) & C ont ro l s ignal
Column Line
Pane l
V COM
CST
CLC
Liquid
Crys tal
Row Li ne TFT
V COM
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-9-
LGE Internal Use Only
- Adjust sequence
A Press the PIP key of the ADJ remote control. (This PIP
key is hot key to enter the VCOM adjusting mode)
(Or After enter Service Mode by pushing “ADJ” key, then
Enter V-Com Adjust mode by pushing “G” key at “10. VCom”)
A As pushing the right or the left button on the remote
control, And find the V-COM value Which is no or
minimized the Flicker.
(If there is no flicker at default value, Press the exit key
and finish the VCOM adjustment.)
A Push the OK key to store value. Then the message
“Saving OK” is pop.
A Press the exit key to finish VCOM adjustment.
3.7. CI+ Key Download method
(1) Download Procedure
1) Press "Power on" button of a service R/C.(Baud rate :
115200 bps)
2) Connect RS232-C Signal Cable.
3) Write CI+ Key through RS-232-C.
4) Check whether the key was downloaded or not at ‘In
Start’ menu. (Refer to below).
[Visual Adjust and control the Voltage level]
3.6. Model name & serial number download
(1) Model name & Serial number D/L
A Press “Power on” key of service remote control.(Baud
rate : 115200 bps)
A Connect RS232 Signal Cable to RS-232 Jack.
A Write Serial number by use RS-232.
A Must check the serial number at Instart menu.
(2) Method & notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C.Serial number D/L must be conformed when it is
produced in production line, because serial number D/L
is mandatory by D-book 4.0
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man,
sometimes model name or serial number is initialized.(Not
always)
There is impossible to download by bar code scan, so It
need Manual download.
a. Press the ‘instart’ key of ADJ remote control.
b. Go to the menu ‘5.Model Number D/L’ like below photo.
c. Input the Factory model name(ex 42LD450-ZA) or Serial
number like photo.
=> Check the Download to CI+ Key value in LGset.
1. check the method of CI+ Key value
a. check the method on Instart menu
b. check the method of RS232C Command
1) into the main ass’y mode (RS232 : aa 00 00)
CMD 1
CMD 2
A
A
Data 0
0
0
2) check the key download for transmitted command
(RS232 : ci 00 10)
CMD 1
CMD 2
C
I
Data 0
1
0
3) result value
- normally status for download : OKx
- abnormally status for download : NGx
2. Check the method of CI+ Key value (RS232)
1) into the main ass’y mode (RS232 : aa 00 00)
CMD 1
CMD 2
A
A
Data 0
0
0
2) Check the method of CI+ key by command (RS232 :
ci 00 20)
CMD 1
CMD 2
C
I
Data 0
2
0
3) Result value
i 01 OK 1d1852d21c1ed5dcx
CI+ key Value
d. Check the model name Instart menu -> Factory name
displayed (ex 42LE7500-ZA)
e. Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LE7500-ZA)
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 10 -
LGE Internal Use Only
4.2. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download
4. Manual Adjustment
4.1. ADC(GP2) Adjustment
4.1.1. Overview
ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
deviation.
4.1.2. Equipment & Condition
(1) Adjust Remote control
(2) 801GF(802B, 802F, 802R) or MSPG925FA Pattern
Generator
- Resolution :
480i, 720*480 (MSPG-925FA -> Model: 209, Pattern: 65)
- 480i
1080p, 1920*1080 (MSPG-925FA -> Model: 225, Pattern:
65) - 1080p
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level: 0.7 ± 0.1 Vp-p
- Image
(3) Must use standard cable
(1) Overview
It is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
(2) Equipment
- Adjust remote control
- Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
(3)Download method
1) Press Adj. key on the Adj. R/C, then select “10.EDID
D/L”, By pressing Enter key, enter EDID D/L menu.
2) Select [Start] button by pressing Enter key, HDMI1 /
HDMI2 / HDMI3 / HDMI4 / RGB are Writing and display
OK or NG.
For Analog EDID
For HDMI EDID
D-sub to D-sub
DVI-D to HDMI or HDMI to HDMI
(4) EDID DATA
A HDMI
4.1.3. Adjust method
(1) ADC 480i, 1080p Comp1
1) Check connected condition of Comp1 cable to the equipment
2) Give a 480i, 1080p Mode, Horizontal 100% Color Bar
Pattern to Comp1.
(MSPG-925FA -> Model: 209, Pattern: 65) - 480i
(MSPG-925FA -> Model: 225, Pattern: 65) - 1080p
3) Change input mode as Component1 and picture mode
as “Standard”
4) Press the In-start Key on the ADJ remote after at least 1
min of signal reception. Then, select 7. External ADC ->
1. COMP 1080p on the menu. Press enter key. The
adjustment will start automatically.
5) If ADC calibration is successful, “ADC RGB Success” is
displayed.
If ADC calibration is failure, “ADC RGB Fail” is displayed.
6) If ADC calibration is failure, after recheck ADC pattern or
condition retry calibration Error message refer to 5).
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x00 00
0x02 0F
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 11 -
50
ⓐ
ⓑ
FF
FF
FF
FF
FF
00
1E
6D
01
03
80
10
09
78
0A
EE
91
A3
54
4C
99
26
54
A1
08
00
71
4F
81
80
01
01
01
01
01
01
2C
0x03 01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
0x04 45
00
A0
5A
00
00
00
1E
01
1D
00
72
51
D0
1E
20
0x05 6E
28
55
00
A0
5A
00
00
00
1E
00
00
00
FD
00
3A
0x06 3E
1E
53
10
00
0A
20
20
20
20
20
20
01
ⓔ1
14
03
20
21
ⓓ
ⓓ
0x07
0x00 02
03
37
F1
4E
10
1F
84
13
05
0x01 22
15
01
26
15
07
50
09
57
07
E3
05
03
01
01
02
12
1D
80
18
71
1C
16
20
58
5A
00
00
00
9E
01
1D
00
80
51
D0
1A
ⓕ
ⓕ
0x02
0x03
ⓕ
0x04 2C
25
00
A0
0x05 20
6E
88
55
00
A0
5A
00
00
00
1A
02
3A
80
18
71
0x06 38
2D
40
58
2C
45
00
A0
5A
00
00
00
1E
00
00
00
0x07 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
ⓔ2
A
(2) ADC 1920*1080 RGB
1) Check connected condition of Component & RGB cable
to the equipment
2) Give a 1920*1080 Mode, 100 % Horizontal Color Bar
Pattern to RGB port.
(MSPG-925 Series -> model: 225 , pattern: 65 )
3) Change input mode as RGB and picture mode as “Standard”.
4) Press the In-start Key on the ADJ remote after at least 1
min of signal reception. Then, select 7. External ADC ->
1. COMP 1080p on the menu. Press enter key. The
adjustment will start automatically.
5) If ADC calibration is successful, “ADC RGB Success” is
displayed.
If ADC calibration is failure, “ADC RGB Fail” is displayed.
6) If ADC calibration is failure, after recheck ADC pattern or
condition retry calibration Error message refer to 5).
FF
ⓒ
0x01
RGB
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x00 00
FF
ⓒ
0x01
0x02 0F
50
ⓐ
ⓑ
FF
FF
FF
FF
FF
00
1E
6D
01
03
68
10
09
78
0A
EE
91
A3
54
4C
99
26
54
A1
08
00
81
80
61
40
45
40
31
40
01
01
2C
0x03 01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
0x04 45
00
A0
5A
00
00
00
1E
01
1D
00
72
51
D0
1E
20
0x05 6E
28
55
00
A0
5A
00
00
00
1E
00
00
00
FD
00
3A
0x06 3E
1E
53
10
00
0A
20
20
20
20
20
20
00
ⓔ3
ⓓ
0x07
ⓓ
Reference
- HDMI1 ~ HDMI4 / RGB
- In the data of EDID, bellows may be different by S/W or
Input mode.
A
LGE Internal Use Only
4.3.3. Equipment connection MAP
ⓐ Product ID
Model Name
HEX
EDID Table
DDC Function
ALL
0001
0100
Analog
0001
0100
Co lo r Analyzer
RS -232C
Probe
Co m p ut er
Digital
RS -232C
RS -232C
ⓑ Serial No. : Controlled on product line
Pat t ern Generat o r
Signal Source
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ -> ‘01’
Year : ‘2010’ -> ‘14’
ⓓ Model Name(Hex):
* If TV internal pattern is used, not needed
4.3.4. Adj. Command (Protocol)
<Command Format>
MODEL
MODEL NAME(HEX)
all
00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
LEN
INPUT
1
2
3
D7
CB
X
HDMI2
D7
BB
X
HDMI3
D7
AB
X
HDMI4
D7
9B
X
HDMI5
X
X
1D
VAL
CS
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
ⓔ Checksum: Changeable by total EDID data.
HDMI1
CMD
A
RS-232C Command used during auto-adj.
RS-232C COMMAND
ⓕ Vendor Specific(HDMI)
Explanation
[CMD
ID
DATA]
wb
00
00
HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb
00
10
Gain adj.(internal white pattern)
HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb
00
1f
Gain adj. completed
HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb
00
20
Offset adj.(internal white pattern)
HDMI4 78 03 0C 00 40 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb
00
2f
Offset adj. completed
HDMI5 78 03 0C 00 50 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb
00
ff
End White Balance adj.(Internal pattern disappears)
INPUT
MODEL NAME(HEX)
Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f -> Gain adj. completed
*(wb 00 20(Start), wb 00 2f(completed)) -> Off-set adj.
wb 00 ff -> End white balance auto-adj.
4.3. White Balance Adjustment
4.3.1 Overview
(1) W/B adj. Objective & How-it-works
(2) Objective: To reduce each Panel’s W/B deviation
(3) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(4) Adj. condition : normal temperature
1) Surrounding Temperature : 25 ºC ± 5 ºC
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
A
Adj. Map
ITEM
Cool
4.3.2 Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14)
2) Adj. Computer(During auto adj., RS-232C protocol is
needed)
3) Adjust Remote control
4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model:217, Pattern:78)
-> Only when internal pattern is not available
A
Begin White Balance adj.
Command
Data Range(Hex.) Default(Decimal)
Cmd 1
Cmd 2
Min
Max
R-Gain
j
g
00
C0
G-Gain
j
h
00
C0
B-Gain
j
i
00
C0
R-Gain
j
a
00
C0
G-Gain
j
b
00
C0
B-Gain
j
c
00
C0
R-Cut
G-Cut
B-Cut
Medium
Color Analyzer Matrix should be calibrated using CS-1000
R-Cut
G-Cut
B-Cut
Warm
R-Gain
j
d
00
C0
G-Gain
j
e
00
C0
B-Gain
j
f
00
C0
R-Cut
G-Cut
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 12 -
LGE Internal Use Only
4.3.5. Adj. method
A
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable (RS-232C)
4) Select mode in adj. Program and begin adjustment.
5) When adj. is complete (OK Sing), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
A
W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need.
Mode
A
Color Coordination
x
Temp
∆UV
y
COOL
0.269 ± 0.002
0.273 ± 0.002 13000 K
0.0000
MEDIUM
0.285 ± 0.002
0.293 ± 0.002
9300 K
0.0000
WARM
0.313 ± 0.002
0.329 ± 0.002
6500 K
0.0000
4.3.7. IOP & Edge LED White balance table
(2) Manual adj. method
1) Set TV in Adj. mode using POWER ON
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10cm of the surface.
3) Press ADJ key -> EZ adjust using adj. R/C -> 7. WhiteBalance then press the cursor to the right (KEY G).
(When KEY(G) is pressed 216 Gray internal pattern will
be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature.
A
Standard color coordinate and temperature using CA210(CH 9)
If internal pattern is not available, use RF input. In EZ
Adj. menu 7.White Balance, you can select one of 2
Test-pattern: ON, OFF. Default is inner(ON). By
selecting OFF, you can adjust using RF signal in 216
Gray pattern.
IOP & Edge LED module change color coordinate because
of aging time.
A apply under the color coordinate table, for compensated
aging time.
- EDGE LED(LX65)
A
GP2
Aging Time
(Min.)
Cool
Medium
Warm
X
Y
X
Y
X
Y
269
273
285
293
313
329
1
0-2
280
291
296
311
319
340
2
3-5
278
288
294
308
317
338
3
6-9
276
285
292
305
315
335
4
10-15
274
282
290
302
313
332
5
20-35
273
279
289
299
312
329
6
36-49
270
276
287
296
310
326
7
50-79
269
273
286
293
308
323
8
Over 80
269
273
285
293
308
323
Adj. condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer (CA-210) probe should be within
10cm and perpendicular of the module surface (80°~
100°)
3) Aging time
- After Aging Start, Keep the Power ON status during
5 Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.3.6. Reference (White Balance Adj. coordinate
and temperature)
A
A
Luminance : 216 Gray
Standard color coordinate and temperature using CS-1000
(over 26 inch)
Mode
Color Coordination
x
Temp
∆UV
y
COOL
0.269
0.273
13000 K
0.0000
MEDIUM
0.285
0.293
9300 K
0.0000
WARM
0.313
0.329
6500 K
0.0000
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 13 -
LGE Internal Use Only
4.4. Wireless function check
4.6. Local Dimming Function Check
Step 1) Connect set and Dongle of Wireless to Cable of HDMI
& TTA 20Pin
Step 2) At OSD of SET, check the message like Fig.3
Step 3) Detach Cable of Wireless Dongle
Step 1) Turn on TV.
Step 2) At the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
Step 3) Confirm the Local Dimming mode.
Step 4) Press “exit” key
Connect
Fig . 1
< Do ng le>
Fig . 2
Local Dimming Demo (Edge LED Model)
< Wireless Read y Set >
Local Dimming Demo (IOP Model)
4.7. 3D function test
(Pattern Generator MSHG-600, MSPG-6100 [Support HDMI 1.4])
* HDMI mode No. 872, pattern No. 83)
1) Please input 3D test pattern like below
Fig . 3 Connect the Dongle
( Do ng le Co nnec t io n Disp lay)
4.5. EYE-Q function check
Step 1) Turn on TV
Step 2) Press EYE key of Adj. R/C
Step 3) Cover the Eye Q II sensor on the front of the using
your hand and wait for 6 seconds
Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
Data (Sensor data, Back light)”. If after 6 seconds,
R/G/B value is not lower than 10, replace Eye Q II
sensor.
Step 5) Remove your hand from the Eye Q II sensor and wait
for 6 seconds.
Step 6) Confirm that “ok” pop up. If change is not seen,
replace Eye Q II sensor.
2) When 3D OSD appear automatically, then select OK button.
3) Don’t wear a 3D Glasses, Check the picture like below.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 14 -
LGE Internal Use Only
4.8. IR emitter inspection
5. GND and Internal Pressure check
(1) Start 3D pattern inspection
(2) If IR emitter emitter signal is correctly received to IR
receiver, the lamp of IR tester turn on
5.1. Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
<IR Emitter inspection>
5.2. Checkpoint
<IR Tester Lamp turned off(NG)>
• TEST voltage
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
• TEST time: 1 second
• TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
• LEAKAGE CURRENT: At 0.5mArms
<IR Tester Lamp turned on(OK)>
4.9. Option selection per country
(1) Overview
- Option selection is only done for models in Non-EU.
- Applied model: LD03D/03E Chassis applied EU model.
(2) Method
1) Press ADJ key on the Adj. Remote Control, then select
Country Group Menu.
2) Depending on destination, select Country Group Code
04 or Country Group EU then on the lower Country
option, select US, CA, MX. Selection is done using +, or GF KEY.
4.10. Tool Option selection
- Method : Press Adj. key on the Adj. Remote Control, then
select Tool option.
Mode
42LX6500
Tool 1
33760
Tool 2
31795
Tool 3
54316
Tool 4
22956
6. Audio
Measurement condition:
1. RF input: Mono, 1KHz sine wave signal, 100% Modulation
2. CVBS, Component: 1KHz sine wave signal 0.4Vrms
3. RGB PC: 1KHz sine wave signal 0.7Vrms
No.
1.
Item
Audio practical max
Tool 5
Output, L/R
2874
(Distortion=10 %
Min. Typ. Max. Unit
4.5
5
6
W
EQ Off
AVL Off
6.33 6.93 Vrms Clear Voice Off
max Output)
4.11. Ship-out mode check(In-stop)
2.
After final inspection, press IN-STOP key of the Adj. R/C and
check that the unit goes to Stand-by mode.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 15 -
Speaker (8 Ω
Impedance)
5
7
W
EQ On
AVL On
Clear Voice On
LGE Internal Use Only
7. USB S/W Download (option, Service only)
1) Put the USB Stick to the USB socket
2) Automatically detecting update file in USB Stick
- If your downloaded program version in USB Stick is Low,
it didn’t work. But your downloaded version is High, USB
data is automatically detecting
3) Show the message “Copying files from memory”
4) Updating is starting.
5) Updating Completed, The TV will restart automatically
6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.
1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and Push “OK” button.
3) Push in the number. (Each model has their number.)
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 16 -
LGE Internal Use Only
BLOCK DIAGRAM
1. MAIN
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 17 -
LGE Internal Use Only
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 18 -
IR Emitter
P2402
51P LVDS
Power
Block
12V
LVDS
3D_SYNC_OUT
51P LVDS
LVDS,12V,I/ F
Main
HW opt ion
LVDS Rx
(2 Ch)
SPI -Flash
( 2MBI T)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
FRC
240Hz
(LG1120) LVDS Tx
(2 Ch)
FPGA
config.
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
I2C(SCL/ SDA)
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
DDR2 * 2
( 512 MBI T)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
SPI -Flash
EPCS16 SI 8N
( 2MBI T)
3DF
FPGA
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
Main Board I/ F
3.3V 2.5V 1.8V 1.26V
Oscillator
LVDS Tx
(2 Ch)
DDR2 * 4
( 512 MBI T)
240Hz FRC + 3D Formatter + TCON
EEPROM
TCON
240
240HZ
TCON
240HZ
EEPROM
mini LVDS
VCOM &
P- gam m a
mini LVDS
80P
mini LVDS
80P
mini LVDS
Module
2. 3F BOARD
LGE Internal Use Only
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
900
910
830
820
500
300
120
570
A2
A21
A5
200
A10
LV1
A13
LV2
530
541
810
540
800
880
840
521
920
400
710
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
Copyright
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 19 -
LGE Internal Use Only
EXT IRQ
GPIO_00, GPIO_01, GPIO_02,
GPIO_11, GPIO_11, GPIO_39
H23
CI_A[5]
J25
CI_A[6]
F26
CI_A[8]
H28
CI_A[9]
J26
CI_A[13]
H27
CI_A[12]
G26
CI_A[11]
J27
CI_A[10]
J28
CI_A[7]
22
R116
F27
22
H26
G24
R122
R117
G27
33
EBI_RW
EBI_CS
G28
22 R127
K23
22
G25
R140
NAND_DATA[0-7]
+3.3V_NORMAL
4.7K
4.7K
+3.3V_NORMAL
R193
R194
+3.3V_NORMAL
GPIO_02
EBI_ADDR1
GPIO_03
EBI_ADDR0
GPIO_04
EBI_ADDR5
GPIO_05
EBI_ADDR6
GPIO_06
EBI_ADDR8
GPIO_07
EBI_ADDR9
GPIO_08
EBI_ADDR13
GPIO_09
EBI_ADDR12
GPIO_10
EBI_ADDR11
GPIO_11
EBI_ADDR10
GPIO_12
EBI_ADDR7
GPIO_13
EBI_TAB
GPIO_14
EBI_WE1B
GPIO_15
EBI_CLK_IN
GPIO_16
EBI_CLK_OUT
GPIO_17
EBI_RWB
GPIO_18
EBI_CS0B
GPIO_19
T26
NAND_DATA[2]
T27
NAND_DATA[3]
U26
NAND_DATA[4]
U27
NAND_DATA[5]
V26
NAND_DATA[6]
V27
NAND_DATA[7]
V28
NAND_CEb
T24
NAND_ALE
R23
NAND_REb
T23
NAND_CLE
T25
NAND_WEb
R24
NAND_RBb
U25
NAND_DATA0
GPIO_22
NAND_DATA1
GPIO_23
NAND_DATA2
GPIO_24
NAND_DATA3
GPIO_25
NAND_DATA4
GPIO_26
NAND_DATA5
GPIO_27
NAND_DATA6
GPIO_28
NAND_DATA7
GPIO_29
NAND_CS0B
GPIO_30
NAND_ALE
GPIO_31
NAND_REB
GPIO_32
NAND_CLE
GPIO_33
NAND_WEB
GPIO_34
NAND_RBB
4.7K
R1025
C103
0.1uF
IC102
M24M01-HRMN6TP
U23
V23
V24
NC
R1032
0
E1
E2
VSS
1
8
2
7
3
A8’h
4
6
5
VCC
GPIO_38
SF_MOSI
GPIO_39
SF_SCK
GPIO_40
SF_CSB
GPIO_41
SDA
R1028
C171
8pF
OPT
22
22
R25
CI_MOD_RESET
MODEL_OPT_0
N27
P23
1K
R199
12K
HDMI_HPD_1 IR_IN
1K
R106
AE19
R1048
100
M4
R109
100
M5
R110
100
17page : Motion Remocon
56
AUD_MASTER_CLK
R105
HDMI_HPD_2 IR_IN
M23
AD19
DD
DD
AH18
A_DIM
R1041
5V_HDMI_1
BB Add.
EPHY_ACTIVITY
EPHY_LINK
L23
Y27
For LEX8(ALEF)
C173
22uF
16V
SIDE_AV_DET
HDMI_HPD_4
BT_RESET
M_REMOTE_TX 17page : Motion Remocon
M_REMOTE_RX 17page : Motion Remocon
L/R_SYNC
G2
EMI
C180
100pF
50V
For CI
/CI_CD1
Y28
R1063
0
TUNER_RESET
G5
R107
100
G6
R108
100
L24
0
5V_HDMI_2
R1033
22
L5
R1046
22
R115
HP_DET
5V_HDMI_4
/CI_IREQ
MODEL_OPT_6
K1
WIRELESS_DL_RX
MODEL_OPT_3
L27
M_REMOTE_RX
M_REMOTE_TX
M26
N23
R132
22
R28
R1050
100
R27
FE_TS_VAL_ERR
R133
USB_PWRFLT3
5V_HDMI_4
MODEL_OPT_2
SCART1_DET
P28
P27
SIDE_COMP_DET
R103
K6
K5
22
P26
M3
100
22
M2
22
0
R129
M_RFModule_RESET
RGB_DDC_SCL
R160
FRC_RESET
R102
L4
COMP1_DET
22
R1051
LOCAL DIMMING
L6
R1052 +3.3V_NORMAL
4.7K
+3.3V_NORMAL
RGB_DDC_SDA
R1049
M1
GPIO_57
WIRELESS_DL_TX
External Demod.
5V_HDMI_3
100 NON_LEX8
22
R161
R26
GPIO_56
SIDE_COMP_DET
For CI
CI_OUTCLK
/CI_CD2
K4
GPIO_55
HP_DET
1.8K
REAR_AV_DET
R1044
P25
E_TCK
DTV_ATV_SELECT
G4
GPIO_53
/RST_HUB
SIDE_COMP_DET
G3
GPIO_54
LG5111_RESET
HP_DET
LG5111_RESET
W27
SGPIO_00
SCL0_3.3V
W28
SGPIO_01
SDA0_3.3V
W26
SGPIO_02
SCL1_3.3V
W25
SGPIO_03
SDA1_3.3V
J2
SGPIO_04
SCL2_3.3V
J1
SGPIO_05
SDA2_3.3V
K3
SGPIO_06
SCL3_3.3V
K2
SDA3_3.3V
SGPIO_07
* NAND FLASH MEMORY 4Gbit (512M for BB)
Boot Strap
SC_RE2
22
R111
N28
GPIO_52
* I2C_3 :
BCM_RX
BCM_TX
SC_RE1
AA25
GPIO_51
* I2C_2 :
/RST_HUB
M27
GPIO_50
* I2C_1 :
+3.3V_NORMAL
Y26
GPIO_49
* I2C_0 :
2.7K
DSUB_DET
BT_RESET
Y25
GPIO_48
* I2C MAP
R1053
MODEL_OPT_1
L2
GPIO_47
SDA3_3.3V
HDMI_HPD_3
L3
GPIO_46
C167
8pF
OPT
PWM_DIM
22
L1
GPIO_45
SCL3_3.3V
R1042
1K
R1029
AA26
GPIO_44
R1026
USB_PWRFLT3
AA27
AA28
For CI
HDMI_HPD_4
K25
GPIO_43
SCL
CI_5V_CTL
NON_LEX8R114
1K
K26
GPIO_42
WP
MODEL_OPT_4
SIDE_AV_DET
K24
GPIO_37
PWM0 : GPIO_24
PWM1 : GPIO_09
17page : Motion Remocon
DC
MODEL_OPT_5
K28
GPIO_35
SF_MISO
ERROR_OUT
K27
GPIO_36
W24
INTERRUPT PIN
INTERRUPT PIN
INTERRUPT PIN
POWER_DET
DC
R192
L25
GPIO_21
U24
NAND_DATA[0]
0
N25
GPIO_20
NAND_DATA[1]
NVRAM
EBI_ADDR2
GPIO_23
GPIO_25
GPIO_29
GPIO_26
OPT R1047
0
L26
:
:
:
:
4.7K
R170
/CI_WAIT
EBI_WE
CI_A[0]
GPIO_01
1.2K
R176
EBI_CS
H24
GPIO_00
EBI_ADDR4
1.2K
R177
SYS_RESETb
CI_A[1]
N26
EBI_ADDR3
1.2K
R180
0
H25
1.2K
R183
R1030
J24
1.2K
R184
R1045
4.7K
J23
CI_A[4]
CI_A[2]
1.2K
R187
R1027
10K
+3.3V_NORMAL
CI_A[3]
4.7K
R171
GAS9
MDS62110204
GAS8
GAS7
MDS62110204
GAS6
MDS62110204
MDS62110204
+3.3V_NORMAL
SOC_RESET
IR_INT
IR1_IN
IR2_IN
IR_OUT
IC100
LGE3556CP (C0 3D PIP)
CI_A[0-13]
OPT
GAS5
MDS62110204
GAS4
GAS3
MDS62110204
GAS2
MDS62110204
OPT
GAS1
MDS62110204
MDS62110204
SMD GASKET
RESET
Default Res. of all NAND pin is Pull-down
+3.3V_NORMAL
+3.3V_NORMAL
2.7K
MODEL OPTION
OPT R1008
2.7K
R1005
2.7K
NAND_IO[1] : NAND Block 0 Write (DNS)
0 : Enable Block 0 Write
1 : Disable Block 0 Write
AL
NAND_ALE
W
NAND_WEb
NAND_IO[3:2] : NAND ECC (1, DNS)
00 : No ECC
01 : 1 ECC Bit
10 : 4 ECC Bit
11 : 8 ECC Bit
+3.3V_NORMAL
4.7K
R136
NC_11
NC_12
NAND_IO[4] : CPU Endian (0)
0 : Little Endian
1 : Big Endian
NC_13
NC_14
C
NAND_IO[6:5] : Xtal Bias Control (1, DNS)
00 : 1.2mA (Fundmental Recommand)
01 : 1.8mA
10 : 2.4mA (3rd over tune Recommand)
11 : 3.0mA
NAND_IO[7] : MIPS Frequency (DNS)
0 : 405MHz
1 : 378MHz
WP
FLASH_WP
Q101
KRC103S
B
E
NC_15
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
NON_URSA3
URSA3
MODEL_OPT_1
AA26
MAIN_MINI_LVDS
MAIN_LVDS
R26
DDR-512M
DDR-236M
MODEL_OPT_3
K1
FHD
MODEL_OPT_4
L25
FRC
MODEL_OPT_5
K27
GIP
NON-GIP
MODEL_OPT_6
K4
OLED
NON_OLED
NAND_DATA[4]
*MODEL_OPT_0 & MODEL_OPT_4
REFER TO THIS OPTION
MODEL_OPT_0 MODEL_OPT_4
NC_24
+3.3V_NORMAL
NC_23
C136
10uF
10V
VDD_2
VSS_2
C115
0.1uF
NC_22
NC_21
+3.3V_NORMAL
NC_20
I/O3
NAND_DATA[3]
I/O2
NAND_DATA[2]
I/O1
NAND_DATA[1]
I/O0
NAND_DATA[0]
NC_19
IF_AGC_SEL
LNA2_CTL/BOSTER_CTL
RF_SWITCH_CTL
R1012
100
R1019
100
R1024
100
R1061
E_TMS
/CI_SEL
LOW
URSA3 Internal
HIGH
HIGH
URSA3 External
LOW
HIGH
PWIZ Pannel T-con
with LG FRC
CHINA
MODEL_OPT_1
MODEL_OPT_2
0
MODEL_OPT_3
EU
43page:/BT_ON_OFF
MODEL_OPT_3
MODEL_OPT_5
R130
LOW
HIGH
For LEX8(ALEF)
MODEL_OPT_4
NC_17
NO FRC
LOW
MODEL_OPT_0
NC_18
NC_16
HD
NON_FRC
1K
39
11
LOW
HIGH
MODEL_OPT_2
FRC
R1020
CL
10
N28
22
MODEL_OPT_4
15page:/TW_9910_RESET
MODEL_OPT_5
15page:/CHB_RESET
26page:USB_PWRON3
MODEL_OPT_6
NO_FRC
R1018
1K
NC_10
NAND_CLE
40
NC_25
MINI_LVDS/NO LOCAL_D
R1011
1K
NAND_IO[0] : Flash Select (1)
0 : Boot From Serial Flash
1 : Boot From NAND Flash
9
NAND_DATA[5]
I/O4
LVDS/LOCAL_D
R1014
1K
NC_9
41
NAND_DATA[6]
I/O5
1K
VSS_1
42
NAND_DATA[7]
I/O6
DDR_512MB
R1022
1K
R1001
2.7K
7
8
I/O7
FHD
R1017
2.7K
NAND_CLE
VDD_1
43
1K
C114
0.1uF
NC_8
44
HD
R156
2.7K
5
6
NAND_DATA[0-7]
NC_26
C179
0.1uF
50V
DDR_256MB
R1015
1K
NC_7
C116
4700pF
2.7K
45
C178
0.1uF
50V
R1021
NAND_CEb
R1038
2.7K
4
NC_27
1K
E
46
EXTERNEL FRC/T_CON FRC
R1013
1K
R157 OPT
R
NAND_REb
47
NC_28
1K
R158 OPT
NAND_RBb
OPT R1007
2.7K
RB
Open Drain
2
3
MODEL_OPT_0
NC_29
GIP
R1009
R1006OPT
2.7K
NC_5
NC_6
R1035
2.7K
2.7K
NAND_DATA[6]
NAND_ALE
R1003
2.7K
R1002
OPT 2.7K
R1034
NAND_DATA[7]
NC_4
48
NON_GIP
R1023
1K
NAND_DATA[5]
R1037OPT
2.7K
NC_3
NAND FLASH
OLED
R118
NAND_DATA[4]
OPT R1004
2.7K
1
NON_OLED
R119
1K
2.7K
NAND_DATA[3]
NC_2
PIN NO.
PIN NAME
+12V
NC_1
R169
2.7K
2.7K
R1039
NAND_DATA[0-7]
R1040
OPT 2.7K
NAND_DATA[2]
NO FRC/INTERNER FRC
R1010
1K
NAND_DATA[1]
FOR ESD 12V Pattern
IC101
NAND04GW3B2DN6E
2.7K
R1036
OPT 2.7K
R191
NAND_DATA[0]
R134
R1000
NAND_DATA[0-7]
NAND_ALE : I2C Level (DNS)
0 : 3.3V Switching
1 : 5V Switching
NAND_CLE
0 : Enable D2CDIFF AC (DNS)
1 : Disabe D2CDIFF AC
BT_RESET
MODEL_OPT_2
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R1064
0
R1062
0
E_TDO
E_TDI
BCM (EUROBBTV)
BCM3556 & NAND FLASH
2009.06.18
1
LGE Internal Use Only
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
IC100
LGE3556CP (C0 3D PIP)
D23
B28
B27
A27
F24
F23
E25
A2.5V
C28
LVDS_TX_1_DATA2_P
POD2CHIP_MISTRT
LVDS_TX_1_DATA2_N
POD2CHIP_MIVAL
LVDS_TX_1_DATA3_P
CHIP2POD_MCLKO
LVDS_TX_1_DATA3_N
CHIP2POD_MDO0
LVDS_TX_1_DATA4_P
CHIP2POD_MDO1
LVDS_TX_1_DATA4_N
CHIP2POD_MDO2
LVDS_TX_1_CLK_P
CHIP2POD_MDO3
LVDS_TX_1_CLK_N
CHIP2POD_MDO4
LVDS_PLL_VREG
CHIP2POD_MDO5
LVDS_TX_AVDDC1P2
CHIP2POD_MDO6
LVDS_TX_AVDD2P5_1
CHIP2POD_MDO7
LVDS_TX_AVDD2P5_2
CHIP2POD_MOSTRT
LVDS_TX_AVSS_1
CHIP2POD_MOVAL
LVDS_TX_AVSS_2
LVDS_TX_AVSS_3
LVDS_TX_AVSS_4
AC18
AF20
0.1uF
AG21
C223
0.1uF
C219
0.1uF
C214
BROAD BAND STUDIO
C212
4.7uF
AG20
VDAC_AVDD2P5
LVDS_TX_AVSS_5
VDAC_AVDD1P2
LVDS_TX_AVSS_6
VDAC_AVDD3P3_1
LVDS_TX_AVSS_7
VDAC_AVDD3P3_2
LVDS_TX_AVSS_8
LVDS_TX_AVSS_9
LVDS_TX_AVSS_10
AF19
AD20
R220 : BCM recommened resistor 562 ohm
+3.3V_NORMAL
R220
P200
C215
0.1uF
TJC2508-4A
AH20
1%
C213
0.01uF
75
R238
R201
1.5K
R200
1.5K
AG19
C2028
4.7uF
1
AE20
560AH22
VDAC_AVSS_1
VDAC_AVSS_3
CLK54_AVDD1P2
VDAC_1
CLK54_AVDD2P5
VDAC_2
CLK54_AVSS
CLK54_XTAL_N
VDAC_VREG
CLK54_XTAL_P
CLK54_MONITOR
VCXO_AGND_2
R6
R7
T7
A2.5V
T8
R3
U3
L200
BLM18PG121SN1D
T4
T3
R4
V1
0.1uF
0.1uF
0.1uF
R209
3.9K
C201
100pF
4.7uF
Route INCM between associated
left and right signals of same channel
0.1uF
U4
V2
U1
SIDE_USB_DM
U2
SIDE_USB_DP
C209
C207
C208
R210
120
C203
C202
D3.3V
The INCM trace ends at the
same point where the connector
ground connects to the board ground
(thru-hole connector pin).
T5
R5
R235
Place test points, resistors
near audio connector.
Connect the other side of
the resistor to GND as close
as possible to the ground
connection of the associated
audio connector.
R266
R1
2.7K
R2
T2
2.7K
T1
USB_AVSS_1
VCXO_AGND_3
USB_AVSS_2
VCXO_AVDD1P2
USB_AVSS_3
VCXO_PLL_AUDIO_TESTOUT
1K R219
P5
P3
A2.5V
A1.2V
BLM18PG121SN1D
L209
BLM18PG121SN1D
P2
EPHY_TDN
EPHY_TDP
N2
N3
P1
P4
BLM18PG121SN1D
N4
N1
C2018
4.7uF
C2020
0.1uF
L210
C2021
4.7uF
C244
0.1uF
16V
C2026
4.7uF
C247
0.1uF
L212
N5
P7
USB_AVDD1P2PLL
USB_AVDD2P5
USB_AVDD2P5REF
RESET_OUTB
RESETB
NMIB
TMODE_0
USB_AVDD3P3
TMODE_1
USB_RREF
TMODE_2
USB_DM1
TMODE_3
USB_DP1
SPI_S_MISO
USB_DM2
POR_OTP_VDD2P5
USB_DP2
POR_VDD1P2
USB_MONCDR
041:B5
REAR_AV_L_IN
041:B5
REAR_AV_R_IN
R214
COMP1_R_IN
51
C210
0.015uF
AD7
AF6
NON_LEX8
C211
0.015uF
AH4
COMP1_R_IN
R228
51
NON_LEX8
C232
0.015uF
NON_LEX8
AG5
COMP1_LR_INCM
041:B5
SC1_L_IN
SC1_R_IN
002:J7
SC1_LR_INCM
041:B5
SIDE_AV_L_IN
SIDE_AV_R_IN
002:J6 SIDE_AV_LR_INCM
009:I3
PC_L_IN
009:I3
SIDE_AV_L_IN
AE6
NON_LEX8
R215
51
041:B5
COMP1_L_IN
0.015uF
002:J6 REAR_AV_LR_INCM
COMP1_L_IN
002:J6
041:B5
For LEX8(ALEF)
C206
002:J7
PC_R_IN
AG4
R229
51
C220
0.015uF
AG6
R230
51
C221
0.015uF
AF7
AE7
NON_LEX8
C224
0.015uF
AH5
0.015uF
R232
51 C225
NON_LEX8
NON_LEX8
AG7
R233
51
C226
0.015uF
AD8
R234
51
C227
0.015uF
AF8
NON_LEX8
R231
51
AH6
AE8
PC_LR_INCM
AH7
SIDE_AV_R_IN
AH8
AG8
COMP1_L_IN
AF5
COMP1_R_IN
0.047uF
C256
0.047uF
0.047uF
0.047uF
C254
C253
C252
0.047uF
0.047uF
C299
C298
0.047uF
0.047uF
C296
C279
0.047uF
C277
C2027 0.047uF
0
R265
AUDIO IN CAP Replacement of MLCC
R264
0
AB9
AA10
AB10
AA11
C222
0.1uF
AB11
AC8
AE5
PLACE NEAR BCM CHIP
C1
F3
C4
A5
E5
Near Q1705
C258
0.1uF
C2019
0.1uF
C261
0.1uF
TU_CVBS_INCM
003:A3
Run Along TUNER_CVBS_IF_P Trace
E6
D7
E7
F7
G7
SC1_RGB_INCM
003:A4
Near J1500
A1.2V
H7
Run Along SC1_R,SC_G,SC_B Trace
A2.5V
AD28
AD26
AC26
AC27
54MHz_XTAL_N
002:I1
54MHz_XTAL_P
002:I2
AE25
REAR_AV_CVBS_INCM
003:A3
Y23
Near J1603
A1.2V
C262
AC24
AF24
C235
4.7uF
C233
0.1uF
COMP1_VID_INCM
NON_LEX8
L203
BLM18PG121SN1D
AF25
0.1uF
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
AB24
F6
V25
AH3
C2015
0.1uF
C2016
0.1uF
C264
0.1uF
R_VID_INCM
003:A5
Run Along DSUB_R Trace
A2.5V
J4
J3
Near P1600
R221
J5
J6
SYS_RESETb
001:A6;001:B7
4.7K
N24
L211
BLM18PG121SN1D
C231
10uF
G_VID_INCM
003:A5
Run Along DSUB_G Trace
A1.2V
C234
0.1uF
Run Along DSUB_B Trace
AB8
+3.3V_NORMAL
B_VID_INCM
003:A5
H4
USB_MONPLL
EJTAG_TCK
USB_PWRFLT_1
EJTAG_TDI
USB_PWRFLT_2
EJTAG_TDO
USB_PWRON_1
EJTAG_TMS
USB_PWRON_2
EJTAG_TRSTB
H3
OPT
R224
2.7K
H2
H1
OPT
R225
2.7K
1K R249
G1
C2011
H6
Near J1500
0.1uF
SC1_CVBS_INCM 003:A3
Run Along SC1_CVBS_IN Trace
H5
EJTAG_CE1
EPHY_VREF
EPHY_RDAC
A1.2V
L204
BLM18PG121SN1D
AB26
EPHY_RDN
PLL_MAIN_AVDD1P2
EPHY_RDP
PLL_MAIN_AGND
EPHY_TDN
PLL_MAIN_MIPS_EREF_TESTOUT
EPHY_TDP
PLL_RAP_AVD_TESTOUT
EPHY_AVDD1P2
PLL_RAP_AVD_AVDD1P2
EPHY_AVDD2P5
PLL_RAP_AVD_AGND
EPHY_AGND_1
EPHY_AGND_2
2.7K
R227
2.7K
AB27
M6
N6
R240
A1.2V
L207
BLM18PG121SN1D
390
OPT
C2023
Near J1501
BYP_DS_CLK
0.1uF
SIDE_AV_CVBS_INCM 003:A3
NON_LEX8
Run Along SC2_CVBS_IN Trace
N7
AA24
BYP_CPU_CLK
BYP_SYS175_CLK
AUDMX_LEFT1
R226
AC25
EPHY_PLL_VDD1P2
EPHY_AGND_3
51
VIDEO INCM
F2
P24
USB_AVDD1P2
BYP_SYS216_CLK
R204
013:E7;035:AK13
F4
+3.3V_NORMAL
USB_AVSS_5
P6
EPHY_RDN
EPHY_RDP
LVDS_TX_0_CLK_P
OPT
C228
10uF
A1.2V A2.5V
USB_AVSS_4
EJTAG_CE0
R218
240
D4
AA23
VCXO_AGND_1
T6
LVDS_TX_0_DATA0_P013:E7;035:AK11
LVDS_TX_0_CLK_N 013:E7;035:AK13
D3
F1
12pF
C229
LVDS_TX_0_DATA0_N013:E7;035:AK11
E4
F5
22
R211
LVDS_TX_0_DATA1_P013:E7;035:AK11
E3
BSC_S_SCL
BSC_S_SDA
A1.2V
LVDS_TX_0_DATA1_N013:E7;035:AK12
E2
PM_OVERRIDE
3
A3.3V
LVDS_TX_0_DATA2_P013:F7;035:AK12
E1
AD27
VDAC_RBIAS
M25
4
LVDS_TX_0_DATA2_N013:F7;035:AK12
D2
VDAC_AVSS_2
AH21
M24
LVDS_TX_0_DATA3_P013:F7;035:AK14
D1
LVDS_TX_AVSS_11
DTV/MNT_V_OUT
2
LVDS_TX_0_DATA3_N013:F7;035:AK14
C3
2
LVDS_TX_1_DATA1_N
POD2CHIP_MDI7
54MHz_XTAL_P
LVDS_TX_0_DATA4_P013:F7;035:AK14
C2
3
POD2CHIP_MDI6
54MHz_XTAL_N
013:E7;035:AK18
LVDS_TX_0_DATA4_N013:F7;035:AK15
B2
X903
54MHz
LVDS_TX_1_DATA1_P
LVDS_TX_1_CLK_P
B1
1
LVDS_TX_1_DATA0_N
POD2CHIP_MDI5
C257
POD2CHIP_MDI4
0
L202
BLM18PG121SN1D
R237
R236
0
A28
LVDS_TX_1_DATA0_P
R250
34
C26
POD2CHIP_MDI3
LVDS_TX_1_DATA0_P013:E7;035:AK16
LVDS_TX_1_CLK_N 013:E7;035:AK18
R251
34
C27
LVDS_TX_0_CLK_N
R248
34
F25
POD2CHIP_MDI2
LVDS_TX_1_DATA0_N013:E7;035:AK16
B5
R244
34
E24
LVDS_TX_0_CLK_P
C5
R245
34
NON_LEX8
E23
CI_OUTVALID
POD2CHIP_MDI1
LVDS_TX_1_DATA1_P013:E7;035:AK16
D6
R247
34
CI_OUTSTART
LVDS_TX_0_DATA4_N
R246
34
CI_OUTDATA[6] D27
CI_OUTDATA[7] D26
POD2CHIP_MDI0
LVDS_TX_1_DATA1_N013:E7;035:AK17
D5
R260
34
CI_OUTDATA[4] E26
CI_OUTDATA[5] D28
LVDS_TX_0_DATA4_P
A2
R261
34
NON_LEX8
CI_OUTDATA[2] C25
CI_OUTDATA[3] E27
POD2CHIP_MCLKI
LVDS_TX_1_DATA2_P013:E7;035:AK17
A1
4.7uF
CI_OUTDATA[0] D25
CI_OUTDATA[1] D24
A3.3V A1.2V
LVDS_TX_0_DATA3_N
G23
LVDS_TX_1_DATA2_N013:E7;035:AK17
L208
LVDS_TX_0_DATA2_N
LVDS_TX_0_DATA3_P
CI_A[14]
C230
12pF
22
R212
LVDS_TX_1_DATA3_P013:E7;035:AK19
1008LS-272XJLC 33pF
RMX0_SYNC
CI_OUTDATA[0-7],CI_OUTSTART,CI_OUTVALID
045:V14
LVDS_TX_1_DATA3_N013:E7;035:AK19
A3
R243
604
LVDS_TX_0_DATA2_P
B3
0.1uF
RMX0_DATA
LVDS_TX_1_DATA4_P013:E7;035:AK19
B6
0.1uF
C240
TP4023
LVDS_TX_0_DATA1_N
C6
C251
A26
RMX0_CLK
LVDS_TX_1_DATA4_N013:E7;035:AK20
A4
C237
TP4022
LVDS_TX_0_DATA1_P
4.7uF
B25
PKT0_SYNC
C236
0.1uF
TP4021
LVDS_TX_0_DATA0_N
C239
0.1uF
C242
4.7uF
C295
0.1uF
C2013
4.7uF
A25
LVDS_TX_0_DATA0_P
PKT0_DATA
C2012
0.1uF
FE_TS_SYNC
When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF
B4
PKT0_CLK
C241
B26
0.1uF
C24
C238
FE_TS_DATA_CLK
FE_TS_SERIAL
54MHz X-TAL
Y24
AE24
1K
R222
AD25
1K
R262
TP is Necessory
AUDIO INCM
AUDMX_RIGHT1
AUDMX_INCM1
PLACE NEAR BCM CHIP
AUDMX_LEFT2
AUDMX_RIGHT2
AUDMX_INCM2
PLACE NEAR Jacks
AUDMX_LEFT3
5.1
NON_LEX8
AUDMX_RIGHT3
AUDMX_INCM3
Near J1501
R256
Route Between SC2_L_IN & SC2_R_IN
AUDMX_LEFT4
0.15uF
C2014
AUDMX_RIGHT4
AUDMX_INCM4
5.1
AUDMX_LEFT5
AUDMX_RIGHT5
SIDE_AV_LR_INCM
002:C6
0.47uF
C271
NON_LEX8
Near J1600
AUDMX_INCM5
REAR_AV_LR_INCM
R258
Route Between AV1_L_IN & AV1_R_IN
AUDMX_LEFT6
0.15uF
C2024
002:C6
0.47uF
C2017
AUDMX_RIGHT6
AUDMX_INCM6
AUDMX_AVSS_1
5.1
AUDMX_AVSS_2
AUDMX_AVSS_3
AUDMX_AVSS_4
Near J1603
R259
Route Between COMP1_L_IN & COMP1_R_IN
AUDMX_AVSS_5
AUDMX_AVSS_6
0.15uF
C265
NON_LEX8
COMP1_LR_INCM
002:C6
C2025
0.47uF
NON_LEX8
AUDMX_LDO_CAP
AUDMX_AVDD2P5
5.1
C232-*1
C225-*1
C206-*1 C210-*1
C226-*1
C224-*1
C211-*1
C221-*1
C220-*1
C227-*1
0.015uF
0.015uF
0.015uF
0.015uF 0.015uF
0.015uF
0.015uF
0.015uF
0.015uF
0.015uF
50V
50V
50V
50V
50V
50V
50V
50V
50V
50V
15nF_U2J 15nF_U2J 15nF_U2J 15nF_U2J 15nF_U2J 15nF_U2J 15nF_U2J
15nF_U2J 15nF_U2J 15nF_U2J
C279-*1
C2027-*1 C277-*1
C298-*1
C253-*1 C254-*1
C296-*1
C299-*1
C252-*1
C256-*1
0.047uF
0.047uF 0.047uF
0.047uF
0.047uF 0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
350V
350V
350V
350V
350V
350V
350V
350V
350V
350V
47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T 47nF_X7T
Near J1500
R257
Route Between SC1_L_IN & SC1_R_IN
0.15uF
C2022
A2.5V
C217
10uF
SC1_LR_INCM
002:C6
0.47uF
C270
5.1
Near J1602
R252
Route Between PC_L_IN & PC_R_IN
0.15uF
C269
PC_LR_INCM
002:C6
0.47uF
C2010
Near Q1704
TU_SIF_INCM
Route Along With TUNER_SIF_IF_N
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BCM (EUROBBTV)
BCM3556 AUD_IN/LVDS
003:A3
2009.06.18
2
LGE Internal Use Only
D1.2V
Place here for common circuit with ATSC
+1.8V_AMP
+1.8V_HDMI
+3.3V_NORMAL
L111
BLM18PG121SN1D
D3.3V
D1.2V
A3.3V
L112
CIC21J501NE
C243
0.1uF
C249
4.7uF
C381
0.1uF
C382
0.01uF
C250
1000pF
C380
10uF
C379
10uF
C383
1000pF
C287
100uF
C286
33uF
C246
0.01uF
C378
0.1uF
C376
4.7uF
C374
0.01uF
C259
1000pF
C366
0.1uF
C266
4.7uF
C288
1000pF
C245
4.7uF
C290
0.01uF
C255
1000pF
C377
0.01uF
C375
0.1uF
C263
4.7uF
C267
0.01uF
C373
1000pF
C289
0.1uF
FOR ESD
C2008
0.1uF
16V
C2007
0.1uF
16V
D3.3V
AG28
AG27
AE26
TU_IF_N_1
TU_IF_P_1
AE28
C172
4.7uF
TU_IF_N_1
C113
0.1uF
L103
TU_IF_P_1
BLM18PG121SN1D
C119
0.1uF
A1.2V
A1.2V
AE27
AD24
C144
0.1uF
AB19
AB25
C122
4.7uF
EDSAFE_AVSS_2
I2S_DATA_OUT
EDSAFE_AVSS_3
I2S_LR_IN
EDSAFE_AVSS_4
I2S_LR_OUT
EDSAFE_AVSS_5
AUD_LEFT0_N
EDSAFE_AVDD2P5
AUD_LEFT0_P
EDSAFE_DVDD1P2
AUD_AVDD2P5_0
EDSAFE_IF_N
AUD_AVSS_0_1
EDSAFE_IF_P
AUD_AVSS_0_2
PLL_DS_AGND
AUD_AVSS_0_3
PLL_DS_AVDD1P2
AUD_AVSS_0_4
PLL_DS_TESTOUT
AUD_AVSS_0_5
AUD_RIGHT0_N
A2.5V
AUD_RIGHT0_P
AB18
C112
0.1uF
C111
0.1uF
BLM18PG121SN1D
AC17
L104 C120
1000pF
BLM18PG121SN1D
AB17
L105
C117
1000pF
C123
0.01uF
AD14
AD16
AB15
AC15
AD13
C118
0.01uF
AE13
AC13
DSUB
AB14
DSUB_R
R_VID_INCM
DSUB_G
AC12
G_VID_INCM
DSUB_B
AB13
B_VID_INCM
AC11
10
AD11
AD12
AA14
C101 47pF
COMP1_Pr
AB12
R138
SC1_G
0.1uF
C128
0.1uF
C129
0.1uF
AD10
AE9
AF9
AH9
AG9
R138-*1 10 NON_EU
SC1_RGB(EU)
C127
AC10
1%
1%
R312 75
1%
R120 82
C104 OPT
R131 75
COMP1_Pb
COMP1_VID_INCM
C169 47pF
1%
C17047pF
R195
AC14
1%
0 EU
C130
0.1uF
AG15
C131
0.1uF
AE15
C132
0.1uF
AF15
AH15
SC1_RGB_INCM
C134
0.1uF
AF16
C135
0.1uF
AH17
NON_EU
1%
1%
NON_EU
R313
OPT 1%
R135
75
SIDE COMPONENT
75
C133
0.1uF
C105 OPT
NON_EU
R315
75
SC1_R
SC1_B
ONLY USE NON_EU
FOR COMP 1
R135-*1
AH16
82 1%
C174
0.1uF
AG14
C175
0.1uF
AE14
C176
R196
10
SIDE_COMP_Y
0.1uF
AH10
AG10
1%
1%
R166 75
R167 75
1%
R165 82
SIDE_COMP_Y
C177 OPT
SIDE_COMP_Pb
SIDE_COMP_INCM
R100
R142
R143
R141
SIDE_COMP_Pb
SIDE_COMP_INCM
EU
R2112
TU_CVBS
1%
REAR_AV_CVBS
NON_EU
R2112-*1
5%
SIDE_COMP_Pr
CVBS
18
5%
12
AE10
NON_EU
R141-*1
AE11
AF11
62
AH11
62
OPT
62
75 1% EU
AH13
AE12
AF12
C110
R2113
12
SC1_CVBS_IN
R2114
R2115
0
SIDE_AV_CVBS
AD9
0.1uF
AG11
C125
0.1uF
AG12
C100
0.1uF
AF13
AC9
12
AF10
A2.5V
SC1_CVBS_INCM
AH12
A2.5V
AG13
R4020
10K
R137
10K
0.1uF
C106
R128
0
AG17
AD15
A1.2V
SC1_ID
OPT
L106
BLM18PG121SN1D
R3055
240
SIDE_AV_CVBS
R139
12K
C121
0.1uF
C140
4.7uF
AE16
AE17
AB16
AA15
AC16
AG3
12K
R4021
120
R3056
TU_SIF_INCM
OPT
AUD_LEFT1_N
SD_V5_AVDD2P5
AUD_LEFT1_P
SD_V5_AVSS
AUD_RIGHT1_N
SD_V1_AVDD1P2
AUD_RIGHT1_P
SD_V1_AVDD2P5
AUD_AVDD2P5_1
SD_V1_AVSS_1
AUD_AVSS_1_1
SD_V1_AVSS_2
AUD_AVSS_1_2
SD_V2_AVDD1P2
AUD_AVSS_1_3
SD_V2_AVDD2P5
AUD_LEFT2_N
SD_V2_AVSS_1
AUD_LEFT2_P
SD_V2_AVSS_2
AUD_RIGHT2_N
SD_V2_AVSS_3
AUD_RIGHT2_P
SD_V3_AVDD1P2
AUD_AVDD2P5_2
SD_V3_AVDD2P5
AUD_AVSS_2_1
SD_V3_AVSS_1
AUD_AVSS_2_2
SD_V3_AVSS_2
C4020
0.1uF
AF4
AUD_SPDIF
SD_V4_AVDD1P2
SPDIF_AVDD2P5
SD_V4_AVDD2P5
SPDIF_AVSS
SD_V4_AVSS
SPDIF_IN_N
SD_R
SPDIF_IN_P
SD_G
HDMI_RX_0_CEC_DAT
SD_B
HDMI_RX_0_HTPLG_IN
SD_INCM_B
HDMI_RX_0_HTPLG_OUT
SD_Y1
HDMI_RX_0_DDC_SCL
SD_PR1
HDMI_RX_0_DDC_SDA
SD_PB1
HDMI_RX_0_RESREF
SD_INCM_COMP1
HDMI_RX_0_CLK_N
SD_Y2
HDMI_RX_0_CLK_P
SD_PR2
HDMI_RX_0_DATA0_N
SD_PB2
HDMI_RX_0_DATA0_P
SD_INCM_COMP2
HDMI_RX_0_DATA1_N
SD_Y3
HDMI_RX_0_DATA1_P
SD_PR3
HDMI_RX_0_DATA2_N
SD_PB3
HDMI_RX_0_DATA2_P
SD_INCM_COMP3
HDMI_RX_0_VDD3P3
SD_L1
HDMI_RX_0_VDD1P2
SD_C1
HDMI_RX_0_VDD2P5
SD_INCM_LC1
HDMI_RX_0_AVSS_1
SD_L2
HDMI_RX_0_AVSS_2
SD_C2
HDMI_RX_0_AVSS_3
SD_INCM_LC2
HDMI_RX_0_AVSS_4
SD_L3
HDMI_RX_0_AVSS_5
SD_C3
HDMI_RX_0_AVSS_6
SD_INCM_LC3
HDMI_RX_0_PLL_AVSS
SD_CVBS1
HDMI_RX_0_PLL_DVDD1P2
SD_CVBS2
HDMI_RX_0_PLL_DVSS
SD_INCM_CVBS1
HDMI_RX_1_CEC_DAT
SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN
SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT
HDMI_RX_1_DDC_SCL
SD_SIF1
HDMI_RX_1_DDC_SDA
SD_INCM_SIF1
HDMI_RX_1_RESREF
SD_FB
HDMI_RX_1_CLK_N
SD_FS
HDMI_RX_1_CLK_P
SD_FS2
HDMI_RX_1_DATA0_N
HDMI_RX_1_DATA0_P
PLL_VAFE_AVDD1P2
PLL_VAFE_AVSS HDMI_RX_1_DATA1_N
HDMI_RX_1_DATA1_P
PLL_VAFE_TESTOUT
RGB_HSYNC
HDMI_RX_1_DATA2_N
HDMI_RX_1_DATA2_P
HDMI_RX_1_VDD1P2
HDMI_RX_1_VDD2P5
HDMI_RX_1_AVSS_1
RGB_HSYNC
HDMI_RX_1_AVSS_2
RGB_VSYNC
HDMI_RX_1_AVSS_3
HDMI_RX_1_AVSS_4
HDMI_RX_1_AVSS_5
SC1_FB
HDMI_RX_1_AVSS_6
HDMI_RX_1_AVSS_7
OPT
HDMI_RX_1_AVSS_8
0
R2116
AUD_LRCK
HP_LOUT_N
AG26
AH26
HDMI_RX_1_AVSS_9
HDMI_RX_1_PLL_AVSS
HDMI_RX_1_PLL_DVDD1P2
HDMI_RX_1_PLL_DVSS
C370
0.1uF
C293
0.01uF
C294
0.1uF
C274
0.1uF
C272
0.1uF
C275
0.1uF
C276
0.1uF
C278
4.7uF
C280
4.7uF
C297
4.7uF
C2004
33uF
A2.5V
C147
0.01uF
AA20
AB21
C155
0.1uF
C162
10uF
AC22
AC23
D1.8V
For LEX8(ALEF)
AD23
AH25
AG25
HP_ROUT_N
HP_LOUT_N
HP_ROUT_P
HP_LOUT_P
AH23
AG23
AG24
BT_LOUT_N
HP_ROUT_N
BT_LOUT_P
HP_ROUT_P
C248
1000pF
BT_ROUT_N
AH24
D1.8V
C281
1000pF
C282
1000pF
C283
1000pF
C284
0.01uF
C285
0.01uF
C2005
0.01uF
C2006
0.01uF
BT_ROUT_P
AE22
C148
0.01uF
AB20
AC21
C156
0.1uF
C365
0.1uF
16V
C364
0.1uF
16V
C357
10uF
10V
C363
0.1uF
16V
C356
0.1uF
16V
C348
0.1uF
16V
C320
0.1uF
16V
C319
0.1uF
16V
C318
0.1uF
16V
C304
0.1uF
16V
C163
10uF
AE23
AF21
SCART1_Lout_N
AE21
SCART1_Lout_P
AF22
SCART1_Rout_N
AG22
SCART1_Rout_P
AD21
C149
0.01uF
AC20
AD22
C157
0.1uF
C164
10uF
AH2
SPDIF_OUT
AC6
AE4
C150
0.1uF
AF3
+5V_NORMAL
IC100
LGE3556CP (C0 3D PIP)
AH1
R2036
1K
D1.2V
AA6
AA5
R309
10K
AB3
0
R307
Y6
0
R308
AC4
499
IC100
LGE3556CP (C0 3D PIP)
HDMI_SDA
J8
C3006
0.1uF
16V
HDMI_CLK-
AC2
HDMI_CLK+
AD1
K8
L8
M8
HDMI_RX0-
AD2
N8
A3.3V
HDMI_RX0+
AE1
P8
HDMI_RX1-
AE2
R8
HDMI_RX1+
AF1
HDMI_RX2+
AD3
AA8
BLM18PG121SN1D
L109
HDMI_RX2-
AF2
A1.2V
H9
H10
A2.5V
AE3
H11
AC3
H12
H13
C160
0.1uF
C153
0.1uF
C145
4.7uF
H14
BLM18PG121SN1D
L107
AB6
H15
AG2
H16
AB4
H17
AA7
H18
Y8
H19
C151
0.01uF
C158
1000pF
AC5
C165
10uF
H21
J21
W8
K21
V4
U6
V5
D3.3V
L21
M21
N21
P21
R21
T21
V3
W4
W2
499
A3.3V
R153
U21
V21
OPT
W21
W3
R205
20
Y1
Y2
Y21
VDDC_2
M7
VDDC_3
AB7
VDDC_4
AC7
VDDC_5
G8
VDDC_6
D9
VDDC_7
AA9
VDDC_8
G10
VDDC_9
A11
VDDC_10
L11
VDDC_11
M11
VDDC_12
N11
VDDC_13
P11
VDDC_14
R11
VDDC_15
T11
VDDC_16
U11
VDDC_17
V11
VDDC_18
D12
VDDC_19
G12
VDDC_20
L12
VDDC_21
M12
VDDC_22
N12
VDDC_23
P12
VDDC_24
R12
VDDC_25
T12
VDDC_26
U12
VDDC_27
V12
VDDC_28
L13
VDDC_29
M13
VDDC_30
N13
VDDC_31
P13
VDDC_32
R13
VDDC_33
T13
V13
AH27
AB1
BLM18PG121SN1D
L110
Y3
A1.2V
AB2
A2.5V
C2003
0.1uF
L14
W5
AA18
W1
AA19
C154
0.1uF
E28
C161
0.1uF
U7
L28
U28
FOR ESD
AB28
V7
BLM18PG121SN1D
L108
W7
U8
V8
C384
33uF
10V
VDDO_2
P14
VDDO_3
R14
VDDO_4
T14
VDDO_5
U14
VDDO_6
V14
VDDO_7
L15
VDDO_8
M15
P15
A9
V6
G11
AA4
G13
C166
10uF
N14
N15
G9
C152
0.01uF
VDDO_1
D1.8V
Y5
C159
1000pF
M14
AA12
Y4
C146
4.7uF
G14
AGC_VDDO
D3.3V
AA13
Y7
L7
U13
AA1
W6
VDDC_1
A3.3V
AA2
U5
K7
H8
AC1
AB5
AD6
J7
HDMI_SCL
R152
AD4
AD5
A2.5V
A14
G15
A19
G19
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C292
1000pF
HP_LOUT_P
G17
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C369
4.7uF
AF23
AA3
HDMI_RX_1_VDD3P3
R2117
0
AG18
SD_CVBS3
SD_CVBS4
C371
0.01uF
AUD_LRCH
AD18
AG1
SD_INCM_G
RGB_VSYNC
CONNECT NEAR BCM CHIP
AH19
SD_INCM_R
SD_INCM_CVBS4
AF17
SIDE_AV_CVBS_INCM
TU_SIF
0.1uF
C124
TU_CVBS_INCM
REAR_AV_CVBS_INCM
For LEX8(ALEF)
AF14
AH14
1%
SIDE_COMP_Pr
AG16
SD_V5_AVDD1P2
C268
1000pF
AUD_SCK
AD17
R2035
0
AF28
C216
0.1uF
AF18
10K
AF27
I2S_DATA_IN
R2039
AF26
A1.2V
BLM18PG121SN1D
L102
I2S_CLK_OUT
EDSAFE_AVSS_1
10K
TU_IF_AGC_1
TU_IF_AGC_2
I2S_CLK_IN
DS_AGCT_CTL
10K
AB22
A2.5V
AE18
DS_AGCI_CTL
R310
AA21
R2038
AH28
TU_IF_AGC_2
R2037
OPT
10K
TU_IF_AGC_1
COMP1_Y
D1.8V
IC100
LGE3556CP (C0 3D PIP)
26page : TUNER(HALF NIM)
COMPONENT
C291
10uF
DDRV_1
R15
DDRV_2
T15
DDRV_3
U15
DDRV_4
V15
DDRV_5
A16
DDRV_6
G16
DDRV_7
L16
DDRV_8
M16
DDRV_9
N16
P16
DVSS_1
DVSS_62
DVSS_2
DVSS_63
DVSS_3
DVSS_64
DVSS_4
DVSS_65
DVSS_5
DVSS_66
DVSS_6
DVSS_67
DVSS_7
DVSS_68
DVSS_8
DVSS_69
DVSS_9
DVSS_70
DVSS_10
DVSS_71
DVSS_11
DVSS_72
DVSS_12
DVSS_73
DVSS_13
DVSS_74
DVSS_14
DVSS_75
DVSS_15
DVSS_76
DVSS_16
DVSS_77
DVSS_17
DVSS_78
DVSS_18
DVSS_79
DVSS_19
DVSS_80
DVSS_20
DVSS_81
DVSS_21
DVSS_82
DVSS_22
DVSS_83
DVSS_23
DVSS_84
DVSS_24
DVSS_85
DVSS_25
DVSS_86
DVSS_26
DVSS_87
DVSS_27
DVSS_88
DVSS_28
DVSS_89
DVSS_29
DVSS_90
DVSS_30
DVSS_91
DVSS_31
DVSS_92
DVSS_32
DVSS_93
DVSS_33
DVSS_94
DVSS_34
DVSS_95
DVSS_35
DVSS_96
DVSS_36
DVSS_97
DVSS_37
DVSS_98
DVSS_38
DVSS_99
DVSS_39
DVSS_100
DVSS_40
DVSS_101
DVSS_41
DVSS_102
DVSS_42
DVSS_103
DVSS_43
DVSS_104
DVSS_44
DVSS_105
DVSS_45
DVSS_106
DVSS_46
DVSS_107
DVSS_47
DVSS_108
DVSS_48
DVSS_109
DVSS_49
DVSS_110
DVSS_50
DVSS_111
DVSS_51
DVSS_112
DVSS_52
DVSS_113
DVSS_53
DVSS_114
DVSS_54
DVSS_115
DVSS_55
DVSS_116
DVSS_56
DVSS_117
R16
T16
U16
V16
AA16
D17
L17
M17
N17
P17
R17
T17
U17
V17
AA17
AC19
G18
L18
M18
N18
P18
R18
T18
U18
V18
D20
G20
H20
A21
E21
F21
G21
E22
F22
G22
H22
J22
K22
L22
M22
N22
P22
R22
T22
U22
V22
W22
Y22
AA22
W23
AB23
F28
M28
T28
AC28
DVSS_57
DVSS_58
DVSS_59
DVSS_60
DVSS_61
EUROBBTV
BCM3556 VIDEO IN
2009.06.18
3
LGE Internal Use Only
D1.8V
A1.2V
IC100
LGE3556CP (C0 3D PIP)
DDR01_A07
DDR01_A08
DDR01_A09
DDR01_A10
DDR01_A11
DDR01_A12
DDR01_A13
DDR1_A04
DDR1_A05
DDR1_A06
DDR01_BA0
DDR01_BA1
DDR01_BA2
DDR01_CASB
DDR0_DQ00
DDR0_DQ01
DDR0_DQ02
DDR0_DQ03
DDR0_DQ04
DDR0_DQ05
DDR0_DQ06
DDR0_DQ07
DDR0_DQ08
DDR0_DQ09
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR1_DQ00
DDR1_DQ01
DDR1_DQ02
DDR1_DQ03
DDR1_DQ04
DDR1_DQ05
DDR1_DQ06
DDR1_DQ07
DDR1_DQ08
DDR1_DQ09
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR0_DM0
DDR0_DM1
DDR1_DM0
DDR1_DM1
DDR0_DQS0
DDR0_DQS0B
DDR0_DQS1
DDR0_DQS1B
DDR1_DQS0
DDR1_DQS0B
DDR1_DQS1
DDR1_DQS1B
DDR01_RASB
DDR_VREF0
DDR_VREF1
DDR01_WEB
DDR_VDDP1P8_1
DDR01_A[0]
E14
DDR01_A[1]
A15
DDR01_A[2]
D15
DDR01_A[3]
E12
DDR0_A[5]
F13
DDR0_A[6]
C14
DDR01_A[7]
F14
DDR01_A[8]
B14
DDR01_A[9]
DDR01_A[11]
D13
DDR01_A[12]
B13
DDR01_A[13]
C15
DDR1_A[5]
D16
DDR1_A[6]
F8
F2
DDR01_RASb
F7
DDR01_CASb
G7
DDR01_WEb
F3
G8
G3
G1
DDR01_BA2
DDR0_A[4-6]
DDR1_A[4-6]
DDR01_A[1]
H3
DDR01_A[2]
H7
J3
DDR0_A[6]
J7
A17
DDR01_CASb
DDR01_A[7]
K2
DDR01_A[8]
K8
J8
A8
DDR0_DQ[0]
B11
DDR0_DQ[1]
DDR01_A[9]
K3
B8
DDR0_DQ[2]
DDR01_A[10]
H2
D11
DDR0_DQ[3]
DDR01_A[11]
DDR01_A[12]
K7
DDR0_DQ[9]
E9
DDR0_DQ[10]
F11
DDR0_DQ[11]
F12
DDR0_DQ[12]
E8
DDR0_DQ[13]
D10
DDR0_DQ[14]
F8
DDR0_DQ[0-7]
DDR0_DQ[4]
E10
DQ6
WE
DQ7
DDR01_A[13]
BA1
DQS
DM/RDQS
D1
DDR0_DQ[4]
D9
DDR0_DQ[5]
DDR01_RASb
F7
B1
DDR0_DQ[6]
DDR01_CASb
G7
DDR01_WEb
F3
B9
DQ1
CKE
DQ2
DQ3
DDR0_DQ[7]
G8
B7
DDR0_DQS0
004:A4
A8
DDR0_DQS0b
004:A4
B3
DDR0_DM0
DQ4
RAS
DQ5
CAS
DQ6
WE
DQ7
DDR1_DQ[0]
C2
DDR1_DQ[1]
D7
DDR1_DQ[5]
D3
DDR1_DQ[3]
DDR1_A[4-6]
DDR01_BA1
DDR1_A[6]
G3
A2
G1
DDR01_BA2
BA0
BA1
NC_1/BA2
D1
DDR1_DQ[4]
D9
DDR1_DQ[2]
R408
75
B1
DDR1_DQ[6]
DDR01_A[12] R409
75
B9
DDR1_DQ[7]
DDR0_A[4-6]
DDR01_CASb
DDR1_DQ[3]
C21
DDR1_DQ[4]
B18
DDR1_DQ[5]
B20
DDR1_DQ[6]
D18
E18
DDR1_DQ[7]
DDR1_DQ[8]
D21
DDR1_DQ[9]
F18
DDR1_DQ[10]
DQS
DDR1_DQ[12]
F17
DDR1_DQ[13]
B22
DDR1_DQ[14]
E17
DDR1_DQ[15]
DM/RDQS
B7
DDR1_DQS0
DDR1_DQS0b
004:A3
DDR01_A[11]
B3
DDR1_DM0
004:A4
DDR01_A[8]
DDR1_A[4]
004:A4
A2
L2
L8
A0
VDDQ_1
A1
VDDQ_2
A2
VDDQ_3
A3
VDDQ_4
A4
VDDQ_5
A5
VDD_1
A6
VDD_2
A7
A8
VDD_3
D1.8V
A10/AP
VSSQ_1
A11
VSSQ_2
A12
VSSQ_3
A13
VSSQ_4
NC_2/A14
NC_3/A15
VSS_2
VSS_3
H8
C1
DDR01_A[1]
H3
C3
DDR01_A[2]
H7
004:B6;004:F3;004:I7 DDR1_A[4-6]
C7
DDR01_A[3]
DDR1_A[4]
J2
A1
DDR1_A[5]
J3
L1
DDR1_A[6]
J7
E9
DDR01_A[7]
K2
H9
DDR01_A[8]
K8
C9
DDR01_A[9]
K3
A7
DDR01_A[10]
H2
B2
DDR01_A[11]
K7
DDR01_A[12]
L2
DDR01_A[13]
L8
B8
D2
D8
VREF
VDDL
A0
VDDQ_1
A1
VDDQ_2
A2
VDDQ_3
A3
VDDQ_4
A4
VDDQ_5
A5
VDD_1
A6
VDD_2
A7
VDD_3
A8
VSSQ_1
A11
VSSQ_2
A12
VSSQ_3
A13
VSSQ_4
L3
DDR0_VREF0
K9
L7
NC_2/A14
NC_3/A15
004:A7;004:C5;004:C2;004:F2;004:I4;004:I6
DDR01_ODT
E1
C449
E7
C1
DDR01_BA1
C3
DDR01_BA0
C7
DDR01_WEb
A1
DDR01_CKE
DDR01_ODT
L1
E9
R410
VSS_2
VSS_3
D2
D8
DDR01_RASb
DDR01_A[2]
A3
E3
DDR0_A[6]
DDR1_VREF0
K9
DDR01_A[3]
75
AR405
DDR01_A[1]
C452
VDDL
E1
C463
75
DDR01_BA1
DDR01_A[12] AR406
C466
E7
VSSDL
0.1uF 470pF
470pF 0.1uF
DDR01_A[9]
Close to IC
Close to IC
C483
0.1uF
DDR01_A[10]
C484
0.1uF
75
AR407
DDR01_A[11]
C492
0.1uF
DDR01_A[8]
DDR01_A[13]
DDR01_CKE
DDR01_ODT
75
AR408
C493
0.1uF
75
AR409
R404
IC401
NT5TU128M8DE_BD
DDR0_DQS0 004:E6
DDR0_DQS0b 004:E6
DDR0_DQS1 004:E3
B9
F10
F9
C19
004:A7;004:C7
DDR0_CLK
004:A7;004:C7
DDR0_CLKb
F8
DDR01_CKE
004:A7;004:C7;004:F7;004:F4
F2
D19
DDR1_DQS1b 004:H3
DDR01_RASb
C16
CK
DDR0_VREF0
DDR1_VREF0
A7
A23
CK
DQ1
CKE
DQ2
DDR01_RASb
F7
DDR01_CASb
G7
DDR01_WEb
F3
G8
DQ4
RAS
DQ5
CAS
DQ6
WE
DDR01_WEb
G3
G1
DQS
BA0
DQS
BA1
DM/RDQS
NC_1/BA2
NU/RDQS
DDR01_A[1]
H3
DDR01_A[2]
H7
DDR01_A[3]
J2
DDR0_A[4]
J8
DDR0_A[5]
J3
J7
DDR01_A[7]
K2
DDR01_A[8]
K8
DDR01_A[9]
K3
DDR01_A[10]
H2
DDR01_A[11]
K7
DDR01_A[12]
L2
DDR01_A[13]
L8
A0
VDDQ_1
A1
VDDQ_2
A2
VDDQ_3
A3
VDDQ_4
A4
VDDQ_5
A5
VDD_1
A6
VDD_2
A7
VDD_3
A8
VDD_4
A9
A10/AP
VSSQ_1
A11
VSSQ_2
A12
VSSQ_3
A13
VSSQ_4
L3
L7
NC_2/A14
NC_3/A15
GND
EN
DDR1_VREF0
VTTS
DDR0_VREF0
VREF
1
8
2
7
3
6
4
5
DDR0_DQ[12]
DDR01_CKE
F2
D3
DDR0_DQ[13]
D1
DDR0_DQ[15]
CK
DQ0
CK
DQ1
CKE
DQ2
DQ3
D9
DDR0_DQ[11]
DDR01_RASb
F7
B1
DDR0_DQ[10]
DDR01_CASb
G7
B9
DDR0_DQ[14]
DDR01_WEb
F3
G8
DQ4
RAS
DQ5
CAS
DQ6
WE
C8
DDR1_DQ[9]
C2
DDR1_DQ[8]
D7
DDR1_DQ[12]
D3
DDR1_DQ[13]
D1
DDR1_DQ[15]
D9
DDR1_DQ[14]
B1
DDR1_DQ[10]
B9
DDR1_DQ[11]
DQ7
C497
0.1uF
C498
0.1uF
SI
B7
DDR0_DQS1
004:A4
A8
DDR0_DQS1b
004:A4
B3
DDR0_DM1
VSS_2
VSS_3
DDR01_BA1
A2
DQS
G2
G3
004:A4
G1
DDR01_BA2
BA0
BA1
DM/RDQS
NC_1/BA2
NU/RDQS
B7
DDR1_DQS1
A8
DDR1_DQS1b
B3
DDR1_A[4-6]
004:B6;004:F6;004:I7
C3
C7
DDR01_A[1]
H3
DDR01_A[2]
H7
DDR01_A[3]
J2
J8
A1
DDR1_A[5]
J3
DDR1_A[6]
A9
H8
DDR1_A[4]
J7
E9
DDR01_A[7]
K2
H9
DDR01_A[8]
K8
DDR01_A[9]
K3
A7
DDR01_A[10]
H2
B2
DDR01_A[11]
K7
B8
DDR01_A[12]
L2
D2
DDR01_A[13]
L8
D8
A0
VDDQ_1
A1
VDDQ_2
A2
VDDQ_3
A3
VDDQ_4
A4
VDDQ_5
A5
VDD_1
A6
VDD_2
A7
VDD_3
A8
VDD_4
A9
VSSQ_1
A11
VSSQ_2
A12
VSSQ_3
A13
VSSQ_4
A3
VSS_1
L3
J1
L7
DDR0_VREF0
NC_2/A14
NC_3/A15
VSS_4
C1
C3
C7
C9
A1
L1
E9
H9
A7
A10/AP
VSSQ_5
E3
004:A3
D1.8V
DDR01_A[0]
C9
L1
004:A3
004:A4
DDR1_DM1
A2
DDR01_A[0-3,7-13]
C1
K9
DQS
VSS_2
VSS_3
B2
B8
D2
D8
A3
E3
J1
K9
DDR1_VREF0
VSS_4
VTT
DDR01_ODT
F9
E2
ODT
VREF
VDDL
VTT_IN
VSSDL
E1
E7
DDR01_ODT
C450
C453
0.1uF 470pF
F9
E2
ODT
VREF
VDDL
VSSDL
E1
C464
C467
E7
470pF 0.1uF
VCC
VDDQ
C422
1uF
10V
R417
220
C416
10uF
10V
C420
0.1uF
16V
Close to IC
C418
1uF
10V
Close to IC
0.1uF
16V
R415
0
D7
A9
H8
VSS_1
D1.8V
C496
0.1uF
DDR1_DQ[8-15]
CS
VSSQ_5
IC404
BD35331F-E2
F8
D1.8V
DDR01_A[0]
D3.3V
R418
10K
DDR1_CLKb
DDR01_A[0-3,7-13]
* DDR_VTT
C494
0.1uF
DDR01_BA0
G2
DDR0_A[4-6]
DDR_VTT
DDR0_DQ[8]
CS
DDR01_BA2
0.1uF
E8
DDR0_DQ[9]
C2
DQ7
75
004:B5
C8
DDR01_BA0
DDR01_BA1
C17 D1.8V
DQ0
DQ3
DDR1_DQS0b 004:H6
DDR1_DQS1 004:H3
E19
IC403
NT5TU128M8DE_BD
DDR0_DQ[8-15]
DDR1_CLK
E8
DDR0_DQS1b 004:E3
DDR1_DQS0 004:H6
B19
C427
C491
0.1uF
DDR01_A[0]
J1
E2
VREF
PI
B8
VSS_4
F9
ODT
C421
0.1uF
DDR_VTT
B2
DDR01_BA2
B10
C414
C499
0.1uF
75
H9
DDR01_BA0
F19
R414
0
75
AR404
DDR01_WEb
DDR0_DM0 004:E6
C423
10uF
10V
C495
470pF
DDR01_BA2
C9
DDR0_A[4]
DDR0_DM1 004:E3
DDR1_DM0 004:H6
DDR1_DM1 004:H3
C413
0.1uF
16V
C490
0.1uF
75
AR403
A7
A10/AP
VSS_1
J1
DDR1_DQ[8-15]
A20
C415
C489
0.1uF
DDR01_A[10]
VDD_4
A9
VSSQ_5
E3
VSSDL
DDR1_DQ[0-7]
A9
A3
E2
ODT
J8
VSS_4
F9
DDR01_ODT
DDR01_A[0]
VDD_4
A9
VSSQ_5
L7
C10
D22
C488
0.1uF
75
DDR01_A[13]
DDR01_A[3] AR402
NU/RDQS
DDR01_A[0-3,7-13]
A9
L3
A10
C7
C487
0.1uF
75
AR401
A8
DDR1_DQ[11]
A22
C486
0.1uF
DDR01_A[9]
DDR1_DQ[2]
B21
75
AR400
DDR01_A[7]
DQS
G2
C485
0.1uF
DDR01_A[0]
DDR0_A[5]
C419
10uF
10V
C482
0.047uF
DDR01_A[2]
DDR01_A[7]
C417
10uF
10V
C481
0.1uF
DDR01_RASb
DDR1_DQ[0]
E20
C480
10uF
SI
DDR01_A[0-3,7-13]
DDR1_A[5]
004:A4
NU/RDQS
VSS_1
DDR0_DQ[15]
A18
C479
470pF
C478
0.047uF
C477
0.1uF
C476
10uF
C475
22uF
C474
10uF
C473
10uF
C472
0.1uF
C471
0.047uF
C470
470pF
C469
10uF
C468
0.1uF
C465
0.047uF
C462
470pF
C460
0.047uF
C459
0.1uF
C458
10uF
C457
470pF
C456
0.047uF
C455
0.1uF
C454
10uF
C451
22uF
C448
10uF
C447
10uF
C446
0.1uF
C445
0.047uF
C461
470pF
F2
DDR01_CKE
CK
C8
CS
DQS
BA0
DDR0_DQ[8-15]
DDR0_A[6]
C412
0.1uF
16V
DDR0_DQ[3]
DQ0
DDR1_DQ[1]
C406
C411
0.1uF
16V
DDR0_DQ[2]
D3
F8
CK
C20
0.1uF
C425
10uF
16V
D7
004:A7;004:F4 DDR1_CLKb
E8
C18
DDR_VDDP1P8_2
C426
10uF
16V
C444
470pF
C443
10uF
DQ5
CAS
DDR0_DQ[1]
004:B5
R407
100
1%
DDR01_A[1]
DDR0_A[5]
DDR0_DQ[8]
DQ4
RAS
DDR0_DQ[0]
D1.8V
H8
DDR01_A[3]
DDR0_A[4]
D8
DQ2
NC_1/BA2
DDR01_A[0]
DDR01_BA1
DDR0_DQ[7]
CKE
C2
DDR01_A[0-3,7-13]
DDR01_BA2
DDR0_DQ[6]
DQ1
G2
DDR01_BA0
DDR0_DQ[5]
CK
DDR01_BA1
DDR01_A[7-13]
E15
C9
DDR1_DQ[0-7]
DDR01_BA0
B16
C11
DQ0
CS
F16
C8
C8
CK
DDR01_BA0
J2
E11
C442
0.1uF
E8
DQ3
DDR0_A[4-6]
DDR1_A[4]
F15
DDR0_CLKb
R406
100
1%
DDR01_CKE
DDR01_A[10]
C13
DDR0_CLK
DDR01_A[0-3]
DDR0_A[4]
E13
D14
C441
0.047uF
C440
470pF
DDR1_CLKb 004:F7;004:F4
B15
IC402
NT5TU128M8DE_BD
DDR0_DQ[0-7] 004:B6
004:A7;004:F4 DDR1_CLK
C410
DDR0_A06
A12
004:A7;004:C4
1uF
DDR0_A05
A13
C400
DDR0_A04
004:A7;004:C4
DDR0_CLK 004:C7;004:C4
DDR0_CLKb 004:C7;004:C4
DDR1_CLK 004:F7;004:F4
C12
C409
DDR01_A03
B12
C401
DDR01_A02
IC400
NT5TU128M8DE_BD
DDR01_ODT
C23
1uF
DDR01_A01
DDR_VTT
240
1%
470pF
DDR01_A00
DDR01_CKE
E16
470pF
DDR1_CLKB
0
R412
C408 OPT
DDR1_CLK
R411
OPT
C22
1uF
DDR0_CLK
DDR0_CLKB
B17
C402 OPT
DDR_EXT_CLK
B23
C407
DDR01_ODT
F20
470pF
DDR_COMP
C404
B24
C405
DDR01_CKE
C403
0.1uF
B7
1uF
DDR_PLL_LDO
0.1uF
A24
470pF
DDR_BVSS1
DDR_PLL_TEST
A6
0.1uF OPT
DDR_BVSS0
0.1uF OPT
DDR_BVDD1
C428
DDR_BVDD0
D1.8V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BCM (EUROBBTV)
HONG YEON HYUK
DDR Memory
2009.06.18
4
LGE Internal Use Only
EARPHONE BLOCK - spec out
COMPONENT
+3.3V_NORMAL
R902
10K
Rear CVBS
R903
1K
COMP1_DET
D900
5.6V
REAR_AV
C931
100pF
50V
REAR_AV
D906
5.1V
L904
270nH
COMP1_Y
[GN]E-LUG
D903
5.1V
6A
[GN]O-SPRING
D910
5.1V
5A
C904
27pF
50V
C932
27pF
50V
L903
270nH
4A
D904
5.5V
[BL]E-LUG-S
[BL]O-SPRING
C933
27pF
50V
5B
L902
270nH
[RD]O-SPRING_1
5C
5.5V
D905
[RD]E-LUG-S
7C
C934
27pF
50V
[WH]O-SPRING
C935
25V
5D
C906
27pF
50V
C905
27pF
50V
[RD]O-SPRING_2
R907
470K
COMP1_Pr
1uF
C939
100pF
50V
C936
25V
6E
[RD]O-SPRING
3C
[RD]CONTACT
4B
[WH]C-LUG
3A
[YL]CONTACT
4A
[YL]O-SPRING
5A
[YL]E-LUG
D909
5.6V
REAR_AV
REAR_AV
C910
100pF
50V
C941
25V
D908
5.6V
REAR_AV
R921
470K
REAR_AV
1uF
REAR_AV
REAR_AV_DET
R926
1K
R928
0
REAR_AV_R_IN
REAR_AV
C916
100pF
50V
REAR_AV
C940
25V
R909
0
COMP1_R_IN
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
4C
REAR_AV
R927
0
REAR_AV_L_IN
[RD]E-LUG
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
5C
COMP1_L_IN
D901
5.6V
5E
PPJ234-01
JK900
+3.3V_NORMAL
REAR_AV
R925
10K
REAR_AV
[RD]E-LUG
COMP1_Pb
R910
0
[RD]CONTACT
4E
REAR_AV
D911
5.1V
REAR_AV
JK902
REAR_AV_CVBS
REAR_AV
C909
47pF
50V
PPJ233-01
[GN]CONTACT
7B
R957
0
D902
5.6V
R961
470K
1uF
C937
100pF
50V
REAR_AV
D907
5.6V
REAR_AV
R920
470K
1uF
REAR_AV
REAR_AV
C915
100pF
50V
EUROBBTV
ETC SUB BOARD I/F
2009.06.18
9
LGE Internal Use Only
Motion Remote controller
Motion Remocon Interface
P1700
+3.3V_NORMAL
12507WR-08L
+3.3V_NORMAL
BLM18PG121SN1D
2
3
4
5
6
7
R1700
100
R1707
2.7K
R1705
2.7K
1
R1706
2.7K
L1700
120-ohm
M_REMOTE_RX
9:F3;9:G4
R1701
100
M_REMOTE_TX
R1702
100
9:F3;9:G4
M_RFModule_RESET
R1703
100
9:F3;9:G4
DC
9:F3;9:G3
DD
9:F3;9:G3
R1704
100
8
9
M_REMOTE
ALL M_REMOTE OPTION
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GP2_BCM_ATSC
MOTION_REMOCON
09/10/xx
20
100
LGE Internal Use Only
+24V_AMP
Sub AMP.
SPK2_L+
D2100
1N4148W
100V
3AMP OPT
3AMP OPT
R2121
3.3
C2134
22000pF
50V
100
2
AD
4
DGND_1
5
R2161
10K
AUD_LRCK
AUD_SCK
SDA2_3.3V
SCL2_3.3V
R2102
100
R2103
100
R2104
100
R2105
100
WAFER-ANGLE
PVDD1B_1
SIGN60000
OUT1B_2
VDR1B
BST1B
PGND1B_1
PGND1B_2
OUT1B_1
PVDD1B_2
PVDD1A_1
OUT1A_1
OUT1A_2
PGND1A_1
PVDD1A_2
44
45
46
47
48
49
51
50
52
53
54
43
42
NC
41
VDR2A
40
BST2A
39
PGND2A_2
38
PGND2A_1
C2148
25V1uF
37
OUT2A_2
36
OUT2A_1
35
PVDD2A_2
DGND_PLL
9
34
PVDD2A_1
AGND_PLL
10
33
PVDD2B_2
32
PVDD2B_1
31
OUT2B_2
30
OUT2B_1
29
PGND2B_2
4
3
D2102
1N4148W
100V
3AMP OPT
50V
R2129
12
R2135
12
C2160
390pF
50V
D2103
1N4148W
100V
3AMP OPT
C2161
390pF
50V
R2130
12
SPK2_R-
1
3AMP OPT
C2175
L2106
AD-9060
2S
2F
1S
1F
C2165
0.47uF
50V
C2169
R2141
0.1uF
50V
4.7K
P2101
0.01uF
50V
3AMP OPT
R2147
3.3
3AMP OPT
R2148
15uH
R2133
12
C2170
R2142
0.1uF
50V
4.7K
SPEAKER2_R
3.3
3AMP OPT
C2176
0.01uF
50V
SPK2_R-
28
+24V_AMP
C2157
10uF
35V
C2154
0.1uF
50V
C2140
1uF
25V
C2132
0.1uF
16V
C2152
22000pF
2
R2154
0
SPK2_R+
PGND2B_1
27
BST2B
26
25
VDR2B
/FAULT
24
23
MONITOR2
MONITOR1
MONITOR0
SCL
21
EAN60969601
20
14
NTP-7000
SDA
13
GND
19
12
DVDD_PLL
BCK
11
AVDD_PLL
18
LF
3AMP OPT
C2125
10uF
10V
100
SPEAKER2_L
3.3
3AMP OPT
C2174
0.01uF
50V
R2153
0
IC2100
C2107
0.1uF
16V
R2101
4.7K
R2152
0
8
+1.8V_AMP
AUD_LRCH
R2140
SPK2_L-
7
WCK
3AMP OPT
C2104
10uF
10V
R2134
12
SPK2_L+
6
15
C2102
0.1uF
16V
C2168
0.1uF
50V
15uH
3.3
3AMP OPT
R2146
C2144
1uF
25V
CLK_I
3.3K
3AMP OPT
C2100
10uF
10V
C2159
390pF
50V
R2128
12
4.7K
C2164
0.47uF
50V
3AMP OPT
C2173
0.01uF
50V
3AMP OPT
R2145
R2151
0
VDD_IO
17
R2157
1F
R2139
C2142
22000pF
50V
THERMAL
57
3
SDATA
100pF
50V
C2115
1000pF
50V
2F
1S
D2101
1N4148W
100V
3AMP OPT
GND_IO
L2102
C2106
55
56
VDR1A
25V /RESET
DVDD
L2100
1uF
DGND_2
BLM18PG121SN1D
BLM18PG121SN1D
+1.8V_AMP
1
16
C2110
100pF
C2118
0.1uF
BST1A
C2128
R2159
56
+1.8V_AMP
2S
C2167
0.1uF
50V
SPK2_R+
R2100
AUD_MASTER_CLK
PGND1A_2
EP_PAD
AMP_RESET_N
C2111
1000pF
50V
L2107
AD-9060
SPK2_L-
L2104
22
BLM18PG121SN1D
+3.3V_NORMAL
R2136
12
C2158
390pF
50V
3AMP OPT
C2155
0.01uF
50V
C2146
10uF
35V
C2136
0.1uF
50V
R2127
12
C2149
22000pF
50V
R2162
0
POWER_DET
C2138
1000pF
50V
OPT
C2114
33pF
50V
OPT
C2120
33pF
50V
C2122
22pF
50V
3AMP OPT
C2130
22pF
50V
C2124
22pF
50V
3AMP OPT3AMP OPT3AMP OPT
R2118
100
AMP_MUTE1
+24V_AMP
Woofer AMP.
SPK_Woofer+
D2104
1N4148W
100V
3AMP OPT
3AMP OPT
R2122
3.3
C2137
0.1uF
50V
C2135
22000pF
50V
AD
4
DGND_1
5
GND_IO
6
CLK_I
7
AUD_LRCH
AUD_LRCK
AUD_SCK
SDA2_3.3V
SCL2_3.3V
R2106
OUT2A_2
R2124
36
OUT2A_1
4.7K
R2137
12
3.3
3AMP OPT
R2150
C2172
0.1uF
50V
R2144
4.7K
Woofer
3.3
3AMP OPT
C2178
0.01uF
50V
OUT1B_2
OUT1B_1
PGND1B_2
PGND1B_1
BST1B
VDR1B
48
47
46
45
44
43
OUT2B_2
30
OUT2B_1
14
29
PGND2B_2
R2156
0
R2155
0
+24V_AMP
SPK_Woofer+
3AMP
1
2
FW25001-02(SPK 2P)
P2100
Development Item(Slim Depth)
28
27
BST2B
26
24
25
VDR2B
/FAULT
MONITOR2
23
MONITOR1
22
MONITOR0
20
21
SCL
SDA
19
BCK
18
17
EAN60969601
3AMP OPT
PVDD1B_1
49
31
13
GND
50V
SPK_Woofer-
12
DVDD_PLL
NTP-7000
C2153
22000pF
3AMP OPT
100
PVDD1B_2
PVDD1A_1
51
50
PVDD1A_2
52
53
OUT1A_1
OUT1A_2
54
PGND1A_1
55
100
PGND2A_1
37
PVDD2B_1
AVDD_PLL
C2133
0.1uF
16V
38
PVDD2B_2
11
3AMP OPT
C2127
10uF
10V
PGND2A_2
PVDD2A_1
10
LF
+1.8V_AMP
39
C2150
25V1uF
32
9
AGND_PLL
C2109
0.1uF
16V
BST2A
33
DGND_PLL
R2158
WCK
3AMP OPT
C2105
10uF
10V
VDR2A
40
34
8
15
C2103
0.1uF
16V
NC
41
PVDD2A_2
VDD_IO
3.3K
42
35
C2117
1000pF
50V
SDATA
100pF
50V
IC2101
16
C2108
THERMAL
57
3
C2145
1uF
25V
R2125
2
L2103
R2132
12
15uH
4.7K
R2126
1
DVDD
1uF
DGND_2
3AMP OPT
C2101
10uF
10V
BLM18PG121SN1D
BLM18PG121SN1D
+1.8V_AMP
L2101
R2160
C2113
100pF
C2119
0.1uF
+1.8V_AMP
BST1A
VDR1A
25V /RESET
C2129
56
PGND1A_2
EP_PAD
56
R2111
AUD_MASTER_CLK
D2105
1N4148W
100V
3AMP OPT
1F
C2166
0.47uF
50V
SPK_Woofer-
100
C2112
1000pF
50V
1S
C2163
390pF
50V
C2171
0.1uF
50V
2F
3AMP OPT
C2177
0.01uF
50V
3AMP OPT
R2149
C2143
22000pF
50V
L2105
AMP_RESET_N
2S
R2143
PGND2B_1
BLM18PG121SN1D
+3.3V_NORMAL
L2108
AD-9060
R2138
12
C2162
390pF
50V
3AMP OPT
C2156
0.01uF
50V
C2147
10uF
35V
R2131
12
C2141
1uF
25V
C2151
22000pF
50V
R2123
4.7K
100
R2107
100
R2108
100
R2109
100
R2110
100
R2119
0
POWER_DET
C2139
1000pF
50V
OPT
C2116
33pF
50V
OPT
C2121
33pF
50V
C2123
22pF
50V
C2126
22pF
50V
3AMP OPT
C2131
22pF
50V
3AMP OPT3AMP OPT3AMP OPT
R2120
100
AMP_MUTE1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
09.10
GP2_BCM_ATSC
AMP_SUB_NTP
21
100
LGE Internal Use Only
LG LOGO FOR LE9500
OPT
+5V_NORMAL
+3.5V_ST
1/10W
1/10W
33
0
R2299
R2298
P2200
12507WR-04L
1
2
LED_B/LG_LOGO
3
100
R2200
4
C
B
5
Q2200
2SC3052
E
D2200
CDS3C05HDMI1
5.6V
OPT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GP2_BCM_ATSC
LG_LOGO_LE9500
09/10/xx
22
100
LGE Internal Use Only
SIDE IR Emitter sync USB JACK
+5V_USB
P2402
12507WR-03L
L2403
1
120-ohm
2
R2404
0
3
4
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3D_SYNC_OUT
D2403
5.5V
3DTV
3DTV
78:T9
C2401
10pF
50V
3DTV
GP2_BCM_ATSC
3D_IR_GENDER
09/11/18
24
100
LGE Internal Use Only
IC2702-*1
TC7SZ02FU
+5V_TU
VERTICAL_NIM
IN_B
TU2701-*1
TDFR-G155D
CAN H-NIM/NIM TUNER for EU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
+B1[5V]
R2738
NC[RF_AGC]
0
AS
SCL[A_DEMOD]
HORIZONTAL_NIM
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
R2754
TU2701
TDFR-G135D
NC(IF_TP)
SIF
NC
VIDEO
0
RF_SWITCH_CTL
3.3V
RESET
2.5V
1
SCL[D_DEMOD]
close to TUNER
RF_S/W_CNTL
SDA[D_DEMOD]
ERR
2
SYNC
MCL
3
D0
D2
4
D3
D5
5
D6
Q2703
2SC3052
6
8
9
RF_S/W_CNTL
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
OUT_Y
C2704
100pF
50V
+B1[5V]
NC[RF_AGC]
R2700
LNA2_CTL/BOSTER_CTL
E
0
+B1[+5V]
10
NC[RF_AGC]
R2724
10K
B
IF_AGC_SEL
OPT
11
SDAT
1
R2746
470
R2749
82
3
B
SCL[A_DEMOD]
33
R2726
SDA[A_DEMOD]
33
R2727
+5V_TU
5
C2736
0.1uF
16V
FE_TS_ERR
TU_SIF
E
E
DVB_T/C
2
OPT
AS
R2758
47
4
FE_TS_VAL_ERR
ISA1530AC1
R2743
4.7K
C
Q2704
SCL0_3.3V
SIF
C2790
10pF
50V
OPT
C2714
18pF
50V
C2712
18pF
50V
NC(IF_TP)
C2791
10pF
50V
OPT
SDA0_3.3V
R2739
200
R2741
200
close to TUNER
C2702
0.1uF
NC
TU_CVBS
E
16V
R2736
0
B
NC_1
SCLT
FE_TS_VAL
+5V_TU
C
Q2700
2SC3052
OPT
+3.3V_TU
IC2702
NL17SZ08DFT2G
C2709
10uF
10V
OPT
C2708
0.1uF
16V
OPT
C2706
0.1uF
16V
BST_CNTL
VIDEO
C
+3.3V_TU
Q2702
ISA1530AC1
NC_2
SIF
12
NC_3
+3.3V_TU
GND
+1.2V_TU
CN
VIDEO
GND
13
+B2[1.2V]
RESET
14
NC_4
CN
1.2V
+B3[3.3V]
3.3V
C2737
4700pF
50V
C2738
1000pF
50V
C2700
100pF
50V
C2703
0.1uF
16V
C2705
100pF
50V
R2723
100K
R2721
100
C2707
0.1uF
16V
SDA
15
ERR
+5V_TU
+2.5V_TU
RESET
TUNER_RESET
C2710
0.1uF
16V
SCL
R2702
200
R2712
200
SYNC
VALID
16
MCL
2.5V
D1
17
D2
R2701
0
C2733
0.1uF
D0
ATV_OUT
16V
SCL[D_DEMOD]
SCL2_3.3V
R2728
33
R2729
33
E
D3
D4
18
D5
SDA[D_DEMOD]
SDA2_3.3V
D6
23
RF_S/W_CNTL
24
BST_CNTL
+B1[+5V]
NC[RF_AGC]
25
NC_1
SCLT
SDAT
26
NC_2
SIF
NC_3
27
VIDEO
GND
+B2[1.2V]
28
+B3[3.3V]
RESET
+B4[2.5V]
29
SCL
SDA
ERR
SYNC
VALID
ERR
31
30
CN
VALID
CN
R2731-*1
0
R2756-*1
30K
1/16W
5%
1/10W
1%
C2716
MCL
D0
EU R2757-*1
47
CN R2757
D1
CN R2717
D2
CN R2716
D3
CN R2711
D4
CN R2709
D5
CN R2708
D6
CN R2707
D7
CN R2710
CN R2705
D0
D1
D3
Q2705
ISA1530AC1
C2713
10pF
50V
C2711
10pF
50V
SYNC
MCL
D2
B
C
D7
TU2701-*3
TDFR-C135D
7
4
R2755
10K
B
D7
22
6
3
OPTION : RF AGC
C2701
0.1uF
16V
BST_CNTL
D4
CN_HORIZONTAL_LGS8G85
5
10K
C2718
0.01uF
25V
D1
21
4
R2742
ISA1530AC1
R2740
2.2K
C
0
+5V_TU
VALID
20
3
Q2701
C
R2720
1.2V
19
2
2
GND
B
CN
SHIELD
1
E
GND
TU2701-*2
TDFR-C155D
4
IN_A
SDA[A_DEMOD]
CN_VERTICAL_LGS8G85
3
VCC
BLM18PG121SN1D
BST_CNTL
7
2
5
RF_S/W_CNTL
SHIELD
1
1
DVB_T2
L2700
CN R2706
SHIELD
D4
D5
CN R2704
D6
D7
CN R2703
+3.3V_TU
0
EU R2717-*1
47
0
EU R2716-*1
47
100pF
50V
0
EU R2711-*1
47
0
EU R2709-*1
47
0
EU R2708-*1
47
0
EU R2707-*1
47
FE_TS_VAL
CN
R2713-*1
56K
FE_TS_DATA[0-7]
FE_TS_DATA_CLK
1/8W
1%
FE_TS_DATA[0]
1% 22K
IC2701
MP2212DN
L2703
CIC21J501NE
FE_TS_SYNC
EU
R2713
75K
1/8W
1%
FB
EU
R2756
18K
EU
R2731
FE_TS_ERR
Close to IC
1
8
2
7
EN/SYNC
1%
R1
+1.2V_TU
10K
R2732
POWER_ON/OFF2_2
Reduce analog beat noise
NR8040T3R6N
R2
GND
IN
3A
3
6
4
5
SW_2
3.6uH
L2704
SW_1
FE_TS_DATA[1]
BS
0
C2715
22uF
10V
FE_TS_DATA[2]
EU R2710-*1
47
0
EU R2705-*1
47
0
EU R2706-*1
47
0
EU R2704-*1
47
0
EU R2703-*1
47
0
VCC
C2730
22uF
10V
C2731
0.1uF
C2720
0.1uF
16V
C2735
10uF
16V
FE_TS_DATA[3]
R2719
0
R2718
FE_TS_DATA[4]
10
1/10W
1%
FE_TS_DATA[5]
C2717
1uF
10V
Vout=0.8*(1+R1/R2)
FE_TS_DATA[6]
FE_TS_DATA[7]
Close to the tuner
EU_VERTICAL_NIM_T2
TU2701-*4
TDFR-G055D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
RF_S/W_CNTL
R2722
0
+3.3V_NORMAL
EU
R2725
0
SHIELD
+3.3V_TU
FE_TS_SERIAL
L2702
CIC21J501NE
CN
60mA
BST_CNTL
+2.5V_TU
+3.3V_TU
+B1[5V]
NC[RF_AGC]
AS
SCL[A_DEMOD]
C2722
0.1uF
16V
C2724
0.1uF
16V
SDA[A_DEMOD]
C2734
0.1uF
16V
C2728
22uF
10V
IC2700
AZ2940D-2.5TRE1
NC(IF_TP)
VIN
SIF
1
$0.11 3
VOUT
NC
2
VIDEO
GND
+5V_TU
+5V_NORMAL
C2719
0.1uF
16V
1.2V
3.3V
L2701
RESET
200mA
BLM18PG121SN1D
2.5V
GND
R2744
1
C2723
10uF
10V
C2726
0.1uF
16V
SCL[D_DEMOD]
SDA[D_DEMOD]
ERR
SYNC
VALID
C2721
0.1uF
16V
C2725
0.1uF
16V
C2727
10uF
16V
C2729
22uF
10V
MCL
D0
D1
D2
D3
D4
D5
D6
D7
SHIELD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
27
Tuner ( Full Nim )
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
USB2 OPTION
USB / DVR Ready
+3.3V_NORMAL
IC2202
+5V_USB
AP2191SG-13
120-ohm
C2218
SIDE_USB_DM
C2206
1uF
10V
SIDE_USB_DP
L2202
MLB-201209-0120P-N2
NC 8
OUT_2 7
2 IN_1
OUT_1 6
3 IN_2
FLG 5
100uF
16V
C2203
0.1uF
C2204
0.1uF
C2205
0.1uF
26
RESET_N
0.1uF R2209
100K
OPT
3
25
HS_IND/CFG_SEL1
USBDN2_DP
4
24
SCL/SMBCLK/CFG_SEL0
VDDA33_1
5
23
VDD33
R2210
100K
22
SDA/SMBDATA/NON_REM1
NC_2
7
21
NC_8
20
NC_7
0
NC_6
C2213
/RST_HUB
USB
IC2203
100K OPT
R2211
100K OPT
R2213
100K OPT
R2207 OPT
R2208
OPT
L2203
MLB-201209-0120P-N2
120-ohm
C2219
SCL2_3.3V
SDA2_3.3V
KJA-UB-4-0004
JK2202
100uF
16V
NC 8
1 GND
+5V_USB
OUT_2 7
2 IN_1
OUT_1 6
3 IN_2
FLG 5
R2221
4.7K
OPT
4 EN
R2223
2.7K
EAN60921001
C2221
10uF
10V
C2223
0.1uF
USB_CTL2
+3.3V_USB
C2214
4.7uF
5
R2227
/USB_OCD2
040:J6
0
USB_DM2
USB_DP2
D2202
CDS3C05HDMI1
5.6V
D2204
CDS3C05HDMI1
5.6V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
/USB_OCD2
USB_CTL2
1uF
10V
C2209
/USB_OCD1
USB_CTL1
+3.3V_NORMAL
+3.3V_USB
4
0.1uF
R2206
100K
R2205
100K
0
R2204
100K
18
NC_5
17
OCS2_N
15
16
PRTPWR2
VDD33CR
14
13
C2211
0.1uF
VDD18
OCS1_N
12
PRTPWR1
TEST
C2215
0.1uF
OPT
USB DOWN STREAM
VDDA33_2
11
19
10
9
D2203
CDS3C05HDMI1
5.6V
AP2191SG-13
6
NC_4
R2214
0
R2212
NC_1
8
2
4
5
VBUS_DET
USBDN2_DM
IC2201
D2201
CDS3C05HDMI1
5.6V
C2212
27
2
USB2512A_AEZG
3
1
THERMAL
37
100K
R2203
SUSP_IND/LOCAL_PWR/NON_REM0
VDDA33_3
29
USBUP_DM
30
USBUP_DP
31
32
XTAL2
XTAL1/CLKIN
33
1
USB_DP1
+3.3V_USB
28
1/10W 1%
VDD18PLL
RBIAS
VDD33PLL
X2201
24MHz
USBDN1_DP
NC_3
C2222
0.1uF
/USB_OCD1
0
USB_DM1
1
C2202
0.1uF
C2220
10uF
10V
USB_CTL1
2
C2201
1uF
10V
R2226
2.7K
3
USB_DP2
R2202
1M 1%
34
R2201
12K
C2208
15pF
C2210
15pF
0.1uF
C2207
USB_DM2
35
VSS
USB_DP1
36
USBDN1_DM
USB_DM1
+3.3V_USB
4 EN
KJA-UB-4-0004
JK2201
USB DOWN STREAM
+3.3V_USB
R2220
4.7K
OPT
EAN60921001
R2225
+3.3V_NORMAL
L2201
BLM18PG121SN1D
1 GND
40
USB
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
+5V_NORMAL
+12V
+3.3V_NORMAL
R4126
10K
20
19
18
17
16
FIX-TER
15
[GN]GND
14
10
[GN]G
SC1_CVBS_IN
[GN]C_DET
8
[BL]B
C4113
47pF
50V
EU
R4115
62
R4123
0
AV_DET
SELECT
C
EU
C
R4133
390
EU
Q4105
2SC3052
EU
R4136
47K
B
EU
SYNC_GND2
SYNC_GND1
RGB_IO
R4112
75
D4106
30V
OPT
D4102
5.6V
OPT
Rf
C4114
100uF
16V
12
11
G_OUT
D2B_IN
[RD]R
9
G_GND
[WH]L_IN
8
ID
D4103
5.6V
CN
CN
D4113
5.1V
EU
R4104
75
1%
D4104
5.1V
CN
EU
R4101
75
1%
EU
270nH CN
R4108-*1
CM2012FR27KT
CN
C4147
27pF
50V
EU
R4134
180
5
2
4
3
7
[RD]R_IN
6
[RD]MONO
5
4
JK4101
3
Selece = Low
2
1
CN
C4148
27pF
50V
R4108
0 EU
EU
EU
30V
D4112
EU
B_OUT
SC1_B
AUDIO_L_IN
D4110
5.6V
CN
B_GND
EU
R4102
75
1%
SC1_ID
OPT
D4111
30V
EU
R4127
15K
EU
+12V
R4130
3.9K
AUDIO_L_OUT
C4105
25V
AUDIO_R_IN
1uF
OPT
OPT
R4141
68K
R4142
68K
C4122
33pF
AUDIO_GND
R4116
0
EU
R4149
33K
C4126 EU
6800pF
50V
C4123
10uF
16V
OPT
EU
EU
5.6K R4148
SCART1_Lout_N
5.6K
SCART1_Lout_P
C4112
100pF
50V
C4104
25V
EU
C4120
0.1uF
16V
2
R4176
10K EU
3
SCART1_Rout_P
R4113
0
002:C6
4
5
EU
R4150
33K
EU
R4144
14
2
13
3
12
4
11
5
10
6
9
7
8
14
13
12
6
11
10
9
+12V
1uF
C4111
100pF
50V
OPT
R4139
68K
EU
C4128
R4100
470K
1
R4147
EU
5.6K
R4143
5.6K
SC1_R_IN
D4108
5.6V
CN
1
C4127
33pF
EU
R4103
470K
D4109
5.6V
CN
AUDIO_R_OUT
EU
OPT
R4140
68K
R4145
1K
EU
7
33pF
8
R4177
10K EU
DTV/MNT_R_OUT
EU
[SCART2 PIN 8]
EU_SCART [OPT]
+12V
C4121
33pF
L4100
BLM18PG121SN1D
R4105
0
EU
DTV/MNT_L_OUT
EU
R4156
10K
EU
R4160
EU 0
R4157
0
R4152
EU
4.7K
D4105
5.6V
OPT
C
EU
Q4111
2SC3052
B
EU
12K
EU
C4100
1000pF
50V
EU
B
SC_RE1
R4154
1K
DTV/MNT_L_OUT
R4107
0
D4100
5.6V
OPT
E
Q4106
2SC3052
041:F3;041:G2
1/16W
5%
EU
C4101
1000pF
50V
EU
C4108
4700pF
50V
EU
R4151
2K
1/16W
RT1P141C-T112
Q4109
EU
SCART1_MUTE
3
C
EU
Q4108
2SC3052
EU
DTV/MNT_R_OUT
EU
B
C4125
6800pF
50V
041:F4;041:G2
C4107
4700pF
50V
DTV/MNT_R_OUT
EU
Q4110
2SC3052
EU
EU
E
C
EU
1/16W
5%
C4124
10uF
16V
OPT
EU
L4101
BLM18PG121SN1D
R4159
EU
EU
IC4100
LM324D
R4146
1K
DTV/MNT_L_OUT
PSC008-01
JK4100
R4155
1K
==> A = B0
EU_SCART [OPT]
REC_8
R4128
0
SCART1_Rout_N
SC_RE2
DTV/MNT_V_OUT
Audio Out Amp
SC1_G
SC1_L_IN
CN
B0
R4131
0
OPT
R4111
75
1%
13
PPJ-230-01
ATV_OUT
GND
Selece = High ==> A = B1
EU
4
B1
EU
R4137
15K
6
5
1
EU
EU
R4138
0
SC1_FB
SC1_R
R4168 0
D2B_OUT
EU
A
EU
R4122
22
R_OUT
RGB_GND
Rg
Gain=1+Rf/Rg
6
VCC
EU
C4117
47uF
16V
E
EU
R4132
390
EU
SYNC_OUT
IC4101
NLASB3157DFT2G
EU
C4119
0.1uF
16V
B
C4115
220pF
50V
OPT
SYNC_IN
R_GND
10
7
EU
COM_GND
13
9
DTV_ATV_SELECT
EU
C4118
0.1uF
16V
75
R4178
1%
21
EU
L4105
EU
R4135
470
EU
E
ISA1530AC1
Q4104
EU
EU
R4164
12
22
11
C4116
0.1uF
16V
D4101
30V
OPT
R6166
0
CN
D4107
5.6V
CN
EU
R4163
10K
EU
C4134
0.1uF
16V
SCART1_DET
R4129
1K
EU
R4153
1
EU
2
C4130
0.1uF
Q4107
REC_8
For Frequency Response
2SC3052
2K
1/16W
E
EARPHONE BLOCK
EARPHONE AMP - Spec out
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EUROBBTV
ETC SUB BOARD I/F
2009.06.18
41
LGE Internal Use Only
CI POWER ENABLE CONTROL
+5V_NORMAL
Q4501
RSR025P03
S
+5V_CI_Vs
D
R4512
10K
OPT
AR4515
10K
CI_A[0]
CI
C4509
4.7uF
16V
22K
0.1uF
16V
CI
CI CONTROL BUFFER
CI
CI
R4514
C4506
CI
CI
C4510
0.1uF
16V
C4508
47uF
16V
G
CI
CI_A[1]
CI
CI_A[2]
CI_A[3]
VCC
/CI_CE1
/CI_CE2
O0
O1
O2
/CI_WE
016:H12
O3
/CI_IOWR
016:T12
O4
016:G13
/CI_OE
016:T13
/CI_IORD
O5
O6
O7
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
OE1
CI
AR4517
10K
10K
R4503
CI
16V
0.1uF
C4500
IC4500
MC74LCX541DTR2G
OE2
016:T13;016:AJ2
2.2K
CI
CI
016:G13;016:AJ2
R4526
D3.3V
D3.3V
CI_A[4]
CI
CI_5V_CTL
CI_A[5]
/CI_SEL 007:H5
007:H7
CI_A[6]
D0
EBI_CS
007:E7;007:E6;016:AL23
D1
CI
007:C2;007:E5
EBI_WE
Q4500
2SC3052
E
CI_A[7]
CI_A[8]
D3
D4
R4513
10K
B CI
AR4501
10K
D2
NAND_WEb
[GP27]
C
007:E6
CI_A[9]
007:C3;007:E6
NAND_REb
D5
CI_A[10]
007:C2;007:E6
NAND_ALE
CI_A[11]
D6
CI
D7
AR4504
10K
GND
CI_A[12]
D3.3V
CI_A[13]
IC4501
74LVC245A
016:F16CI_D[0-7]
007:E7;016:C13
CI
DIR
1
20
2
19
3
18
4
17
5
16
6
15
7
14
0.1uF
16V
EBI_RW
C4507
CI
007:E6
CI_A[0-13]
EBI_CS
007:E7;007:E6;016:K26
VCC
NAND_DATA[0-7]
CI_D[0]
A0
CI_D[1]
A1
CI_D[2]
A2
CI_D[3]
A3
CI_D[4]
A4
CI_D[5]
A5
CI_D[6]
A6
CI_D[7]
A7
GND
016:AG22 CI_D[0-7]
CI_D[4]
NAND_DATA[4]
B5
NAND_DATA[5]
B6
NAND_DATA[6]
B7
NAND_DATA[7]
CI
/CI_CE2
016:H25;016:AJ2
[GP26] 016:AJ3
9
43
CI_A[11]
10
44
/CI_IORD
016:H24
CI_A[9]
11
45
/CI_IOWR
016:H25
12
46
13
47
FE_TS_DATA[0]
14
48
FE_TS_DATA[1]
15
49
16
50
FE_TS_DATA[3]
17
51
R4505
18
52
R4507 100
0
19
53
OPT
AR4516 33
CI
FE_TS_DATA[4]
20
54
FE_TS_DATA[5]
21
55
FE_TS_DATA[6]
22
56
FE_TS_DATA[7]
57
24
58
25
59
CI
26
60
CI_A[2]
27
61
CI_A[1]
28
62
29
63
30
64
31
65
32
66
33
67
34
68
CI_A[0]
AR4513
33
016:AJ3
[GP41] /CI_IOIS16
R4504
OPT
100
G1
69
CI
47
R4506 016:AL9
100
/CI_INPACK
CI
OPT
0 R4508
R4511
007:G6;016:AJ2
CI_MOD_RESET [GP49]
/CI_WAIT 007:E6;016:AJ3
AR4505
33
DVB-CI PULL-UP (Near CI Slot)
CI_OUTCLK
CI
CI_OUTVALID
CI_OUTSTART
+5V_NORMAL
AR4514 33
CI
CI_OUTDATA[0]
CI_OUTDATA[1]
10K
23
CI_A[4]
External Demod.
OPT
CI_A[6]
CI_A[5]
C4503
0.1uF
CI_OUTDATA[2]
G2
CI_OUTDATA[3]
CI
R4509
100
/CI_CD2
0.1uF
CI
C4504
/CI_IOIS16
/CI_IREQ
/CI_VS1
/CI_WAIT
CI_OUTCLK
AR4520 33
[GP38]
007:H5;016:AJ2
CI
AR4519
33
R4525
CI
FE_TS_DATA[2]
10K
C4502
0.1uF
33
AR4506
FE_TS_DATA[0-7]
10K
CI
16V
CI
CI
R4524
OPT
R4500
CI
33
R4523
OPT
47
0.1uF
/CI_WE
/CI_IREQ
[GP39]
007:H5;016:AJ3
C4501
CI_A[12]
AR4512
10K
CI
/CI_INPACK
R4522
CI
CI_A[14]
016:O9
CI
CI_A[8]
/CI_VS1
CI
/CI_OE
10K
42
CI_OUTDATA[7]
10K
8
DVB-CI PULL-DOWN (Near CI Slot)
CI_OUTDATA[6]
R4521
41
CI_OUTDATA[5]
CI
40
7
CI_OUTCLK,CI_OUTDATA[0-7],CI_OUTSTART,CI_OUTVALID
CI_OUTDATA[4]
R4520
6
AR4502 33
CI
10K
39
R4519
OPT
R4502
38
5
22K
47
37
4
10K
R4501
CI
36
3
R4517
47
/CI_CE1
35
2
007:H6;016:AJ3
R4518
CI_A[0-14]
1
/CI_CD1
CI
C4505
0.1uF
10K
CI
CI_A[3]
NAND_DATA[3]
B4
R4516
OPT
AR4507
33
CI
CI_D[2]
CI_A[7]
B3
10K
CI
CI_D[0]
AR4509
33
11
NAND_DATA[2]
R4515
CI_D[7]
P4500
10067972-000LF
CI_D[1]
CI_A[13]
10
NAND_DATA[1]
B2
CI
R4510
100
CI_D[6]
CI
12
B1
AR4511
33
CI
CI_D[5]
33
AR4518
13
9
NAND_DATA[0]
B0
+5V_CI_Vs
CI_D[3]
CI_A[10]
8
OE
/CI_CD1
/CI_CD2
/CI_CE1
/CI_CE2
FE_TS_SYNC
FE_TS_VAL_ERR
CI_MOD_RESET
FE_TS_DATA_CLK
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EUROBBTV
CI
2009.06.18
45
LGE Internal Use Only
PANEL_VCC
[51Pin LVDS Connector]
(For FHD 60/120Hz)
L7800
120-ohm
TM480Hz
P7800
TF05-51S
TM480Hz
C7800
10uF
25V
OPT
1
C7801
1000pF
50V
TM480Hz
C7802
0.1uF
50V
TM480Hz
2
3
4
I2C_#3 Check(LG5111,LG1120,etc)
5
6
For Debugging
7
OPT
8
P7801
12507WR-04L
9
10
11
RRXB4+/RLV0P
12
RRXB4-/RLV0N
1
R7806
0
SCL3_3.3V
0
SDA3_3.3V
0
V_SYNC
OPT
2
13
RRXB3+/RLV1P
14
RRXB3-/RLV1N
R7805
OPT
3
15
16
RRXBCK+/RLV2P
17
RRXBCK-/RLV2N
4
R7804
OPT
5
18
19
RRXB2+
20
RRXB2-
21
RRXB1+
22
RRXB1-
23
RRXB0+/RLCLKP
24
RRXB0-/RLCLKN
25
26
27
RRXA4+/RLV3P
28
RRXA4-/RLV3N
29
RRXA3+
30
RRXA3-
31
32
RRXACK+/RLV4P
33
RRXACK-/RLV4N
34
P7803
35
RRXA2+/RLV5P
36
RRXA2-/RLV5N
37
RRXA1+
38
RRXA1-
39
RRXA0+
40
RRXA0-
If current of 12V is over 2A, use another power cable for 3DTV
12507WR-06L
P7802
1
12507WR-04L
L7801
1
120-ohm
41
42
43
44
47
48
49
50
R7811
0
E_TCK
3
R7812
0
E_TDO
4
R7813
0
E_TMS
5
R7814
0
E_TDI
2
R7810
0
OPT
R7809
0
3D_DIMMING
R7808
0
3DTV
3D_DIMMING_2
3
3D_DIMMING
L/R_SYNC
4
45
46
2
PANEL_VCC
R7800
0
TM480Hz
R7801
0
TM480Hz
R7802
0
TM480Hz
R7803
0
TM480Hz
R7807
0
3DTV
FRC_RESET
6
5
7
SCL3_3.3V
SDA3_3.3V
V_SYNC
3D_SYNC_OUT
51
52
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
COMMON
LG5111 60Hz LVDS
09/10/xx
78
100
LGE Internal Use Only
[To MASTER LED DRIVER]
P7900
12507WR-10L
IOP
1
L_VS
2
M0_MOSI
3
M0_SCLK
+3.3V_NORMAL
4
5
M1_MOSI
6
M1_SCLK
R7907
3.3K
Edge
7
R7908
3.3K
Edge
R7909
3.3K
Edge
8
R7904
22
IOP
S_CS_N
9
R7905
22
IOP
S_MOSI
10
R7906
22
IOP
11
S_SCLK
C7903
100pF
50V
C7901
100pF
50V
C7907
100pF
50V
OPT
OPT
OPT
C7905
100pF
50V
C7909
100pF
50V
C7911
100pF
50V
OPT
OPT
C7913
100pF
50V
OPT
OPT
C7914
100pF
50V
OPT
[To SLAVE LED DRIVER]
P7901
12507WR-08L
Except Edge(42/47")
1
R7900
3
4
R7901
22
Edge(55")
R7902
6
22
IOP
R7911
22
IOP
R7912
22 Edge(55")
R7913
22
R7914
22 Edge(55")
R7918
22
IOP
R7919
22
IOP
R7915
22 Edge(55")
R_VS
OPT
2
5
R7910
22
IOP
M2_MOSI
M2_SCLK
M2_SCLK
M2_MOSI
22
IOP
7
R7916
22
Edge(55")
8
R7917
22
Edge(55")
M3_MOSI
M3_SCLK
R_VS
9
R7903 22
IOP
C7900
100pF
50V
OPT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C7902
100pF
50V
OPT
C7904
100pF
50V
OPT
C7906
100pF
50V
OPT
C7908
100pF
50V
OPT
C7910
100pF
50V
OPT
C7912
100pF
50V
OPT
GP2_Saturn7M
Interface for LG5111
Ver. 1.0
72
LGE Internal Use Only
PIN No
Driver
On
22
N.C
N.C
4
24V
5
6
GND
GND
7
8
GND
3.5V
9
10
3.5V
11
12
3.5V
GND
13
14
GND
GND
15
16
GND/V-sync
12V
17
18
INV ON
12V
19
20
A.DIM
12V
21
22
P.DIM1
23
24
Err OUT
R8063
12K
1%
R8053
47K
R8054
5.6K
1%
1%
POWER 20V
R8061
24K 1%
NCP803SN293
VCC
3
2
R8074
100
RESET
1
POWER 18.5V
R8062-*2
4.7K 1%
POWER 24V
R8062-*1
4.3K 1%
POWER 20V
R8062
5.1K 5%
GND
R2
3
13
12
0
NON_ESD
R8043 R8046
EN/SYNC
PGND_2
L8009
2uH
C8069
0.1uF
OPT
4
11
5
10
6
9
SW_2
470K
1%
30K
R1
MAX 2.3A
A1.2V
D1.2V
R8060
R8048
POWER_ON/OFF2_2
L8013
910K
1%
1%
+3.3V_NORMAL
+12V
ESD
R8045-*1
100K
L8011
BLM18PG121SN1D
R2
L8006
MLB-201209-0120P-N2
NC
BS
7
8
IN_2
C8036
0.1uF
POK
R8040
VCC
100K
R8041
EN
C8037
22uF
10V
R8042
0
10
MP2208DL-LF-Z
C8041
22uF
10V
C8043
10uF
16V
FB
C8045
0.1uF
16V
C8051
0.1uF
50V
C8052
22uF
25V
COMP
C8032
0.1uF
C8033
1uF
10V
6
4
IC8005
7
LX
AOZ1024DI
5
R8058
20K
C8054
2200pF
50V
C8029
22uF
16V
D3.3V
L8016
CIC21J501NE
L8015
3.6uH
VIN
IN_1
+3.3V_NORMAL
10K
CIC21J501NE
1%
2
R8045
FB
MAX 3.1A
POWER_ON/OFF2_1
R8069
27K
0
POWER 24V
R8061-*1
24K 1%
1%
0
C8012
1uF
25V
OPT
SCAN_BLK2
not to RESET at 8kV ESD
IC8008
POWER 18.5V
R8061-*2
22K 1%
OPT
R8080
14K 1%
OPT
C8046
100pF
50V
R8079
100K
+24V
+3.5V_ST
C8049
0.1uF
16V
R8070
4.7K
14
IC8001
SW_1
C8057 C8059
22uF 22uF
10V
10V
C8067
10uF
10V
C8063
0.1uF
16V
C8064
0.1uF
16V
C8035
22uF
Vout=0.8*(1+R1/R2)
D
Q8004
AO3407A
S
R8010
10K
C8013
10uF
16V
PANEL_VCC
G
R8011
1.8K
OPT
C8015
1uF
25V
C
Q8003
2SC3052
B
C
R8008
22K
Q8001
2SC3052
C8022
0.1uF
50V
E
BCM DDR 1.8V
Max 1100 mA
A2.5V
+3.3V_NORMAL
1:AK10
E
+3.5V_ST
A2.5V
D1.8V
IC8004
SC4215ISTRT
BST
+12V
1
2
+5V_USB
L8001
500
LX
MAX 1500mA
Placed on SMD-TOP
PGND
C IN
C8002
10uF
25V
SW_2
C8007
0.1uF
BST
7
3
3A
4
6
5
OPT
C8016
100pF
50V
C8014
1uF
50V
VCC
EN/SYNC
POWER_ON/OFF2_1
R8013
10K
R8006
22
R1
R8012
10K
FB
1%
2
GND
R8016
33K
8
OPT
C8019
100pF
50V
C8020
22uF
10V
C8023
0.1uF
16V
C8025
0.1uF
16V
C8031
22uF
10V
SGND
3
4
5
10
3A
500
L8014
R8059
10K
9
8
7
6
RUN
10K
R8052
1
8
2
7
NC_1
EN
VOUT : 2.533V
GND
R8073
18K R2
1%
ADJ
R8072
39K R1
1%
POWER_ON/OFF1
VREF
C8042
0.01uF
25V
COMP
FB
C8039
3300pF
50V
SS
C8038
0.01uF
25V
R8051
6.8K
OPT
50V
100pF
C8044
R2
R8056
10K
1/10W
1%
C8053
10uF
16V
R1
R8057
3
6
4
5
VO
VIN
C8055
0.1uF
OPT
C8056
0.1uF
NC_2
NC_3
C8058
10uF
16V
C8061
10uF
16V
C8062
0.1uF
Placed on SMD-TOP
10K
1%
C8048
22uF
10V
C8050
0.1uF
Vout=0.8*(1+R1/R2)
1%
SW_1
1
R8017
6.2K
IN
NR8040T3R6N
IC8002
MP2108DQ
VIN
IC8000
MP8706EN-C247-LF-Z
L8012
3.6uH
Replaced Part
C8034
0.01uF
25V
L8008
+5V_USB
CIC21J501NE
Vout=0.9*(1+R1/R2)
500
L8017
PANEL_CTL
C8066
22uF
10V
1%
PGND_1
1
ERROR_OUT
C8027
0.1uF
R8001
47K
B
ESD
C8065
0.1uF
16V
R8071
10K
SS
C8026
0.1uF
PANEL_POWER
OPT
R8002
10K
C8047
22uF
10V
R1
OPT
AGND
R8025
0
OPT
L8000
CIC21J501NE
ESD
D8000
5.6V
OPC_OUT
+12V
R8003
22K
GND
3.9K
R8066
10K
EP
R8034
0
HD_OPC
R8024
0
AUO/SHARP
C8010
10uF
25V
OPT
POWER_DET
R8044
PWM_DIM
R8033
0
SCAN_BLK1/OPC_OUT
SCAN/FHD_OPC
C8021
1uF
25V
OPT
C8017
0.1uF
OPT
GND
C8009
0.1uF
50V
R8081
100
RESET
BCM core 1.2V volt
A_DIM
R8027
0
NON_OPC
+3.5V_ST
C8008
0.01uF
25V
2
1
0
LGD_V4
R8035
0 +3.3V_NORMAL
PWM_DIM
Err_out INV_ON PWM_DIM
24
R8020
NON_SCAN_PSU
0
INV_ON
A-DIM
3
R8039
10K
OPT
R8031 0
R8022
0
COMP
5
Vout=0.8*(1+R1/R2)
AUO R8030
R8021
AUO
4
INV_CTL
R8029
CMO 0
LGD_IOP
FB
12K
2200pF
R8049
C8040
Q8005
2SC3052
E
POWER_ON/OFF2_2
EN
6
R8055
10K
SCAN
R8009
0
OPT
2A
3
LX_1
R8050
10K
C8030
10uF
25V
C8028
10uF
25V
R8032
10K
B
Err_out Err_out
NC
VCC
2
PWM_DIM PWM_DIM
7
IC8007
NCP803SN293
1
22
2
L8010
3.6uH
LX_2
3
V4:VBR-A
V5:NC
8
Power_DET
+3.5V_ST
R8068
100K
PGND
20
A-DIM
1
+5V_NORMAL
AGND
INV_ON
C
R8023
6.8K
R8084
0
VIN
C8068
0.1uF
16V AGND
+3.3V_NORMAL
R8026
1K
R8018
100
P8001
SHARP
INV_ON
18
400Hz_MO_SCLK/42_47_LOCAL DIMMING
R8077
0
M2_SCLK
R8028
0
MO_SCLK
400Hz_MO_SCLK
V_SYNC
NON_CMO
R8019
100
SCAN_PSU
AUO
PGND
3.9K
CMO(09)
0
OPT
R8037
4.7K
LGD
L8007
CIC21J501NE
OPT
R8047
C8011
0.1uF
16V
OPT
R8085
0
SCAN_LIPS
0
SCAN_PSU
25
SMAW200-H24S2
0
PIN No
MAX 350mA
+3.5V_ST
NR8040T3R6N
R8082
400Hz_VSYNC
CMO
<OS MODULE PIN MAP>
ST_3.5V-->3.5V
IC8003
AOZ1072AI
R_VS
400Hz_VSYNC
R8036
0
L_VS
SLIM_32~52
R8007
400Hz_MD_MDSI/42_47_LOCAL DIMMING
R8076
0
M2_MOSI
MO_MOSI
C8005
0.1uF
50V
400Hz_MD_MDSI
R8005
0
C8003
0.1uF
50V
C8001
100uF
25V
GND/P.DIM2
+12V
15
+12V
400Hz_VSYNC/42_47_LOCAL DIMMING
R8078
0
C8024
68uF
35V
C8018
0.1uF
50V
3.5V
C8006
0.1uF
16V
L8002
MLB-201209-0120P-N2
L8005
MLB-201209-0120P-N2
R8083
C8004
0.1uF
16V
24V
GND
L8003
MLB-201209-0120P-N2
C8000
100uF
16V
2
SCAN_PSU
+3.5V_ST
PWR ON 1
24V
3
THERMAL
E
+5V_NORMAL
NON_PD_+3.5V
R8064
5.1K
NORMAL_26~52
P8000
FW20020-24S
2
Q8000
2SC3052
R8014
B
12V-->3.58V
+24V
LD
R8015
0
C
R8000
10K
RL_ON
3
1
SHARP
R8004
4.7K
+12V
OPT
R8075
10K
15V-->3.6V
20V-->3.5V
24V-->3.48V
Q8002
R8067
1K
RT1P141C-T112
PD_+3.5V
1%
23
R8064-*1
27K
SCAN_BLK2
N.C
18
PD_+3.5V
1%
SCAN_BLK1/OPC_OUT
OPC_OUT
+3.5V_ST
16
PD_+12V
1%
FROM LIPS & POWER B/D
LX95
1/16W
5%
L_VS
R_VS
MO_SCLK
M2_SCLK
MO_MOSI
M2_MOSI
R2
L8004
3.6uH
+5V_USB
NR8040T3R6N
Vout=(1+R1/R2)*0.8
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BCM (EUROBBTV)
POWER
15
LGE Internal Use Only
FLMD0
GND
10K
MICOM_DOWNLOAD
32.768KHz
R8175
P123/XT1
P124/XT2/EXCLKS
RESET
P40
P41
P120/INTP0/EXLVI
42
41
40
39
38
37
OCD1B
22
R8104 10K
+3.5V_ST
10K
R8105
10K
10K
R8107
10K
22
P60/SCL0
1
R8128
22
P61/SDA0
2
P62/EXSCL0
3
P63
4
NEC_EEPROM_SCL
NEC_ISP_Tx
NEC_EEPROM_SDA
OPT
R8126
NEC_ISP_Rx
10K
R8106
R8129
22
P33/TI51/TO51/INTP4
5
R8130
22
P75
6
R8131
22
P74
7
HDMI_CEC
OCD1A
POWER_ON/OFF2_1
OCD1B
AMP_MUTE
+3.5V_ST
R8188
22
34
P01/TI010/TO00
R8189
10K
33
P130
R8192
32
P20/ANI0
R8194
22
31
ANI1/P21
R8195
22
30
ANI2/P22
R8196
22
22
WIRELESS_SW_CTRL
ANI3/P23
R8190
22
28
ANI4/P24
R8193
22
MODEL1_OPT_3
MODEL1_OPT_2
POWER_ON/OFF1
22
P71/KR1
10
27
ANI5/P25
R8135
22
P70/KR0
11
26
ANI6/P26
12
25
ANI7/P27
P32/INTP3/OCD1B
FLASH_WP
MICOM_DOWNLOAD
R8134
22
RL_ON
SCART1_MUTE
29
R8191
22
SIDE_HP_MUTE
KEY2
KEY1
NON_M-REMOTE
TOUCH_KEY
31
PDP/3D
LCD/OLED
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
LCD
PDP
OLED
3D
MODEL_OPT_0
0
0
1
1
MODEL_OPT_3
0
1
0
1
LOW
LOW_SMALL
LX9500
HIGH
MODEL_OPT_1
0
0
1
1
MODEL_OPT_2
0
1
0
1
AVSS
C8107 1uF
P10/SCK10/TXD0
22
R8179
AVREF
P11/SL10/RXD0
22
R8177
P12/SO10
P13/TXD6
P14/RXD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
TACT_KEY
FOR ATSC Assy
SCART1_MUTE
R8181
10K
OPT
R8182
10K
OPT
TP8100
OPC_EN
SIDE_HP_MUTE
10K
OPT
NEC_TXD
30
MODEL_OPT_3
22
MODEL_OPT_2
+3.5V_ST
+3.5V_ST
R8183
NEC_RXD
LCD/PDP
R8124
10K
PWM_LED
R8121
10K
TACT_KEY
R8112
10K
LCD/OLED
R8110
10K
MODEL1_OPT_3
POWER_ON/OFF2_2
OPC
R8176
PWM_LED
NEC_ISP_Tx
LOGO_BUZZ
NEC_ISP_Rx
11
22
MODEL_OPT_1
R8145
LCD/PDP
IR
OLED/3D
LED_R/BUZZ
LOW
8
MODEL1_OPT_1
MODEL1_OPT_2
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HIGH
MODEL_OPT_0
TACT_KEY
OLED/3D
R8123
10K
LOGO_BUZZ
R8120
10K
MODEL1_OPT_0
LED_B/LG_LOGO
100
100
PIN NO.
22
100
R8103
R8101
MODEL OPTION
PIN NAME
OCD1A
R8102
TOUCH_KEY
R8111
10K
+3.5V_ST
R8144
NEC_EEPROM_SDA
PDP/3D
R8109
10K
OPC_EN
P00/TI000
9
POWER_DET
R8114
MICOM MODEL OPTION
PANEL_CTL
35
8
P31/INTP2/OCD1A
SDA
22
AMP_RESET_N
22
P72/KR2
22 NON_M-REMOTE
NEC_EEPROM_SCL
22
VSS
NEC_MICOM
R8142
5
R8117
0.1uF
4
SCL
C8100
6
WC
R8122 4.7K
3
UPD78F0513AGA-GAM-AX
36
R8187
VCC
R8125 4.7K
R8100
47K
NC_3
IC8101
13
M24C16-WMN6T
7
Q8100
2SC3052
E
P140/PCL/INTP6
P73/KR3
R8136
OCD1B
2
EDID_WP
C
B
22
MODEL1_OPT_1
IC8100
8
20K
1/16W
1%
22
INV_CTL
EEPROM for Micom
1
R8186
R8133
SOC_RESET
NC_2
3
R8132
MODEL1_OPT_0
NC_1
1
4
24
+3.5V_ST
R8127
23
SCL1_3.3V
SDA1_3.3V
R8108
2
FLMD0
12
22
R8119
11
13
14
9
R8178
0.1uF
8
10
21
22
OCD1A
20
R8118
NEC_ISP_Rx
15
7
19
22
6
C8108
0.1uF
1/16W
1%
FLMD0
43
R8116
NEC_ISP_Tx
18
22
SW8100
JTP-1127WEM
R8185
20K
P122/X2/EXCLK/OCD0B
44
22
R8115
47K
P121/X1/OCD0A
45
R8113
17
5
16
4
MICOM_RESET
C8104
3
R8184
REGC
46
+3.5V_ST
1
2
22
VSS
47
C8103
0.1uF
22
VDD
48
GND
for Debugger
+3.5V_ST
P8100
R8180
4.7M
+3.5V_ST
12505WS-12A00
+3.5V_ST
X8101
OPT
WIRELESS_PWR_EN
R8139
10K
MICOM_RESET
C8105
C8106
0
R8138
WIRELESS_DETECT
27pF
R8146
22pF
10MHz
X8100
0
R8143
47K
50V
15pF
C8102
OPT
50V
15pF
C8101
R8140
10Mhz Crystal Ready
+3.5V_ST
GP2_Saturn7M
MICOM
Ver. 1.4
5
LGE Internal Use Only
+3.5V_ST
IR & KEY
EYEQ
R8225
100
NEC_EEPROM_SCL
D8204
CDS3C05HDMI1
5.6V
R8213
10K
1%
R8211
10K
1%
L8200
BLM18PG121SN1D
R8209
100
1
EYEQ
R8226
100
KEY1
L8201
BLM18PG121SN1D
R8210
100
P8200
12507WR-12L
C8213
1000pF
50V
OPT
D8201
5.6V
AMOTECH
KEY2
C8206
0.1uF
2
NEC_EEPROM_SDA
D8205
CDS3C05HDMI1
5.6V
C8214
1000pF
50V
OPT
C8207
0.1uF
D8200
5.6V
AMOTECH
3
4
+3.5V_ST
+3.5V_ST
5
L8202
BLM18PG121SN1D
+3.5V_ST
R8202
47K
R8200
22
6
+3.5V_ST
R8204
47K
IR
Q8200
2SC3052
C8208
0.1uF
16V
C8209
1000pF
50V
R8227
LED_B/LG_LOGO
1.5K
TACT_KEY
R8203
10K
C
B
E
R8205
47K
C
R8206
3.3K
OPT
7
OPT
C8215
0.1uF
16V
8
R8224
100
9
B
Q8201
2SC3052
E
+3.5V_ST
COMMERCIAL
R8201
0
10
L8203
BLM18PG121SN1D
R8276
R8218
47K
R8216 COMMERCIAL
10K
IR_OUT
COMMERCIAL
C
Q8202
2SC3052
COMMERCIAL_EU
11
+3.5V_ST
R8214
47K
R8207 COMMERCIAL_EU
22
OPT
D8206
5.6V
AMOTECH
C8212
100pF
50V
+3.3V_NORMAL
C8210
0.1uF
16V
LED_R/BUZZ
C8211
1000pF
50V
1.5K
B
E
COMMERCIAL_EU
12
OPT
R8280
10K
13
R8220
47K
C
ETHERNET CONNECT
B
Q8204
2SC3052
COMMERCIAL
COMMERCIAL
E
A2.5V
L8204
JK8200
CIC21J501NE
XRJV-01V-D12-180
R8212
0
COMMERCIAL_US
R8283
0
Zener Diode is
close to wafer
R8284
0
R8217
10K
C
E
WIRELESS
5.6V
5
OPT
C8222
10pF
50V
B
E
6
EPHY_RDN
R8221
47K
C
Q8205
2SC3052
WIRELESS
C8216
1000pF
50V
R8286
0
B
WIRELESS
5.6V
Q8203
2SC3052
WIRELESS
D8209
WIRELESS
4
OPT
C8221
10pF
50V
R8219
47K
WIRELESS
D8212
EPHY_RDP
3
OPT
C8220
10pF
50V
D8208
R8208
22
IR_PASS
R8285
0
5.6V
EPHY_TDN
+3.5V_ST
R8215
47K
WIRELESS
2
5.6V
D8207
OPT
C8218
10pF
50V
+3.5V_ST
WIRELESS
1
EPHY_TDP
7
C8217
1000pF
8
D3.3V
R8281
510
R8282
510
D2
5.6V
D3
5.6V
D4
D8211
D8210
EPHY_LINK
EPHY_ACTIVITY
D1
9
RS232C
10
+3.5V_ST
5
9
OPT
IR_OUT
4
R8279
0
R8277
100
8
3
C8200 0.33uF
IC8200
C1+
C8202
0.1uF
V+
C2-
VC8204
0.1uF
16
2
15
3
14
2
D8202
CDS3C30GTH
30V
VCC
6
D8203
CDS3C30GTH
30V
1
GND
+3.5V_ST
C1-
C2+
C8203
0.1uF
1
7
R8278
100
C8205
0.1uF
MAX3232CDR
C8201
0.1uF
Trace impedance : 100 ohm differenctial impedance to GND plane
5 mils trace width with 7 mils air gap on P/N pair.
Adjacent TX/RX differential pairs should be separated by more than
15 mils to each other
DOUT2
4
13
5
12
6
7
11
10
SPG09-DB-009
DOUT1
RIN1
JK8201
R8222
4.7K
OPT
R8223
4.7K
OPT
ROUT1
R8273 0
DIN1
R8274 0
BCM_RXD1
NEC_RXD
DIN2
R8272 0
BCM_TXD1
RIN2
8
9
ROUT2
R8275 0
NEC_TXD
EAN41348201
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
* HDMI CEC
E
E
13
CKCK-_HDMI1
CK_GND
CK+
CK+_HDMI1
D0-
9
D0-_HDMI1
D0_GND
8
12
11
JK830310
9
8
D0+
7
7
D0+_HDMI1
D1-
6
6
D1-_HDMI1
D1_GND
5
D1+
4
4
D1+_HDMI1
D2-
3
3
D2-_HDMI1
D2_GND
2
2
D2+
1
1
D2+_HDMI1
DDC_CLK
NC
CE_REMOTE
R8318
82
DDC_SDA_4
R8326
22K
DDC_SCL_4
GND
JP8307
D8312
CEC_REMOTE
MMBD301LT1G
CK-_HDMI4
CK_GND
HDMI_CEC
CEC_REMOTE
GND
CK+
CK+_HDMI4
D0D0-_HDMI4
D0_GND
D0+
D0+_HDMI4
D1D1-_HDMI4
D1_GND
D1+
D1+_HDMI4
D2-
+3.3V_HDMI
D2-_HDMI4
D2_GND
D2+
D2+_HDMI4
GND
UI_HW_PORT1
GND
D8311
5.5V
ESD
JP8306
CK-
KJA-ET-0-0032
YKF45-7058V
R8317
82
SIDE_HDMI_PORT4
C8311
14
CEC_REMOTE
DDC_DATA
C8310
0.1uF
GND
GND
C8309
0.1uF
15
JP8305
C8324
0.1uF
+3.5V_ST
C8308
0.1uF
R8308
0
NC
CE_REMOTE
5V_HDMI_4
C
1K
5V
100K
R8349
DDC_SCL_1
5V_HPD4
B
C8307
0.1uF
16
C
+3.3V_HDMI
L8300
BLM18PG121SN1D
C8305
0.1uF
17
JP8304
DDC_CLK
11
JK830210
5
DDC_SDA_1
B
R8321
4.7K
0.1uF
EAG59023302
12
D8305
5.5V
OPT
HDMI_HPD_4
KRC104S
Q8307
G
18
R8307
0
DDC_DATA
E
KRC104S
Q8306
R8316
HP_DET
C
GND
GND
GND
20
5V_HDMI_1
19
15
13
GND
5V_HPD1
1K
5V
16
14
C
B
EAG42463001
17
D8308
5.5V
ESD
D
B
S
Q8308
BSS83
R8302
HP_DET
19
18
E
KRC104S
Q8302
+3.3V_NORMAL
JACK_GND
HDMI_HPD_1
B
R8311
4.7K
5.6V
GND
20
KRC104S
Q8305
5.6V
D8314
CDS3C05HDMI1
SHIELD
GND
D8313
CDS3C05HDMI1
D8302
5.5V
OPT
33
33
33
33
33
R8331
R8332
R8333
R8334
4.7K
C8302
0.1uF
16V
DDC_SDA_4
DDC_SCL_4
OPT
R8328
DDC_SCL_3
D2+_HDMI2
3
2
1
DDC_SDA_4
HDMI_HPD_4
CK+_HDMI4
CK-_HDMI4
DDC_SCL_4
D0+_HDMI4
D0-_HDMI4
D1+_HDMI4
D1-_HDMI4
D2-_HDMI4
0
OPT
RXD_HPD
RXD_5V
RXD_DDC_DAT
RXD_DDC_CLK
RXD_C-
RXD_C+
VDDH[3V3]_7
RXD_D0-
RXD_D0+
VSS_10
RXD_D1-
RXD_D1+
RXD_D2-
RXD_D2+
VDDH[3V3]_8
76
77
78
79
80
81
82
83
84
85
86
87
88
RXA_C+
14
62
RXC_C-
VDDH[3V3]_1
15
61
RXC_DDC_CLK
RXA_D0-
16
60
RXC_DDC_DAT
RXA_D0+
17
59
RXC_5V
VSS_3
18
58
RXC_HPD
RXA_D1-
57
CEC
D1-_HDMI1
19
RXA_D1+
20
56
VSS_7
D1+_HDMI1
VDDH[3V3]_2
21
55
VDDS[3V3]
RXA_D2-
22
PD
I2C_SCL
I2C_SDA
R8336 0 TEST2
VDDDC[1V8]_4
VSS_6
RXB_D2+
CDEC_DDC
RXB_D2-
RXB_D1+
VSS_5
RXB_D1-
RXB_D0+
RXB_D0-
RXB_C+
VDDDC[1V8]_2
0
VDDH[3V3]_4
C8300
0.1uF
VDDH[3V3]_3
DDC_SDA_3
DDC_CLK
RXB_C-
R8327
D8304
5.5V
OPT
JP8302
RXB_DDC_CLK
C
R8305
0
D0+_HDMI3
D0-_HDMI3
CK+_HDMI3
CK-_HDMI3
DDC_SCL_3
DDC_SDA_3
HDMI_HPD_3
Ready for TDA19997
+3.3V_HDMI
R8346
0
OPT
OPT
R8347
4.7K
OPT
C8315
0.1uF
50
49
48
47
46
RXE_DDC_CLK
45
51
44
25
43
AUX_5V
42
RXE_DDC_DAT
41
INT_N/MUTE
52
40
53
24
39
23
38
54
RXA_D2+
VDDH[1V8]_1
5V_HDMI_3
D1+_HDMI3
D1-_HDMI3
R8345
0
OPT
CDEC_STBY
4.7K
R8348
0 OPT
R8343
DDC_SCL_3
R8306
0
NC
JP8303
GND
C8313
0.1uF
16V
CE_REMOTE
CEC_REMOTE
CKCK-_HDMI3
CK_GND
5V_HDMI_2
+1.8V_HDMI
CK+
C8314
0.1uF
16V
CK+_HDMI3
C8301
0.1uF
16V
C8303
0.1uF
16V
C8304
0.1uF
16V
D0+
D0+_HDMI3
R8340
22
D0-_HDMI3
D0_GND
R8338 22
C8306
0.1uF
16V
D0-
R8337
0
D1D1-_HDMI3
D1_GND
D1+
D1+_HDMI3
D2D2-_HDMI3
D2_GND
D2+
HDMI2
D2+_HDMI3
SDA2_3.3V
4
89
RXC_C+
D2+_HDMI3
D2-_HDMI3
SCL2_3.3V
5
90
63
D2-_HDMI1
D2+_HDMI1
C8317
0.1uF
16V
D2-_HDMI2
D2+_HDMI2
6
VDDDC[1V8]_3
13
D1+_HDMI2
7
VSS_11
RXA_C-
D1-_HDMI2
8
91
VDDH[3V3]_5
DDC_SCL_1
CK-_HDMI1
D0+_HDMI2
9
92
RXC_D0-
64
D0-_HDMI2
11
JK830110
93
65
12
CK+_HDMI2
EAG59023302
12
OUT_D2+
RXC_D0+
11
DDC_SCL_2
CK-_HDMI2
13
OUT_D2-
66
IC8300
TDA19997
DDC_SDA_2
14
VDDO[1V8]
VSS_8
9
HDMI_HPD_2
15
94
RXC_D1-
67
8
+5V_NORMAL
16
95
RXC_D1+
68
7
RXA_HPD
GND
DDC_DATA
OUT_D1+
69
VSS_2
VDDDC[1V8]_1
1K
5V
OUT_D1-
VDDH[3V3]_6
10
5V_HPD3
B
RXC_D2-
70
37
C
KRC104S
Q8301
R8301
HP_DET
RXC_D2+
71
6
26
GND
20
72
5
VSS_4
SHIELD
B
R8310
4.7K
4
OUT_DDC_DAT
RXA_5V
CK+_HDMI1
HDMI_HPD_3
KRC104S
Q8304
VDDO[3V3]
OUT_DDC_CLK
RXA_DDC_CLK
E
E
5V_HDMI_3
12K
RXA_DDC_DAT
D0-_HDMI1
GND
VSS_9
DDC_SDA_1
D0+_HDMI1
D8301
5.5V
OPT
VDDH[1V8]_2
R8344
R12K
73
75
36
EDID Pull-up
UI_HW_PORT3
GND
74
3
35
D2+
2
34
DDC_SDA_3
1
33
47K
R8323
VSS_1
OUT_C-
32
D2-_HDMI2
C8323
0.1uF
16V
HDMI3
Place close
to
TDA9996
OUT_C+
31
D1+_HDMI2
D2D2_GND
R8320
4.7K
R8315
0
17
D2+_HDMI4
R8339
5V_HDMI_1
D1_GND
R8313
47K
C8318
0.1uF
16V
C8316
0.1uF
16V
HDMI1
D8310
D1-_HDMI2
D1+
VSS_12
5V_HPD4
5V_HPD3
D8307
96
D0+_HDMI2
D1-
OUT_D0+
D0+
HDMI_3
YKF45-7058V
18
HDMI_RX2+
HDMI_RX2-
HDMI_RX1+
HDMI_RX1-
HDMI_RX0+
33
R8330
OUT_D0-
D0_GND
HDMI_HPD_1
19
HDMI_RX0-
HDMI_CLK+
HDMI_CLK-
HDMI_SCL
A1
A2
+5V_NORMAL
5V_HDMI_4
97
+5V_NORMAL
5V_HDMI_3
D0-_HDMI2
98
CK+_HDMI2
D0-
99
CK+
30
1
CK-_HDMI2
CK_GND
RXB_DDC_DAT
2
CK-
29
3
+1.8V_HDMI
CEC_REMOTE
RXB_5V
4
0.1uF
OPT
5
DDC_SCL_2
100
6
DDC_SDA_2
GND
28
7
CE_REMOTE
JP8301
27
8
DDC_SCL_2
R8304
0
HDMI_3
NC
TEST1
9
DDC_SDA_1
DDC_SCL_1
DDC_CLK
RXB_HPD
11
JK830010
DDC_SDA_2
R8324
1.8K
47K
HDMI_3
C8312
0.1uF
16V
R8335
0
EAG59023302
12
JP8300
R8322
R8319
47K
HDMI_3
47K
A1
13
DDC_DATA
R8314
R8312
47K
D8303
5.5V
OPT
A2
14
HDMI_3
R8303
0
0.1uF
C8321
5V_HDMI_4
0.1uF
C8322
C
15
GND
0.1uF
C8320
R8325
1.8K
C
A1
16
+5V_NORMAL
HDMI_3
D8309
1K
5V
A2
17
5V_HPD2
5V_HPD1
D8306
5V_HDMI_2
C
18
C
B
R8329
HP_DET
19
GND
E
HDMI_3
KRC104S
Q8300
C8319
C
HDMI_3 GND
R8300
20
HDMI_HPD_2
B
R8309 HDMI_3
5V_HPD2
4.7K
A1
SHIELD
HDMI_3
KRC104S
Q8303
+5V_NORMAL
5V_HDMI_2
C
D8300
5.5V
OPT
A2
+5V_NORMAL
5V_HDMI_1
E
HDMI_SDA
HDMI4
YKF45-7058V
GND
UI_HW_PORT2
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BCM (EUROBBTV)
LEE GI YOUNG
HDMI
2009.06.18
8
LGE Internal Use Only
RGB PC
A0
E2 3
D2A
VSS 4
5
SDA
R8405
22
2.7K
6
SCL
R8420
10K
R8422
100
OPT
RGB_DDC_SCL
R8415
22
RGB_DDC_SDA
22
+3.3V_NORMAL
OPT
D8408
CDS3C05HDMI1
5.6V
OPT
R8424
10K
1K
R8425
L8408 60-ohm
DSUB_B
DSUB_DET
RGB_BEAD
L8409 60-ohm
DSUB_G
OPT
0
R8423
L8410-*1 0
GND
Fiber Optic
1
10
4
3
2
1
JK8400
JST1223-001
JP8401
JP8402
VCC
2
VINPUT
3
R8400
1K
SPDIF_OUT
C8400
0.1uF
16V
4
JP8400
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SPG09-DB-010
JK8402
RGB_0OHM
+3.3V_NORMAL
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
5
9
8
7
6
RGB_0OHM
RGB IN
16
RGB_0OHM
L8409-*1 0
OPT
C8409
D8411
100pF
5.6V
50V
ADMC5M03200L_AMODIODE
SHILED
DDC_CLOCK
V_SYNC
SYNC_GND
DDC_GND
15
H_SYNC
NC
BCM Reference
D8402 D8404 D8405
30V
30V
30V
L8408-*1 0
GND_1
R8407
75
14
R8404
75
BLUE_GND
RGB_BEAD
R8403
75
BLUE
RGB_BEAD
L8410 60-ohm
DSUB_R
D8400
30V
OPT
EDID_WP
R8416
OPT
D8410
CDS3C05HDMI1
5.6V
C8403
22pF
50V
R8406
22
BCM Reference
7
WC
RGB_EDID_ST
C8402
22pF
50V
8
VCC
0IMMR00014A
D8403
ADUC30S03010L_AMODIODE
30V
7
Q2
D8401
ADUC30S03010L_AMODIODE
30V
GND
8
R8421
0
E1 2
GREEN
9
D2B
13
6
10
E0 1
DDC_DATA
Q1
5
IC8401
M24C02-RMN6T
Q3
12
D1B
A2
RGB_EDID_RENESAS
R8414
11
C
SDA
R8417
0
4
5
GREEN_GND
R8402
22
4
RED
D1A
RGB_VSYNC
D3A
SCL
DEV
VSS
11
12
6
D8409
ENKMC2838-T112
A1
2.7K
3
3
WP
GND_2
RGB_HSYNC
Q0
C8401
0.1uF
+5V_NORMAL
VCC
R8413
R8401
22
D3B
7
C8406
18pF 50V
13
8
2
RED_GND
14
2
A2
D0B
1
C8404
0.1uF
16V
1
A1
VCC
C8405
18pF 50V
D0A
IC8401-*1
R1EX24002ASAS0A
+5V_NORMAL
IC8400
74F08D
FIX_POLE
RGB AUDIO IN
JK8401
PEJ027-01
3
E_SPRING
6A
T_TERMINAL1
7A
B_TERMINAL1
C8407
PC_R_IN
4
R_SPRING
5
T_SPRING
7B
B_TERMINAL2
6B
T_TERMINAL2
D8406
AMOTECH
5.6V
R8411
470K
1uF
25V
R8418
0
C8408
PC_L_IN
D8407
AMOTECH
5.6V
R8412
470K
1uF
25V
R8419
0
EUROBBTV
ETC SUB BOARD I/F
2009.06.18
9
LGE Internal Use Only
ALL for SIDE_GENDER option
SIDE CVBS PHONE JACK
(New Item Developmen)
SIDE_AV_CVBS
R8603
0
C8605
47pF
50V
D8600
5.5V
JK8600
KJA-PH-1-0177
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
+3.3V_NORMAL
R8605
10K
SIDE_AV_DET
D8601
5.6V
R8608
1K
C8600
100pF
50V
C8607
25V
R8606
0
SIDE_AV_L_IN
1uF
D8602
5.6V
C8611
100pF
50V
R8601
470K
C8606
25V
R8607
0
SIDE_AV_R_IN
1uF
D8603
5.6V
R8602
470K
C8612
100pF
50V
SIDE COMPONENT PHONE JACK
(New Item Developmen)
L8600
270nH
SIDE_COMP_Y
D8064
5.1V
D8068
5.1V
C8608
27pF
50V
C8601
27pF
50V
+3.3V_NORMAL
Near J
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
R8600
10K
Run Along SIDE_COMP_Y_IN,SIDE_COMP_Pr_IN,SIDE_COMP_Pb_IN Trace
R8604
1K
0.1uF
SIDE_COMP_INCM
R8609
36
C8613
JK8601
KJA-PH-1-0177
SIDE_COMP_DET
C8604
100pF
50V
D8606
5.6V
L8602
270nH
SIDE_COMP_Pb
D8607
5.5V
C8603
27pF
50V
C8610
27pF
50V
L8601
270nH
SIDE_COMP_Pr
D8605
5.5V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C8602
27pF
50V
C8609
27pF
50V
11
SIDE_GENDER
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
WIRELESS READY MODEL
JK8700
KJA-PH-3-0168
Wireless power
VCC[24V/20V/17V]_1
VCC[24V/20V/17V]_2
VCC[24V/20V/17V]_3
VCC[24V/20V/17V]_4
VCC[24V/20V/17V]_5
+24V
VCC[24V/20V/17V]_6
From wireless_I2C to micom I2C
DETECT
+3.3V_NORMAL
R8704
22K
C8700
0.1uF
50V
+3.3V_NORMAL
INTERRUPT
C8701
2.2uF
TP8700
GND_1
R8714
10K
S
RESET
R8705
2.2K
10K
R173
OPT
G
Q8701
R8713
AO3407A
D
TP8701
1K
GND_2
WIRELESS_DETECT
L8700
I2C_SCL
R8702
10K
WIRELESS_PWR_EN
C
MLB-201209-0120P-N2
B
WIRELESS_SCL
I2C_SDA
WIRELESS_SDA
Q8700
C8702
0.01uF
50V
C8705
10uF
WIRELESS_RX
35V
UART_RX
UART_TX
WIRELESS_TX
S
GND_4
IR
SDA2_3.3V
IR_PASS
G
D
WIRELESS_SDA
C8704
10uF
35V
G
E
Q103
FDV301N
GND_3
OPT
GND_5
D
WIRELESS_SCL
S
Q104
FDV301N
GND_6
SCL2_3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OPT
21
R123
R124
0 WIRELESS
0
SHIELD
+3.5V_ST
WIRELESS
NON_WIRELESS
0
R8703
WIRELESS
R8707
0
IC8700
MC14053BDR2G
WIRELESS
R8700
WIRELESS_DL_RX
0
Y1
WIRELESS_TX
1
WIRELESS
16
VDD
RS232C & Wireless
C8703
15
3
14
Y
X
BCM_TXD1
BCM_RXD1
R8708
Z
Z0
INH
R8701
0
VEE
4
13
5
12
6
11
7
10
8
9
X1
0.1uF
0
WIRELESS
WIRELESS_DL_TX
WIRELESS_SW_CTRL
SELECT PIN
STATUS
WIRELESS_RX
X0
R8706
0 NON_WIRELESS
+3.5V_ST
HIGH
X1/Y1/Z1
WIRELESS Dongle connect --> WIRELESS RS232
LOW
X0/Y0/Z0
WIRELESS Dongle Dis_con --> S7 RS232
BCM_RX
A
OPT
Z1
2
B
4.7K
R8711
Y0
BCM_TX
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C
47K
R8712
VSS
OPT
WIRELESS
WIRELESS_SW_CTRL
12
WIRELESS
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
+24V_AMP
+24V
L8803
MLB-201209-0120P-N2
C8827
0.1uF
50V
+1.8V_AMP
+3.3V_NORMAL
CCFL = 20V
IC8800
IN
3 Vd=1.4V 1
R8800
1
AP1117E18G-13
ADJ/GND
Edge_LED 32~47 Inch = 20V
120 mA
2
C8800
0.1uF
16V
OUT
55 Inch & IOP Module = 24V
C8803
0.1uF
16V
C8802
10uF
10V
+24V_AMP
SPK_L+
D8800
1N4148W
100V
OPT
EMI
R8809
3.3
C8819
22000pF
50V
AUD_LRCK
AUD_SCK
SDA1_3.3V
SCL1_3.3V
R8802
PVDD1B_2
PVDD1B_1
OUT1B_2
OUT1B_1
PGND1B_2
PGND1B_1
BST1B
VDR1B
48
47
46
45
44
43
PVDD1A_1
49
PVDD1A_2
OUT1A_1
OUT1A_2
PGND1A_1
51
50
52
53
PGND1A_2
PGND2A_2
38
PGND2A_1
6
37
OUT2A_2
CLK_I
7
36
OUT2A_1
VDD_IO
8
35
PVDD2A_2
34
PVDD2A_1
33
PVDD2B_2
32
PVDD2B_1
C8810
1000pF
50V
DGND_PLL
9
R8806
AGND_PLL
10
LF
11
IC8801
EAN60969601
NTP-7000
4.7K
SPEAKER_L
C8839
0.47uF
50V
C8842
0.1uF
50V
15uH
R8817
12
R8821
4.7K
SPK_R+
C8830
22000pF
D8802
1N4148W
100V
OPT
50V
R8814
12
R8818
12
L8804
AD-9060
2S
2F
1S
C8838
390pF
50V
D8803
1N4148W
100V
OPT
R8815
12
1F
15uH
R8816
12
C8840
0.47uF
50V
C8843
R8822
0.1uF
50V
4.7K
C8844
R8823
0.1uF
50V
4.7K
SPEAKER_R
SPK_R-
28
+24V_AMP
PGND2B_1
27
BST2B
26
25
VDR2B
/FAULT
MONITOR2
MONITOR1
MONITOR0
SCL
SDA
BCK
WCK
SDATA
C8818
0.1uF
16V
24
PGND2B_2
23
29
22
14
21
GND
20
OUT2B_1
19
30
18
13
17
31
DVDD_PLL
16
12
OUT2B_2
C8807
0.1uF
16V
R8813
12
C8837
390pF
50V
AVDD_PLL
OPT
C8815
10uF
10V
R8801
54
EP_PAD
39
+1.8V_AMP
AUD_LRCH
C8828
25V1uF
5
15
OPT
C8805
10uF
10V
1F
C8836
390pF
50V
D8801
1N4148W
100V
OPT
GND_IO
3.3K
C8804
0.1uF
16V
4
AD
THERMAL
57
3
DGND_2
OPT
C8801
10uF
10V
100pF
50V
BST2A
DGND_1
L8801
C8806
VDR2A
40
2
C8811
0.1uF
BLM18PG121SN1D
BLM18PG121SN1D
L8800
NC
41
1
+1.8V_AMP
2F
1S
R8820
C8825
1uF
25V
42
BST1A
VDR1A
25V /RESET
C8816
1uF
55
56
C8808
1000pF
50V
AUD_MASTER_CLK
2S
C8841
0.1uF
50V
SPK_L-
L8802
AMP_RESET_N
L8805
AD-9060
C8823
22000pF
50V
DVDD
BLM18PG121SN1D
+3.3V_NORMAL
+1.8V_AMP
C8824
0.1uF
50V
C8820
0.1uF
50V
C8835
390pF
50V
EMI
C8832
0.01uF
50V
C8826
10uF
35V
R8819
12
R8812
12
C8822
1uF
25V
C8831
C8833
0.1uF
50V
0.1uF
50V
C8834
10uF
35V
C8829
22000pF
50V
100
R8807
0
100
R8803
100
R8804
100
R8805
100
POWER_DET
C8821
1000pF
50V
OPT
+3.5V_ST
C8809
33pF
50V
C8812
33pF
50V
C8813
47pF
50V
EMI
C8814
47pF
50V
EMI
C8817
47pF
50V
EMI
R8808
100
WAFER-ANGLE
R8810
10K
R8824
0
C
B
Q8800
2SC3052
R8811
SPK_L+
4
AMP_MUTE
R8825
0
10K
E
SPK_L-
3
R8826
0
SPK_R+
2
R8827
0
SPK_R-
1
P8800
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BCM (EUROBBTV)
KIM JONG HYUN
NTP7000
2009.06.18
38
LGE Internal Use Only
IC9701
LG5111
A3
LVDS_TX_0_DATA0_P
A2
LVDS_TX_0_DATA0_N
A4
LVDS_TX_0_DATA1_P
B3
LVDS_TX_0_DATA1_N
B1
LVDS_TX_0_DATA2_P
B2
LVDS_TX_0_DATA2_N
C2
LVDS_TX_0_CLK_P
C1
LVDS_TX_0_CLK_N
C3
LVDS_TX_0_DATA3_P
D3
LVDS_TX_0_DATA3_N
D1
LVDS_TX_0_DATA4_P
D2
LVDS_TX_0_DATA4_N
A17
R1A1P
T1A1P
R1A1M
T1A1N
R1B1P
T1B1P
R1B1M
T1B1N
R1C1P
T1C1P/RLV0N
R1C1M
T1C1N/RLV0P
R1CLK1P
T1CLK1P/RLV1N
R1CLK1M
T1CLK1N/RLV1P
R1D1P
T1D1P
R1D1M
T1D1N
R1E1P
T1E1P/RLV2N
R1E1M
T1E1N/RLV2P
E2
LVDS_TX_1_DATA0_P
E1
LVDS_TX_1_DATA0_N
E3
LVDS_TX_1_DATA1_P
F3
LVDS_TX_1_DATA1_N
F1
LVDS_TX_1_DATA2_P
F2
LVDS_TX_1_DATA2_N
G1
LVDS_TX_1_CLK_P
G2
LVDS_TX_1_CLK_N
H1
LVDS_TX_1_DATA3_P
H2
LVDS_TX_1_DATA3_N
J1
LVDS_TX_1_DATA4_P
J2
LVDS_TX_1_DATA4_N
RRXA0-
B16
T1A2P/RCLKN
R1A2M
T1A2N/RCLKP
R1B2P
T1B2P
R1B2M
T1B2N
R1C2P
T1C2P
R1C2M
T1C2N
R1CLK2P
T1CLK2P/RLV3N
R1CLK2M
T1CLK2N/RLV3P
R1D2P
T1D2P/RLV4N
R1D2M
T1D2N/RLV4P
R1E2P
T1E2P/RLV5N
R1E2M
T1E2N/RLV5P
C9704
27pF
50V
RRXA1+
A15
RRXA1-
B17
C9707
27pF
50V
G3
H3
C18
RRXACK+/RLV4P
C17
R9741
RRXACK-/RLV4N
D16
1M
J3
IC9701
LG5111
RRXA2-/RLV5N
K3
L3
1%
M3
RRXA3+
C16
RRXA3-
D17
A5
B5
RRXA4+/RLV3P
D18
RRXA4-/RLV3N
TMODE3
CLK25_XIN
TMODE2
TMODE1
RRXB0+/RLCLKP
E17
RRXB0-/RLCLKN
F16
RRXB1+
E16
RRXB1-
F17
RRXB2+
F18
RRXB2-
G18
RRXBCK+/RLV2P
G17
M0_SCLK
R9742
22
A7
M0_MOSI
R9743
22
B7
M1_SCLK
R9744
22
A6
M1_MOSI
R9745
22
B6
M2_SCLK
R9746
22
R6
M2_MOSI
R9747
22
T6
M3_SCLK
R9748
22
U6
22
V6
R9749
M3_MOSI
RRXBCK-/RLV2N
H18
M1_MOSI
GPIO1
M2_SCLK
GPIO2
M2_MOSI
GPIO3
M3_SCLK
GPIO4
M3_MOSI
GPIO5
B8
S_SCLK
RRXB4-/RLV0N
B9
S_MOSI
K2
L1
S_SCLK
S_MOSI
L2
M1
M2
N2
N1
N3
Close to LG5111 LVDS Input PIN
P3
P1
P2
K18
R2A1P
T2A1P
R2A1M
T2A1N
R2B1P
T2B1P/LLV0N
R2B1M
T2B1N/LLV0P
R2C1P
T2C1P/LLV1N
R2C1M
T2C1N/LLV1P
R2CLK1P
T2CLK1P/LLV2N
R2CLK1M
T2CLK1N/LLV2P
R2D1P
T2D1P
R2D1M
T2D1N
R2E1P
T2E1P/LCLKN
R2E1M
K17
VS_SLAVE_MODE
L18
/TCON_EN
R_VS
EEPROM_WP
L17
R9750
V5
DUAL_LVDS
+3.3V_NORMAL
M18
M17
V_SYNC
L_VS
P16
R9751
A10
A12
P17
A13
P18
T2E1N/LCLKP
B4
LVDS_TX_0_DATA0_P
R9704
100
LVDS_TX_0_DATA0_N
LVDS_TX_0_DATA1_P
R9705
100
LVDS_TX_0_DATA1_N
B10
B11
LVDS_TX_0_DATA2_P
R9706
100
LVDS_TX_0_DATA2_N
R2
LVDS_TX_0_CLK_P
R9707
100
LVDS_TX_0_CLK_N
R1
LVDS_TX_0_DATA3_P
R9708
100
LVDS_TX_0_DATA3_N
R3
LVDS_TX_0_DATA4_P
R9709
100
LVDS_TX_0_DATA4_N
T3
T1
T2
U2
U1
LVDS_TX_1_DATA0_P
R9710
100
LVDS_TX_1_DATA0_N
U3
LVDS_TX_1_DATA1_P
R9711
100
LVDS_TX_1_DATA1_N
V4
LVDS_TX_1_DATA2_P
R9712
100
LVDS_TX_1_DATA2_N
V2
LVDS_TX_1_CLK_P
R9713
100
LVDS_TX_1_CLK_N
LVDS_TX_1_DATA3_P
R9714
100
LVDS_TX_1_DATA3_N
LVDS_TX_1_DATA4_P
R9715
100
LVDS_TX_1_DATA4_N
V3
LG5111_RESET
R18
R2A2P
T2A2P
R2A2M
T2A2N
R2B2P
T2B2P
R2B2M
T2B2N
R2C2P
T2C2P/LLV3N
R2C2M
T2C2N/LLV3P
R2CLK2P
T2CLK2P/LLV4N
R2CLK2M
T2CLK2N/LLV4P
R2D2P
T2D2P
R2D2M
T2D2N
R2E2P
T2E2P/LLV5N
R2E2M
T2E2N/LLV5P
B12
R17
M15
R11
R9716 0
R13
M16
V_SYNC
N15
3D_DIMMING_2
R14
3D_DIMMING
P15
T8 R9759
U8
EEPROM_WP
EEPROM_NA
V8
C4
+1.8V_VDD
EEPROM_A1
TCON_EN
R_VS
M_SDA
DUAL_LVDS
M_SCL
VS_IN
S_SDA
L_VS
S_SCL
U7 R9760
V7 R9761
D6
22
M_SDA
D13
22
M_SCL
G7
U9 R9762
V9 R9763
H7
22
SDA3_3.3V
H12
22
SCL3_3.3V
J7
J12
H_CONV
DPM
K7
V10
SOE
UARTRXD
PORES_N
UARTTXD
U10R9764
22
UART_RXD
UART_TXD
K12
L7
L12
OPT_N
POL
T11
TMS
T16
TCK
R16
TDI
T17
TDO
T18
U11
V12
U12
V11
TRST_N
U18
M7
TMS
M8
TCK
M9
TDI
TDO
M10
M11
TRST_N
M12
RX_GND_5
RXVDD_18_6
RX_GND_6
TXVDD_18_1
TX_GND_1
TXVDD_18_2
TX_GND_2
TXVDD_18_3
TX_GND_3
TXVDD_18_4
TX_GND_4
TXVDD_18_5
TX_GND_5
TXVDD_18_6
TX_GND_6
TXVDD_18_7
TX_GND_7
TXVDD_18_8
TX_GND_8
TXVDD_18_9
TX_GND_9
V15
GCLK1[GSP_R]
U16
GCLK2
A14
V16
B13
V17
B14
VDD_ODD[GSC]
GCLK3
VDD_EVEN[GOE] GCLK4[OPT_P]
VST[GSP]
GCLK5
RMLVDS
GCLK6
C7
U13
C8
T13
T14
V14
U14
C9
C10
C11
C12
R9739
12K
D7
D9
D10
[Mini-LVDS Signal Strength]
1. Adjust Mini-LVDS Tx voltage swing level
(swing level can be affected by FFC cable)
2. Add resistor and make option for each model
D11
D12
G8
G9
G10
G11
+3.3V_NORMAL
[+1.8V for LG5111]
+12V
IC9702
AOZ1072AI
H4
C9712
0.1uF
16V
J4
120-ohm
R9730
10K
TM240Hz
PGND
Dual/Quad-Link LVDS Input Selection
- High : Dual-Link LVDS(TM480Hz,LE9500)
- LOW : Quad-Link LVDS
(TM240Hz, LE5500/7500/8500)
C9702
10uF
25V
C9703
10uF
25V
C9776
0.1uF
AGND
16V
FB
+3.3V_NORMAL
8
2
7
3
6
4
5
+3.3V_NORMAL
LX_2
LX_1
+3.3V_NORMAL
R9740
10K
EN
R9738
9.1K
C9709
22uF
10V
C9719
0.1uF
16V
C9725
0.1uF
16V
C9732
0.1uF
16V
C9739
0.1uF
16V
C9746
0.1uF
16V
C9751
0.1uF
16V
C9757
0.1uF
16V
C9764
0.1uF
16V
C9769
0.1uF
16V
C9720
0.1uF
16V
C9726
0.1uF
16V
C9733
0.1uF
16V
C9740
0.1uF
16V
C9747
0.1uF
16V
C9752
0.1uF
16V
C9758
0.1uF
16V
C9765
0.1uF
16V
C9770
0.1uF
16V
C9721
0.1uF
16V
C9727
0.1uF
16V
C9734
0.1uF
16V
C9741
0.1uF
16V
C9748
0.1uF
16V
C9753
0.1uF
16V
C9759
0.1uF
16V
C9766
0.1uF
16V
C9771
0.1uF
16V
C9722
0.1uF
16V
C9728
0.1uF
16V
C9735
0.1uF
16V
C9742
0.1uF
16V
C9749
0.1uF
16V
C9754
0.1uF
16V
C9760
0.1uF
16V
C9767
0.1uF
16V
C9772
0.1uF
16V
C9723
0.1uF
16V
C9729
0.1uF
16V
C9736
0.1uF
16V
C9743
0.1uF
16V
C9750
0.1uF
16V
C9755
0.1uF
16V
C9761
0.1uF
16V
TXVDD_18_10
TX_GND_10
TXVDD_18_11
TX_GND_11
TXVDD_18_12
TX_GND_12
+1.8V_TXVDD
H14
H15
C9713
0.1uF
16V
J14
K15
L14
L15
M14
+1.8V_VDD
N14
GND_1
PLL2_AVDD
GND_2
C9714
0.1uF
16V
GND_3
VDD_18_1
GND_4
VDD_18_2
GND_5
VDD_18_3
GND_6
VDD_18_4
GND_7
VDD_18_5
GND_8
VDD_18_6
GND_9
VDD_18_7
GND_10
VDD_18_8
GND_11
VDD_18_9
GND_12
VDD_18_10
GND_13
VDD_18_11
GND_14
VDD_18_12
GND_15
VDD_18_13
GND_16
VDD_18_14
GND_17
VDD_18_15
GND_18
VDD_18_16
GND_19
VDD_18_17
GND_20
VDD_18_18
GND_21
VDD_18_19
GND_22
VDD_18_20
GND_23
GND_24
VDD_33_1
GND_25
VDD_33_2
GND_26
VDD_33_3
GND_27
VDD_33_4
GND_28
VDD_33_5
GND_29
VDD_33_6
GND_30
VDD_33_7
GND_31
VDD_33_8
GND_32
VDD_33_9
GND_33
VDD_33_10
GND_34
VDD_33_11
GND_35
VDD_33_12
GND_36
VDD_33_13
GND_37
VDD_33_14
GND_38
VDD_33_15
GND_39
VDD_33_16
GND_40
VDD_33_17
GND_41
VDD_33_18
GND_42
D4
D5
D14
D15
E5
E14
+1.8V_VDD
F4
F5
G5
C9715
0.1uF
16V
H5
H8
H9
H10
H11
J5
J8
+3.3V_VDD
J9
J10
J11
C9716
0.1uF
16V
K5
K8
K9
K10
K11
L5
L8
+3.3V_VDD
L9
L10
L11
C9717
0.1uF
16V
M5
N4
N5
P5
P14
+1.8V_L/DIMMING
+1.8V_RXVDD +1.8V_TXVDD +1.8V_PLL
+1.8V_VDD
+3.3V_VDD
+3.3V_NORMAL
R15
T7
T9
T10
L9702
120-ohm
L9703
120-ohm
L9704
120-ohm
L9705
120-ohm
L9706
120-ohm
T12
T15
C9774
10uF
10V
U15
C9730
10uF
10V
C9737
10uF
10V
C9744
10uF
10V
C9756
10uF
10V
[JTAG for LG5111]
R9756
10K
1%
R2
[UART for LG5111]
R9766
TDO
22
R9765
22
TDI
R9767
22
TCK
R9768
22
TMS
R9769
22
TRST_N
FOr Debugging
3
Write Protection
Low : Normal Operation
High : Write Protection
4
[RESET for LG5111]
+3.3V_NORMAL
C9706
0.1uF
16V
+3.3V_NORMAL
R9735
3.3K
1K
R9774
10K
10K
R9775
E0
5
.
1
8
2
7
3
6
4
5
VCC
R9752
3.3K
OPT
R9757
2K
I
1
3
O
R9734
22
E1
LG5111_RESET
EEPROM_A1
WC
EEPROM_WP
OPT
2
C9700
0.1uF
16V
UART_TXD
R9758
2K
3
KIA7027AF
22
UART_RXD
1K
OPT
10K
IC9700
R9773
10K
R9776
TX
IC9703
M24512-WMW6G(REV.B)
R9733
R9728
SW9700
JTP-1127WEM
R9772
10K
RX
C9763
0.1uF
16V
M_SCL
+3.3V_NORMAL
R9771
GND
R9367 OPT22
I2C Slave Address : 0xA4
+3.3V_NORMAL
+3.3V
M_SDA
[EEPROM for LG5111]
+3.3V_NORMAL
12505WS-04A00
R9366 OPT22
External Serial EEPROM Avalibility
- High : Not Available
- LOW : Use EEPROM
2
1
C9775
0.1uF
16V
K14
1
4
C9773
0.1uF
16V
J15
P9701
Master/Slave Mode Selection
- High : Slave Mode(TM480Hz,LE9500)
- LOW : Master Mode
(TM240Hz,LE5500/7500/8500)
2
C9768
0.1uF
16V
G14
C15
PLL_AVDD
R9732
10K
R9777
330
C9762
0.1uF
16V
C9710
0.1uF
16V
C9708
2200pF
C9705
1000pF
50V
EEPROM_NA
R9703
10K
TM240Hz
R9754
10.5K
1%
R9755
2K
1%
COMP
EAN60922901
VS_SLAVE_MODE
C9745
0.1uF
16V
L9701
3.6uH
R9731
3.3K
OPT
R9702
3.3K
TM480Hz
C9738
0.1uF
16V
R1
VIN
TX Output Mode Selection
- High : LVDS(TM480Hz, LE9500)
- LOW : Mini-LVDS
(TM240Hz, LE5500/7500/8500)
1
C9731
0.1uF
16V
M4
DUAL_LVDS
R9701
10K
TM240Hz
C9724
0.1uF
16V
L4
+1.8V_L/DIMMING
Vout = 0.8*(1+R1/R2)
L9700
C9718
0.1uF
16V
K4
F14
C6
V13
D8
/TCON_EN
RXVDD_18_5
+3.3V_VDD
U17
B15
R9729
3.3K
TM480Hz
RX_GND_4
C5
C14
FLK
EAN60997801
R9700
3.3K
TM480Hz
RX_GND_3
RXVDD_18_4
E4
22
C13
+3.3V_NORMAL
RX_GND_2
RXVDD_18_3
+1.8V_PLL
VS_SLAVE_MODE
A9
22
A11
N16
L16
R10
G12
R9737
3.3K
TM240Hz
N18
N17
U5
22
K16
R9
EEPROM_A1
R5
T5
J16
R8
R12
RX_GND_1
RXVDD_18_2
S_CS
EEPROM_NA
K1
H16
GPIO7
A8
S_CS_N
RRXB4+/RLV0P
J17
G15
G16
GPIO0
GPIO6
RRXB3-/RLV1N
J18
F15
U4
R7
M1_SCLK
RXVDD_18_1
E15
T4
M0_SCLK
RRXB3+/RLV1P
H17
R4
TMODE0
M0_MOSI
G4
+1.8V_TXVDD
P4
CLK25_XOUT
+1.8V_PLL
+1.8V_RXVDD
+1.8V_RXVDD
X9700
25MHz
RRXA2+/RLV5P
B18
E18
R1A2P
IC9701
LG5111
RRXA0+
A16
G
C9701
4.7uF
10V
R9736
10K
OPT
E2
VSS
SCL
M_SCL
SDA
M_SDA
R9753
10K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
COMMON_LD_400/480HZ
LG5111 (L.D.) from BCM
09/10/13
97
LGE Internal Use Only
002:AI32
002:F32
002:F32
002:AI32
DDR_BA0 002:F36;002:U33;002:AI36;002:BB34
DDR_BA1 002:F36;002:U33;002:AI36;002:BB33
DDR_DM3
DDR_DM2
DDR_DM1
DDR_DM0
DDR_RAS 002:F34;002:U31;002:AI34;002:BB32
DDR_CAS 002:F34;002:U32;002:AI34;002:BB32
DDR_ODT
002:AI32
002:AI33
002:AI32
002:AI33
DDR_CS 002:F34;002:U33;002:AI34;002:BB33
DDR_WE 002:F34;002:U32;002:AI34;002:BB32
DDR_CKE
DDR_DQS3
DDR_DQS3
DDR_DQS2
DDR_DQS2
002:F33
002:F32
002:F33
002:F32
DDR_DQS0
DDR_DQS1
DDR_DQS1
002:F35;002:AI35
DDR_CLK 002:F35;002:AI35
DDR_CLK
DDR_DQS0
DDR_DATA[31]
DDR_DATA[30]
DDR_DATA[29]
DDR_DATA[28]
DDR_DATA[27]
DDR_DATA[26]
DDR_DATA[25]
DDR_DATA[24]
DDR_DATA[23]
DDR_DATA[22]
DDR_DATA[21]
DDR_DATA[20]
DDR_DATA[19]
DDR_DATA[18]
DDR_DATA[17]
DDR_DATA[16]
DDR_DATA[15]
DDR_DATA[14]
DDR_DATA[13]
DDR_DATA[9]
DDR_DATA[12]
DDR_DATA[8]
DDR_DATA[11]
DDR_DATA[7]
DDR_DATA[10]
DDR_DATA[6]
DDR_DATA[5]
DDR_DATA[4]
DDR_DATA[3]
DDR_DATA[0-31]
002:N40;002:AQ40
DDR_DATA[2]
DDR_DATA[1]
DDR_DATA[0]
DDR_ADDR[9]
DDR_ADDR[12]
DDR_ADDR[8]
DDR_ADDR[11]
DDR_ADDR[7]
DDR_ADDR[10]
DDR_ADDR[6]
DDR_ADDR[5]
DDR_ADDR[4]
DDR_ADDR[3]
DDR_ADDR[0-12]
002:E39;002:W39;002:AH39;002:BD39
DDR_ADDR[2]
DDR_ADDR[1]
DDR_ADDR[0]
IC102
LG1120
IC102
LG1120
P102
12505WR-10
OPT
D5
1
1
R1211
22
008:V22
AN15
LVRX1_AM
008:V21
AP16
LVRX1_BP
008:V22
AN16
LVRX1_BM
008:V21
AP17
LVRX1_CP
008:V21
AN17
LVRX1_CM
008:V19
AN19
LVRX1_DP
008:V19
AP19
LVRX1_DM
008:V18
AN20
LVRX1_EP
008:V19
AP20
LVRX1_EM
R168
R1212
22
AJ5
4
FRC_TCK
R1213
22
TMODE[0] 001:H22
5
FRC_TDO
AK7
AK9
6
SPI_DI 001:H18;001:AX5
009:E22
LVTX1_CLK-
009:O11
LVTX1_A+
009:O11
LVTX1_A-
009:O9
LVTX1_B+
009:O9
LVTX1_B-
009:O8
LVTX1_C+
009:O8
LVTX1_C-
009:O6
LVTX1_D+
009:O6
LVTX1_D-
009:O5
LVTX1_E+
009:O6
LVTX1_E-
009:E21
LVTX2_CLK+
009:E21
LVTX2_CLK-
009:E16
LVTX2_A+
009:E17
LVTX2_A-
009:O5
LVTX2_B+
009:O5
LVTX2_B-
009:E14
LVTX2_C+
009:E14
LVTX2_C-
009:E15
LVTX2_D+
009:E15
LVTX2_D-
009:E17
LVTX2_E+
009:E17
LVTX2_E-
009:E20
LVTX3_CLK+
009:E20
LVTX3_CLK-
009:E16
LVTX3_A+
B4
A2
B2
C3
C2
B3
A3
C5
C4
B5
A5
B8
A6
B6
C7
C6
B7
A7
C9
C8
B9
A9
A10
B10
C11
C10
LVTX3_B-
009:E12
B11
LVTX3_C+
009:E8
009:E8
LVTX3_C-
009:E12
LVTX3_D+
009:E12
LVTX3_D-
009:E10
LVTX3_E+
009:E11
LVTX3_E-
DDR_TAOUT
P32
DDR_TDOUT[1]
DDR_TDOUT[0]
DDR_BA[1]
DDR_BA[0]
DDR_DM[3]
DDR_DM[2]
DDR_DM[1]
DDR_DM[0]
DDR_ODT
DDR_WE_N
DDR_CAS_N
DDR_RAS_N
DDR_CS_N
DDR_CKE
DDR_DQS[3]
DDR_DQS[2]
DDR_DQS_N[3]
DDR_DQS_N[2]
DDR_DQS[1]
DDR_DQS[0]
DDR_CK_N
DDR_CK
DDR_DQ[31]
DDR_DQ[30]
DDR_DQ[29]
DDR_DQ[28]
DDR_DQ[27]
DDR_DQ[26]
DDR_DQ[25]
DDR_DQ[24]
DDR_DQ[23]
DDR_DQ[22]
DDR_DQ[21]
DDR_DQ[20]
DDR_DQ[19]
DDR_DQ[18]
DDR_DQ[17]
DDR_DQ[16]
DDR_DQ[15]
DDR_DQ[14]
DDR_DQ[13]
DDR_DQ[12]
DDR_DQ[9]
DDR_DQ[8]
DDR_DQ[7]
DDR_DQ[6]
DDR_DQ[5]
DDR_DQ[4]
DDR_DQ[3]
DDR_DQ[2]
DDR_DQ[1]
DDR_DQ[0]
DDR_A[12]
DDR_A[11]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_DQ[11]
RCLK2M
RA2P
RA1M
RA2M
RB1P
RB2P
RB1M
RB2M
RC1P
RC2P
RC1M
RC2M
RD1P
RD2P
RD1M
RD2M
RE1P
RE2P
A11
C13
C12
B13
A13
R172
100
R174
100
R176
100
TCLK5P
TCLK1N
TCLK5N
TA1P
TA5P
TA1N
TA5N
TB1P
TB5P
TB1N
TB5N
TC1P
TC5P
TC1N
TC5N
TD1P
TD5P
TD1N
TD5N
TE1P
TE5P
TE1N
TE5N
AN21
AP21
AN22
AP22
AN23
AP23
AN25
AP25
AN26
AP26
TCLK6P
TCLK2N
TCLK6N
TA2P
TA6P
TA2N
TA6N
TB2P
TB6P
TB2N
TB6N
TC2P
TC6P
TC2N
TC6N
TD2P
TD6P
TD2N
TD6N
IC102
LG1120
TE2P
TCLK3P
TE6P
SPI_DO 001:H18;001:BD4
AK30
LVRX2_CLKP
008:V15
LVRX2_CLKM
008:V15
LVRX2_AP
008:V17
LVRX2_AM
008:V18
LVRX2_BP
008:V17
LVRX2_BM
008:V17
LVRX2_CP
008:V16
D20
LVRX2_CM
008:V16
D22
LVRX2_DP
008:V14
D24
LVRX2_DM
008:V15
D26
LVRX2_EP
008:V14
D16
008:V14
D18
LVRX2_EM
LVTX5_CLK+
B20
LVTX5_CLK-
A18
LVTX5_A+
B18
LVTX5_A-
C19
LVTX5_B+
C18
B19
A19
C21
C20
B21
A21
B24
A22
B22
C23
C22
B23
A23
C25
C24
B25
A25
TCLK7N
TA3P
TA7P
TA3N
TA7N
TB3P
TB7P
TB3N
TB7N
TC3P
TC7P
TC3N
TC7N
TD3P
TD7P
TD3N
TD7N
TE3P
TE7P
TE3N
TE7N
9
+3.3VD
B28
A26
B26
R109
3.3K
009:E10
LVTX4_A+
009:E10
LVTX4_A-
009:E8
LVTX4_B+
009:E8
LVTX4_B-
009:E7
LVTX4_C+
009:E7
LVTX4_C-
009:E6
LVTX4_D+
009:E6
LVTX4_D-
009:E11
LVTX4_E+
009:E11
LVTX4_ETMODE[0]
B16
A14
B14
C15
C14
B15
A15
C17
C16
B17
A17
001:AO38
AP10
AL11
AM11
+3.3VD
AN31
R121
FRC_TMS
R1182
3.3K
OPT
AK31
FRC_TDO
AL31
+3.3VD
001:AO35;001:AX5
TB8N
TC4P
TC8P
TC4N
TC8N
TD4P
TD8P
TD4N
TD8N
TE4P
TE8P
TE4N
TE8N
SMODE
M_VS
TMODE[0]
M_SCLK
TMODE[1]
M_MOSI
TMODE[2]
S_VS
TMODE[3]
S_SCLK
D10
10
D12
D14
11
009:E37
009:E35
E11
009:E35
E13
009:E35
E15
009:E35
LVTX5_C+
009:E33
E19
LVTX5_C-
009:E34
LVTX5_D+
009:E5
LVTX5_D-
009:E5
LVTX5_E+
009:E33
E27
LVTX5_E-
009:E33
G5
+2.5VQ
+2.5LVDS_TX
+2.5VPLL
E21
+2.5LVDS_RX
E23
E25
L100
120-ohm
L101
120-ohm
H5
J5
LVTX6_CLK+
009:H22
LVTX6_CLK-
009:H22
LVTX6_A+
009:E32
L5
LVTX6_A-
009:E32
M5
LVTX6_B+
009:E28
LVTX6_B-
009:E29
LVTX6_C+
009:E27
R5
LVTX6_C-
009:E27
T5
LVTX6_D+
009:E31
U5
LVTX6_D-
009:E31
V5
LVTX6_E+
009:E36
W5
LVTX6_E-
009:E36
Y5
K5
L102
120-ohm
C1163
22uF
16V
C1162
22uF
16V
LVTX7_CLK+
009:H21
N5
C1164
22uF
16V
P5
LVTX7_CLK-
009:H21
LVTX7_A+
009:E31
LVTX7_B-
B27
LVTX7_C+
A27
LVTX7_D+
C28
LVTX7_D-
B29
A29
+3.3VD
+3.3V_IO
AC5
AD5
AE5
L103
120-ohm
009:E29
AG5
009:E30
AF5
L104
120-ohm
009:E29
LVTX7_C-
C29
+3.3V
009:E32
LVTX7_B+
C26
AB5
G30
009:E29
H30
009:E26
J30
009:E27
LVTX7_E+
009:E26
LVTX7_E-
009:E26
C1166
22uF
16V
C1165
22uF
16V
K30
L30
M30
33
AP8
R117
33
AL10
R118
33
AP9
R122
33
AM9
GPIO[1]
TMS
GPIO[2]
TDI
GPIO[3]
GPIO[4]
M_SCL
GPIO[5]
M_SDA
GPIO[6]
SCL
GPIO[7]
GPIO[8]
GPIO[9]
SPI_CS
GPIO[10]
SPI_SCLK
GPIO[11]
SPI_DI
GPIO[12]
SPI_DO
GPIO[13]
GPIO[14]
AL8
R123
33
AP7
UART_RXD
GPIO[15]
UART_TXD
GPIO[16]
FRC_RESET
GPIO[17]
AM10
PORES_N
OPT 33
GPIO[18]
GPIO[19]
AP11
DDRS_TDOUT[1]
DDRS_TDOUT[0]
DDRS_TAOUT
DDRS_BA[1]
DDRS_BA[0]
DDRS_DM[3]
DDRS_DM[2]
DDRS_DM[1]
DDRS_DM[0]
DDRS_ODT
DDRS_CAS_N
DDRS_RAS_N
DDRS_WE_N
DDRS_CS_N
DDRS_CKE
DDRS_DQS_N[3]
DDRS_DQS[3]
DDRS_DQS_N[2]
DDRS_DQS[2]
DDRS_DQS_N[1]
DDRS_DQS[1]
DDRS_DQS_N[0]
DDRS_DQS[0]
DDRS_CK_N
DDRS_CK
DDRS_DQ[31]
DDRS_DQ[30]
DDRS_DQ[29]
DDRS_DQ[28]
DDRS_DQ[27]
DDRS_DQ[26]
DDRS_DQ[25]
DDRS_DQ[24]
DDRS_DQ[23]
DDRS_DQ[22]
DDRS_DQ[21]
DDRS_DQ[20]
DDRS_DQ[19]
DDRS_DQ[18]
DDRS_DQ[17]
DDRS_DQ[16]
DDRS_DQ[15]
DDRS_DQ[14]
DDRS_DQ[13]
DDRS_DQ[12]
DDRS_DQ[11]
DDRS_DQ[10]
DDRS_DQ[9]
DDRS_DQ[8]
DDRS_DQ[7]
DDRS_DQ[6]
DDRS_DQ[5]
DDRS_DQ[4]
DDRS_DQ[3]
DDRS_DQ[2]
DDRS_DQ[1]
DDRS_DQ[0]
DDRS_A[9]
+0.9VREFS
DDRS_A[12]
GPIO[21]
DDRS_A[11]
XTALO
DDRS_A[10]
GPIO[20]
DDRS_A[8]
AN11
001:BA10
XTAL_OUT
XTALI
DDRS_A[7]
001:AX10
XTAL_IN
DDRS_A[6]
OPT
C123
0.1uF
50V
GPIO[0]
SDA
AN9
B32
A30
B30
C31
C30
B31
A31
C33
C32
B33
A33
LVTX8_CLK+
009:O24
P30
LVTX8_CLK-
009:O23
R30
LVTX8_A+
009:E28
T30
LVTX8_A-
009:E28
U30
LVTX8_B+
009:O34
V30
LVTX8_B-
009:O34
W30
LVTX8_C+
009:E25
Y30
LVTX8_C-
009:E26
AA30
LVTX8_D+
009:O35
AB30
LVTX8_D-
009:O35
AC30
LVTX8_E+
009:O33
LVTX8_E-
009:O33
AF30
AG30
R177
4.7K
OPT
AM30
AN30
Serial Flash Boot Mode
- GPIO[0]=1 : 50MHz Booting
- GPIO[0]=0 : 25MHz Booting
AP5
AN5
GPIO[22]
GPIO[23]
AL18
AL19
AL20
33
AN4
R1219
33
AP4
R173
33
AL5
R1191
33
004:AL21;005:AJ5
WP_EEPROM_TCON
L/R_SYNC
AL21
R1225
10K
004:K10;005:I9
PWM_SEQ
AL22
AL23
AL6
LVDS_IN
AM6
AN6
R180
33
R1220
33
R1214
0
R1197
10K
OPT
AL7
R175
10K
AL27
N3
R1224
0
LVDS_OUT
VIDEO_OUT
AM25
+3.3VD
M_TCON_EN
I2CEN
005:AA14
S_TCON_EN
FPGA_D/L_CTRL
005:AG12
+3.3VD
DDRS_DM2
DDRS_DM3
+3.3VD
AM26
C105
0.1uF
16V
C106
0.1uF
16V
C109
0.1uF
16V
C114
0.1uF
16V
C117
0.1uF
16V
C120
0.1uF
16V
C126
0.1uF
16V
C127
0.1uF
16V
C130
0.1uF
16V
C133
0.1uF
16V
C137
0.1uF
16V
C139
0.1uF
16V
C142
0.1uF
16V
C145
0.1uF
16V
C148
0.1uF
16V
C151
0.1uF
16V
C154
0.1uF
16V
C156
0.1uF
16V
C159
0.1uF
16V
C162
0.1uF
16V
C165
0.1uF
16V
C168
0.1uF
16V
C103
0.1uF
16V
C107
0.1uF
16V
C110
0.1uF
16V
C115
0.1uF
16V
C119
0.1uF
16V
C121
0.1uF
16V
C124
0.1uF
16V
C128
0.1uF
16V
C131
0.1uF
16V
C134
0.1uF
16V
C136
0.1uF
16V
C140
0.1uF
16V
C143
0.1uF
16V
C146
0.1uF
16V
C149
10uF
10V
C157
0.1uF
16V
C152
22uF
16V
C173
0.1uF
16V
C176
0.1uF
16V
C179
0.1uF
16V
C160
0.1uF
16V
C163
0.1uF
16V
C172
0.1uF
16V
C166
0.1uF
16V
C181
0.1uF
16V
C182
10uF
10V
C183
0.1uF
16V
C34
D1
AM22
D2
AM24
D33
D34
+1.8V_DDRS
VDD33_5
VDD33_6
VDD33_7
DDRS_VDDQ_1
VDD33_8
DDRS_VDDQ_2
VDD33_9
DDRS_VDDQ_3
VDD33_10
DDRS_VDDQ_4
VDD33_11
DDRS_VDDQ_5
VDD33_12
DDRS_VDDQ_6
VDD33_13
DDRS_VDDQ_7
VDD33_14
DDRS_VDDQ_8
VDD33_15
DDRS_VDDQ_9
VDD33_16
DDRS_VDDQ_10
VDD33_17
DDRS_VDDQ_11
VDD33_18
DDRS_VDDQ_12
VDD33_19
DDRS_VDDQ_13
VDD33_20
DDRS_VDDQ_14
VDD33_21
DDRS_VDDQ_15
VDD33_22
DDRS_VDDQ_16
DDRS_VDDQ_18
LVTX_VDD_1
DDRS_VDDQ_19
LVTX_VDD_2
DDRS_VDDQ_20
LVTX_VDD_3
DDRS_VDDQ_21
LVTX_VDD_4
DDRS_VDDQ_22
E3
H1
E4
K4
E5
L3
E6
M4
E7
N4
E8
P4
E10
R4
E12
T4
E14
U3
E16
U4
E18
Y4
E20
AA3
E22
AA4
E24
E26
AB4
E28
AC4
E29
AD4
E30
AF1
E31
AG4
E32
AJ4
F1
AK1
F5
P1
F30
P3
G3
+1.8V_DDR
LVTX_VDD_5
LVTX_VDD_6
G31
H2
L31
LVTX_VDD_7
DDR_VDDQ_1
LVTX_VDD_8
DDR_VDDQ_2
PVCC1
DDR_VDDQ_3
PVCC2
DDR_VDDQ_4
DDR_VDDQ_6
VDD_1
DDR_VDDQ_7
VDD_2
DDR_VDDQ_8
VDD_3
DDR_VDDQ_9
VDD_4
DDR_VDDQ_10
VDD_5
DDR_VDDQ_11
VDD_6
DDR_VDDQ_12
VDD_7
DDR_VDDQ_13
VDD_8
DDR_VDDQ_14
VDD_9
DDR_VDDQ_15
VDD_10
DDR_VDDQ_16
VDD_11
DDR_VDDQ_17
VDD_12
DDR_VDDQ_18
VDD_13
DDR_VDDQ_19
VDD_14
DDR_VDDQ_20
VDD_15
DDR_VDDQ_21
VDD_16
DDR_VDDQ_22
J3
M31
M34
K1
N31
L32
P31
M12
R31
M13
R32
M14
T31
M15
U31
M16
V31
M17
Y31
M18
AA31
M19
AB31
M20
AB34
M21
AC31
M22
AD31
M23
AE31
M32
AE32
M33
AE34
N12
AG31
N13
AH31
N14
N15
AK34
N16
+1.0VPLL
VDD_17
VDD_18
N17
N18
AM14
VDD_19
SS_DISP_DVDD
VDD_20
DDRPLL_DVDD
N19
AN12
N20
+2.5VPLL
VDD_21
VDD_22
N21
N22
AL13
VDD_23
DDRPLL_AVDD
VDD_24
SS_AVDD
VDD_25
DISP_AVDD
N23
AN13
P2
AP14
P12
VDD_26
P13
VDD_27
P14
VDD_28
P15
VDD_29
P16
VDD_30
P17
VDD_31
P18
VDD_32
P19
VDD_33
P20
VDD_34
P21
VDD_35
P22
VDD_36
P23
VDD_37
R12
VDD_38
R13
VDD_39
R14
VDD_40
R15
VDD_41
R16
VDD_42
R17
VDD_43
R18
VDD_44
R19
VDD_45
R20
VDD_46
R21
VDD_47
R22
VDD_48
R23
VDD_49
T12
VDD_50
T13
VDD_51
T14
VDD_52
T15
VDD_53
T16
VDD_54
T17
VDD_55
T18
VDD_56
T19
VDD_57
T20
VDD_58
T21
VDD_59
T22
VDD_60
T23
VDD_61
U12
VDD_62
U13
VDD_63
U14
VDD_64
U15
VDD_65
U16
VDD_66
U17
U19
U20
LVDS_IN
INCH_OPT_2
LVDS_OUT
R1188
4.7K
U18
R1199
4.7K
VIDEO_OUT
U21
U22
R1200
4.7K
OPT
R1198
4.7K
AP29
R1215
33
AN29
TCON_SCL_M
R1216
33
AN27
TCON_SDA_M
R1217
33
V13
AP27
TCON_SCL_S
R1218
R1192
R1193
33
TCON_SDA_S
V14
AP30
AM27
AP28
AL28
R1194
R1195
R1196
AM29
R1201
AL29
R1221
AM28
+3.3VD
33
R1222
10K
33
33
VSYNC
33
008:Y25
/FPGA_RESET
009:AN29
OD data D/L,
during 2D/3D mode switching
33
3D_FRAME_INFO
R1226 0
010:AN12
33
33
GPIO[24]
OPT
Output LVDS Data Mapping Selection
- GPIO[6] = 1 : JEIDA
- GPIO[6] = 0 : VESA
V12
V15
Video Output Selection
- GPIO[7] = 1 : Reverse(LED Model)
- GPIO[7] = 0 : Normal(LAMP Model)
V16
V17
V18
V19
OPT
L/R_SYNC_FRC_OUT
Input LVDS Data Mapping Selection
- GPIO[5] = 1 : JEIDA
- GPIO[5] = 0 : VESA
U23
GAMMA_BKSEL
008:M17
V20
DPM_CTRL1
008:M17
V21
R1227 0
OPT
R1185
10K
V22
V23
W4
+3.3VD
R1204
4.7K
INCH_1_HIGH
R1205
4.7K
INCH_1_LOW
W12
+3.3VD
R1206
4.7K
INCH_2_HIGH
INCH_OPT_1
LOW
LOW
47
LOW
HIGH
55
HIGH
LOW
C125
0.1uF
16V
C129
0.1uF
16V
C132
0.1uF
16V
C135
0.1uF
16V
C138
0.1uF
16V
C141
0.1uF
16V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C144
0.1uF
16V
C147
0.1uF
16V
C150
0.1uF
16V
C153
0.1uF
16V
C155
0.1uF
16V
C158
0.1uF
16V
C161
0.1uF
16V
C164
0.1uF
16V
C167
0.1uF
16V
C169
10uF
10V
C171
22uF
16V
VSS_6
VSS_132
VSS_7
VSS_133
VSS_8
VSS_134
VSS_9
VSS_135
VSS_10
VSS_136
VSS_11
VSS_137
VSS_12
VSS_138
VSS_13
VSS_139
VSS_14
VSS_140
VSS_15
VSS_141
VSS_16
VSS_142
VSS_17
VSS_143
VSS_18
VSS_144
VSS_19
VSS_145
VSS_20
VSS_146
VSS_21
VSS_147
VSS_22
VSS_148
VSS_23
VSS_149
VSS_24
VSS_150
VSS_25
VSS_151
VSS_26
VSS_152
VSS_27
VSS_153
VSS_28
VSS_154
VSS_29
VSS_155
VSS_30
VSS_156
VSS_31
VSS_157
VSS_32
VSS_158
VSS_33
VSS_159
VSS_34
VSS_160
VSS_35
VSS_161
VSS_36
VSS_162
VSS_37
VSS_163
VSS_38
VSS_164
VSS_39
VSS_165
VSS_40
VSS_166
VSS_41
VSS_167
VSS_42
VSS_168
VSS_43
VSS_169
VSS_44
VSS_170
VSS_45
VSS_171
VSS_46
VSS_172
VSS_47
VSS_173
VSS_48
VSS_174
VSS_49
VSS_175
VSS_50
VSS_176
VSS_51
VSS_177
VSS_52
VSS_178
VSS_53
VSS_179
VSS_54
VSS_180
VSS_55
VSS_181
VSS_56
VSS_182
VSS_57
VSS_183
VSS_58
VSS_184
VSS_59
VSS_185
VSS_60
VSS_186
VSS_61
VSS_187
VSS_62
VSS_188
VSS_63
VSS_189
VSS_64
VSS_190
VSS_65
VSS_191
VSS_66
VSS_192
VSS_67
VSS_193
VSS_68
VSS_194
VSS_69
VSS_195
VSS_70
VSS_196
VSS_71
VSS_197
VSS_72
VSS_198
VSS_73
VSS_199
VSS_74
VSS_200
VSS_75
VSS_201
VSS_76
VSS_202
VSS_77
VSS_203
VSS_78
VSS_204
VSS_79
VSS_205
VSS_80
VSS_206
VSS_81
VSS_207
VSS_82
VSS_208
VSS_83
VSS_209
VSS_84
VSS_210
VSS_85
VSS_211
VSS_86
VSS_212
VSS_87
VSS_213
VSS_88
VSS_214
VSS_89
VSS_215
VSS_90
VSS_216
VSS_91
VSS_217
VSS_92
VSS_218
VSS_93
VSS_219
VSS_94
VSS_220
VSS_95
VSS_221
VSS_96
VSS_222
VSS_97
VSS_223
VSS_98
VSS_224
VSS_99
VSS_225
VSS_100
VSS_226
VSS_101
VSS_227
VSS_102
VSS_228
VSS_103
VSS_229
VSS_104
C175
0.1uF
16V
C184
0.1uF
16V
C177
0.1uF
16V
C174
22uF
16V
C178
22uF
16V
C180
22uF
16V
C185
0.1uF
16V
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W32
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB32
AB33
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AD3
AE33
AF2
AF32
AG3
AH5
AH30
AH33
AJ31
AJ34
AK2
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK33
AL1
AL3
AL25
AL26
AL32
AM3
AN2
AN3
AN32
AP2
AP3
AP32
AP33
D9
VSS_105
LVTX_VSS_1
VSS_106
LVTX_VSS_2
VSS_107
LVTX_VSS_3
VSS_108
LVTX_VSS_4
VSS_109
LVTX_VSS_5
VSS_110
LVTX_VSS_6
VSS_111
LVTX_VSS_7
VSS_112
LVTX_VSS_8
VSS_113
D11
D13
D15
D21
D23
D25
D27
D17
VSS_114
PGND1
VSS_115
PGND2
VSS_116
D19
AM17
VSS_117
LVRX_VSS1
VSS_118
LVRX_VSS2
VSS_119
LVRX_VSS3
VSS_120
LVRX_VSS4
VSS_121
AM19
AM21
AM23
AM12
VSS_122
DDRPLL_DVSS
VSS_123
SS_AVSS
VSS_124
DISP_AVSS
VSS_125
DDRPLL_AVSS
VSS_126
SS_DISP_DVSS
AM13
AN14
AP12
AP13
R191
1M
XTAL_IN
XTAL_OUT
001:H17
001:H17
C1160
15pF
50V
C1159
15pF
50V
+1.0VPLL
C186
0.1uF
16V
C189
0.1uF
16V
C193
0.1uF
16V
C195
0.1uF
16V
C198
0.1uF
16V
C1101
0.1uF
16V
C1104
0.1uF
16V
C1107
0.1uF
16V
C1110
0.1uF
16V
C1113
0.1uF
16V
C1116
0.1uF
16V
C1121
0.1uF
16V
C1122
0.1uF
16V
C1127
0.1uF
16V
C1129
0.1uF
16V
C1133
0.1uF
16V
C1136
0.1uF
16V
C1139
0.1uF
16V
C1140
0.1uF
16V
C1143
0.1uF
16V
C1148
0.1uF
16V
C1151
10uF
10V
C1152
22uF
16V
C1153
22uF
16V
C1154
22uF
16V
C1155
22uF
16V
C1157
0.1uF
16V
C1158
0.1uF
16V
+3.3VD
C187
0.1uF
16V
C190
0.1uF
16V
C192
0.1uF
16V
C196
0.1uF
16V
C199
0.1uF
16V
C1102
0.1uF
16V
C1105
0.1uF
16V
C1108
0.1uF
16V
C1111
0.1uF
16V
C1114
0.1uF
16V
C1117
0.1uF
16V
C1119
0.1uF
16V
C1123
0.1uF
16V
C1125
0.1uF
16V
C1130
0.1uF
16V
C1131
0.1uF
16V
C1134
0.1uF
16V
C1137
0.1uF
16V
C1141
0.1uF
16V
C1144
0.1uF
16V
C1146
10uF
10V
C1149
10uF
10V
R188
R190
4.7K
10K
IC101
W25X20AVSNIG
DO
C191
0.1uF
16V
C194
0.1uF
16V
C197
0.1uF
16V
C1100
0.1uF
16V
C1103
0.1uF
16V
C1106
0.1uF
16V
C1109
0.1uF
16V
C1112
0.1uF
16V
C1115
0.1uF
16V
C1118
0.1uF
16V
C1120
0.1uF
16V
C1124
0.1uF
16V
C1126
0.1uF
16V
C1128
0.1uF
16V
C1132
0.1uF
16V
C1135
0.1uF
16V
C1138
0.1uF
16V
C1142
0.1uF
16V
C1145
0.1uF
16V
C1147
10uF
10V
8
2
7
3
6
4
5
C1161
0.1uF
VCC
HOLD
R192
3.3K
WP
C188
0.1uF
16V
1
33
GND
C122
0.1uF
16V
VSS_131
X100
25MHz
R189
C118
0.1uF
16V
VSS_5
XTAL
SPI_DI
001:H18;001:AO37
C116
0.1uF
16V
VSS_130
INCH_2
42
+1.0VDC
C111
0.1uF
16V
VSS_129
VSS_4
+1.0VDC
+1.8V_DDR
C108
0.1uF
16V
VSS_128
VSS_3
INCH_OPT_2
SPI_CS
001:H19;001:AO35
C104
0.1uF
16V
VSS_127
VSS_2
R1207
4.7K
INCH_2_LOW
CS
C102
0.1uF
16V
W13
VSS_1
SPI FLASH(2Mbit)
+2.5VPLL
+2.5LVDS_RX
+2.5LVDS_TX
C170
0.1uF
16V
LVRX_VDD4
C1
AM18
AM20
VDD_67
R1189
4.7K
OPT
R1187
4.7K
OPT
002:F13;002:U7;002:AK13;002:BB6 DDRS_BA1
DDRS_DM1
002:AK10
002:F13;002:U8;002:AK13;002:BB7 DDRS_BA0
DDRS_DM0
002:F9
002:F9
002:AK10
DDRS_WE
002:F11;002:U5;002:AK12;002:BB4 DDRS_ODT
002:F11;002:U6;002:AK11;002:BB5 DDRS_CAS
002:F11;002:U6;002:AK11;002:BB5 DDRS_RAS
002:F11;002:U6;002:AK11;002:BB5
DDRS_CS
002:F11;002:U7;002:AK12;002:BB6
002:F12;002:U7;002:AK12;002:BB6 DDRS_CKE
DDRS_DQS2
DDRS_DQS2
DDRS_DQS3
DDRS_DQS3
002:AK9
002:AK9
002:AK10
DDRS_DQS0
DDRS_DQS1
DDRS_DQS1
DDRS_DQS0
AM15
AM16
INCH_OPT_1
AN28
AL24
TCON_POWER_EN 007:Q15;006:P14
DPM_CTRL
004:AM14
OPT
AC3
AB3
W3
V3
0
22
22
R1223
R169
R167
M3
AE3
AJ3
22
22
22
22
R165
R161
R159
R163
F4
AA2
AB2
AB1
22
22
22
22
R157
R155
R153
R151
AA1
AC2
R149
22
Y1
22
R147
AF4
AK4
AK3
AF3
22
22
22
22
R145
R143
R141
R139
L2
G1
L1
22
22
22
R137
R135
R133
G2
22
R131
V2
22
R129
V1
22
R127
22
R1180
DDRS_DATA[31]
AE1
22
R1179
DDRS_DATA[30]
AH2
22
R1178
DDRS_DATA[29]
AD2
22
R1177
DDRS_DATA[28]
AG1
22
R1176
DDRS_DATA[27]
AG2
22
R1175
DDRS_DATA[26]
AD1
22
R1174
DDRS_DATA[25]
AH1
22
R1173
DDRS_DATA[24]
AE2
22
R1172
DDRS_DATA[23]
AJ1
22
R1171
DDRS_DATA[22]
AL2
22
R1170
DDRS_DATA[21]
AH3
22
R1169
DDRS_DATA[20]
AM2
22
R1168
DDRS_DATA[19]
AN1
22
R1167
DDRS_DATA[18]
AH4
22
R1166
DDRS_DATA[17]
AM1
22
R1165
DDRS_DATA[16]
K2
22
R1164
DDRS_DATA[15]
J2
22
R1163
DDRS_DATA[14]
M2
22
R1162
DDRS_DATA[13]
N1
22
R1161
DDRS_DATA[12]
AJ2
22
R1160
DDRS_DATA[11]
M1
22
R1159
DDRS_DATA[10]
J1
22
R1158
DDRS_DATA[9]
N2
22
R1157
DDRS_DATA[8]
K3
22
R1156
DDRS_DATA[7]
F2
22
R1155
DDRS_DATA[6]
G4
22
R1154
DDRS_DATA[5]
E2
22
R1153
DDRS_DATA[4]
H3
22
R1152
DDRS_DATA[3]
J4
22
R1151
DDRS_DATA[2]
E1
22
R1150
DDRS_DATA[1]
H4
22
22
R1149
DDRS_DATA[0]
F3
AC1
22
DDRS_ADDR[11]
R1148
U2
22
DDRS_ADDR[10]
R1147
R3
22
DDRS_ADDR[9]
R1146
Y3
22
DDRS_ADDR[8]
R1145
U1
22
DDRS_ADDR[7]
R1144
Y2
22
DDRS_ADDR[6]
R1143
R2
22
DDRS_ADDR[5]
R1142
T3
22
DDRS_ADDR[4]
R1141
R1
22
DDRS_ADDR[3]
R1140
T2
22
DDRS_ADDR[2]
R1139
W2
T1
AL16
+3.3VD
R1190
AN7
AL15
AL17
AM4
AM7
AL14
R178
4.7K
AM5
AP6
C1167
0.1uF
16V
+1.8V_DDRS
+3.3V_IO
C101
0.1uF
16V
002:AK10
UART_TX 001:H18
.
002:F10
002:F9
TX
002:F10
002:F9
UART_RX 001:H18
5
C100
0.1uF
16V
AE30
+3.3VD
INCH_1
002:F12;002:AK13 DDRS_CLK
002:F12;002:AK12 DDRS_CLK
RX
DDRS_ADDR[12]
R125
R1186
33
22
C113
0.1uF
50V
DDRS_DATA[0-31]
002:N17;002:AT17
4
GND
DDRS_ADDR[0-12]
3
+3.3V
002:E16;002:W13;002:AK17;002:BD12
2
22
OPT
DDRS_ADDR[1]
R1138
+3.3VD
DDRS_ADDR[0]
R1137
W1
V4
L4
AE4
P100
1
AD30
L105
120-ohm
For 3D Formatter
12505WR-04A00
+1.0VPLL
+1.0VDC
AL4
TCK
VDD33_4
DDR_VDDQ_5
E9
S_MOSI
TRST_N
LVRX_VDD3
D8
AL30
DDRS_A[5]
008:W24
R111
O
G
TB4N
DDRS_A[4]
3
OPT
2
TB8P
DDRS_A[3]
1
OPT
C112
0.1uF
50V
4
R116
001:E12 UART_RX
001:E12 UART_TX
3
1
IC100
I
2
SPI_CS
001:AO36;001:BD4 SPI_SCLK
001:AO37;001:AX5
SPI_DI
001:AO36;001:BD4
SPI_DO
KIA7029AF
OPT
R115
0 OPT AN8
0 OPT AM8
AL9
33
R1184
1K
TB4P
TDO
FPGA_SDA
I2C_SCL
005:AA16;008:F18;008:V24;008:AL4;009:AP8
I2C_SDA
005:AA15;008:N18;008:V25;008:AL4;009:AP11
SW100
JTP-1127WEM
TA8N
DDRS_A[2]
R1181
3.3K
OPT
3.3K
R1183
OPT
R101
TA4N
DDRS_A[1]
R110
1K
AM31
FRC_TDI
FPGA_SCL
OPT
R106
10K
TA8P
DDRS_A[0]
R107
1K
+3.3VD
TA4P
AP31
FRC_TCK
For 3D Formatter I2C (Ready)
TCLK8N
R119 10K AL12
AN10
[TEST MODE SETTING]
- SMODE = 0 : Serial Flash Setting
- TMODE(All) = 1 : Normal Mode
TCLK4N
DDRS_VREF2
R105
3.3K
LVTX4_CLK-
TCLK8P
VDD33_3
009:E36
LVTX7_A-
C27
A32
TCLK4P
DDRS_VREF1
R103
3.3K
009:E5
A16
DDRS_VREF0
R102
3.3K
LVTX4_CLK+
LVRX_VDD2
SPI_CS 001:H19;001:AX5
N30
009:E5
VDD33_2
DDRS_VDDQ_17
AA5
A28
TCLK3N
LVRX_VDD1
+2.5LVDS_TX
E17
LVTX5_B-
TE6N
TCLK7P
VDD33_1
+1.0VDC
A24
TCLK2P
AK29
8
AP24
A20
TCLK1P
AK27
SPI_SCLK
001:H19;001:BD4
AK28
R179
100
RE2M
A12
LVTX3_B+
009:E11
RCLK2P
RA1P
TE2N
B12
R171
100
AN24
A8
LVTX3_A-
009:E16
R170
100
A4
LVTX1_CLK+
AK10
AJ30
RE1M
009:E22
AK5
AK6
6
N32
R166
D31
AK8
AC32
U32
V32
R164
R162
K32
G32
AM32 R158
AD32 R160
R156
R152
R150
R154
P34
R33
P33
R148
R34
N33
R146
T34
R144
R140
R138
R142
J32
J31
F31
F32
AF34 R134
AF33 R136
AL33 R130
AL34 R132
R128
V33
R126
V34
H33 R1135
K34 R1136
J34 R1133
L33 R1134
L34 R1131
J33 R1132
K33 R1129
H34 R1130
F33 R1127
G34 R1128
E33 R1125
H32 R1126
H31 R1123
E34 R1124
G33 R1121
F34 R1122
AD33R1119
AG34R1120
AC34R1117
AJ33R1118
AH34R1115
AD34R1116
AG33R1113
AC33R1114
AK32R1111
AM34R1112
AJ32R1109
AN33R1110
AN34R1107
AG32R1108
R124
AM33R1105
AH32R1106
N34
AA32R1103
W33 R1104
W34 R1101
T32 R1102
AA33R199
T33 R1100
AA34R197
Y32 R198
DDR_A[5]
DDR_A[4]
DDR_DQS_N[1]
LVRX1_AP
RCLK1M
DDR_DQS_N[0]
008:V22
AP15
DDR_DQ[10]
008:V20 LVRX1_CLKM
RCLK1P
DDR_A[10]
AP18
DDR_A[3]
008:V20 LVRX1_CLKP
DDR_A[2]
AN18
DDR_A[1]
R120
100
DDR_A[0]
R114
100
DDR_VREF2
R113
100
DDR_VREF1
R112
100
DDR_VREF0
R108
100
D29
3
7
R104
100
004:AE9
D32
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
U33 R195
Y33 R196
U34 R193
Y34 R194
W31
K31
AF31
TCON_SDA
D30
FRC_TMS
5
004:AA9
D28
2
FRC_TDI
4
+0.9VREF
D6
D7
R1210
22
3
TCON_SCL
B34
+2.5LVDS_RX
D3
D4
2
B1
+3.3V_IO
P101
+3.3VD
YFW254-06
C1150
10uF
10V
CLK
SPI_SCLK
001:H19;001:AO36
DIO
SPI_DO
001:H18;001:AO36
3D + 240 FRC + TCON BOARD
LG1120(FRC
฀
240Hz Chip)
2009. 11. 13
1
10
LGE Internal Use Only
IC200
H5PS5162FFR-S6C
+0.9VREF
IC205
H5PS5162FFR-S6C
+0.9VREF
DDR_DATA[0-31]
DDR_DATA[0-31]
001:O40;002:N40
001:O40;002:AQ40
N8
A5
N3
DDR_ADDR[6]
A6
N7
DDR_ADDR[7]
A7
P2
DDR_ADDR[8]
A8
DDR_ADDR[9]
A9
P3
DDR_ADDR[10]
A10/AP
M2
DDR_ADDR[11]
A11
P7
DDR_ADDR[12]
A12
R2
BA0
001:Z38;002:U33;002:AI36;002:BB34 DDR_BA0
001:AA38;002:U33;002:AI36;002:BB33 DDR_BA1
BA1
P8
200
001:V38;002:AI35 DDR_CLK
001:Y38;002:U31;002:AI34;002:BB31 DDR_ODT
001:X38;002:U33;002:AI34;002:BB33 DDR_CS
001:Y38;002:U31;002:AI34;002:BB32 DDR_RAS
001:Y38;002:U32;002:AI34;002:BB32 DDR_CAS
R202
001:V38
DDR_DQS0
001:W38
DDR_DQS1
100
OPT
DDR_DM0
001:Y38
DDR_DQS0
001:W38
DDR_DQS1
F9
DQ7
C8
DQ8
C2
DQ9
D7
DQ10
D3
DQ11
D1
DQ12
D9
DQ13
B1
DQ14
B9
DQ15
L3
A1
VDD5
E1
VDD4
CK
J8
J9
VDD3
CK
K8
M9
VDD2
K2
R1
VDD1
VDDQ9
L7
C3
WE
K3
C7
VDDQ7
C9
VDDQ6
LDQS
E9
VDDQ5
F7
UDQS
G1
VDDQ4
B7
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
A8
L1
NC5
R3
R7
NC1
A2
NC2
E2
NC3
R8
VSSDL
+1.8V_DDR
VDDL
A5
N3
DDR_ADDR[6]
A6
N7
DDR_ADDR[7]
A7
P2
DDR_ADDR[2]
DDR_ADDR[8]
A8
150
R291
DDR_ADDR[3]
DDR_ADDR[9]
A9
P3
DDR_ADDR[10]
A10/AP
M2
DDR_ADDR[11]
A11
P7
DDR_ADDR[12]
A12
R2
150
R292
DDR_ADDR[4]
150
R293
DDR_ADDR[5]
150
R294
DDR_ADDR[6]
150
R295
DDR_ADDR[7]
001:Z38;002:F36;002:U33;002:BB34 DDR_BA0
001:AA38;002:F36;002:U33;002:BB33 DDR_BA1
P8
R296
R297
DDR_ADDR[9]
R298
DDR_ADDR[10]
150
R299
DDR_ADDR[11]
150
R215
DDR_ADDR[12]
200
001:V38;002:F35 DDR_CLK
001:V38;002:F35 DDR_CLK
001:X38;002:F35;002:U32;002:BB33 DDR_CKE
DDR_ADDR[8]
150
150
J7
J1
001:Y38;002:F34;002:U31;002:BB31 DDR_ODT
001:X38;002:F34;002:U33;002:BB33 DDR_CS
BA0
L2
BA1
L3
150
A3
VSS5
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
R217
R218
150
R219
150
R220
150
R221
150
150
001:X38;002:F34;002:AI34;002:BB33
DDR_CS
DDR_CKE 001:X38;002:F35;002:AI35;002:BB33
001:W38
DDR_DQS2
001:W38
DDR_DQS3
001:Z38
001:Z38
DDR_CAS 001:Y38;002:F34;002:AI34;002:BB32
DDR_RAS 001:Y38;002:F34;002:AI34;002:BB32
R223
R249
100
OPT
100
OPT
DDR_DM2
H1
DQ4
H9
DQ5
DDR_DATA[21]
F1
DQ6
DDR_DATA[22]
F9
DQ7
DDR_DATA[23]
C8
DQ8
DDR_DATA[24]
C2
DQ9
DDR_DATA[25]
D7
DQ10
DDR_DATA[26]
D3
DQ11
DDR_DATA[27]
D1
DQ12
DDR_DATA[28]
D9
DQ13
DDR_DATA[29]
B1
DQ14
B9
DQ15
A1
VDD5
E1
VDD4
J8
J9
VDD3
K8
M9
VDD2
K2
R1
VDD1
L8
DDR_DATA[20]
001:L40;002:E39;002:W39;002:AH39
DDR_DATA[30]
K9
A9
VDDQ10
K7
C1
VDDQ9
L7
C3
VDDQ8
WE
K3
C7
VDDQ7
C9
VDDQ6
LDQS
E9
VDDQ5
F7
UDQS
G1
VDDQ4
B7
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
F3
UDM
B3
LDQS
E8
DDR_DM3
001:W38
DDR_DQS2
001:X38
DDR_DQS3
UDQS
A8
NC4
DDR_ODT 001:Y38;002:F34;002:AI34;002:BB31
L1
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
A3
VSS5
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
D8
VSSDL
J7
+1.8V_DDR
+3.3VD
VDDL
J1
C203
0.1uF
16V
C209
0.1uF
16V
C206
0.1uF
16V
C212
0.1uF
16V
C215
0.1uF
16V
C218
0.1uF
16V
C221
0.1uF
16V
C225
0.1uF
16V
C223
0.1uF
16V
C227
0.1uF
16V
C229
0.1uF
16V
C231
0.1uF
16V
C233
0.1uF
16V
C237
0.1uF
16V
C235
0.1uF
16V
C255
4.7uF
10V
C253
47uF
10V
C254
47uF
10V
VSSQ5
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
C243
10uF
10V
EN
VTTS
C263
0.01uF
50V
C213
0.1uF
16V
C216
0.1uF
16V
C219
0.1uF
16V
C224
0.1uF
16V
C222
0.1uF
16V
C226
0.1uF
16V
C228
0.1uF
16V
C230
0.1uF
16V
C232
0.1uF
16V
C234
0.1uF
16V
C238
0.1uF
16V
C236
0.1uF
16V
DDR_ADDR[5]
R2218
DDR_ADDR[6]
R2219
DDR_ADDR[7]
150
150
R2220
R2221
DDR_ADDR[8]
DDR_ADDR[9]
150
150
R2222
R2223
DDR_ADDR[10]
DDR_ADDR[11]
150
R258
DDR_ADDR[12]
150
R259
150
R260
150
R261
150
R262
150
R263
150
R264
150
R265
150
R266
C261
0.1uF
16V
DDR_BA0 001:Z38;002:F36;002:U33;002:AI36
DDR_BA1 001:AA38;002:F36;002:U33;002:AI36
DDR_CS
001:X38;002:F34;002:U33;002:AI34
DDR_CKE
001:X38;002:F35;002:U32;002:AI35
DDR_WE
001:X38;002:F34;002:U32;002:AI34
DDR_CAS
001:Y38;002:F34;002:U32;002:AI34
DDR_RAS
001:Y38;002:F34;002:U31;002:AI34
DDR_ODT 001:Y38;002:F34;002:U31;002:AI34
+1.8V_DDR
+1.8V_DDR
+0.9VREF
+0.9VREF
R276
4.7K
OPT
R250
4.7K
OPT
1
8
2
7
3
6
4
VTT
C275
0.1uF
16V
VTT_IN
VCC
RC FILTER
R236
220
VDDQ
5
C257
10uF
6.3V
C265
1uF
10V
C267
10uF
6.3V
R284
4.7K
OPT
C278
0.1uF
16V
C281
0.1uF
16V
C284
0.1uF
16V
C287
0.1uF
16V
C290
0.1uF
16V
C296
0.1uF
16V
C293
0.1uF
16V
C1200
0.1uF
16V
C298
0.1uF
16V
C1202
0.1uF
16V
C1204
0.1uF
16V
C1206
0.1uF
16V
C1208
0.1uF
16V
C1210
0.1uF
16V
C1212
0.1uF
16V
C1216
0.1uF
16V
C1214
10uF
10V
C1222
0.01uF
50V
C1236
0.1uF
16V
R251
4.7K
OPT
+1.8V_DDRS
C273
0.01uF
50V
C269
2.2uF
25V
C1240
0.01uF
50V
C1244
0.1uF
16V
R277
4.7K
OPT
C1246
0.01uF
50V
R285
4.7K
OPT
+1.8V_DDR
+1.8V_DDRS
+1.8V_DDRS
C271
0.1uF
16V
+1.8V_DDR
C210
0.1uF
16V
R2217
150
150
0.9V DDR VREF POWER DIVIDER
+0.9VREFS
R278
4.7K
OPT
R252
4.7K
OPT
C276
0.1uF
16V
C244
10uF
10V
+0.9VREFS
+0.9VREFS
+1.8V_DDRS
C207
0.1uF
16V
DDR_ADDR[4]
DDR_ADDR[2]
+1.8V_DDRS
VREF
C204
0.1uF
16V
R2216
DDR_ADDR[0]
DDR_ADDR[1]
- For Main Chip Side
IC202
BD35331F-E2
R224
10K
+0.9VREF
C201
0.1uF
16V
DDR_ADDR[3]
150
+1.8V_DDR
GND
C200
0.1uF
16V
R2215
VSSQ6
F2
+0.9VREF
C259
0.1uF
16V
R2212
R2213
R2214
150
VSSQ7
E7
+0.9VTT
+1.8V_DDR
150
150
150
150
DDR_DATA[31]
CAS
LDM
DDR_ADDR[0-12]
+0.9VTT
001:X38;002:F34;002:AI34;002:BB32
DDR_WE
R222
R247
DDR_DATA[19]
CK
CS
DDR_BA0 001:Z38;002:F36;002:AI36;002:BB34
DDR_BA1 001:AA38;002:F36;002:AI36;002:BB33
DDR_DATA[18]
DQ3
CK
001:X38;002:F34;002:U32;002:BB32 DDR_WE
R216
150
150
DQ2
H3
CKE
RAS
001:Y38;002:F34;002:U31;002:BB32 DDR_RAS
001:Y38;002:F34;002:U32;002:BB32 DDR_CAS
H7
+1.8V_DDR
ODT
VDDQ8
NC6
N8
DDR_ADDR[5]
DDR_ADDR[0]
DDR_ADDR[1]
R290
150
VDDQ10
NC4
DDR_ADDR[4]
R288
R289
R246
C1
E8
N2
A4
150
DDR_DATA[15]
A9
LDQS
M7
A3
150
DDR_DATA[14]
K7
B3
M3
A2
150
DDR_DATA[13]
L8
F3
A1
DDR_ADDR[2]
DDR_ADDR[3]
DDR_DATA[8]
DDR_DATA[12]
K9
UDM
DDR_ADDR[1]
M8
DDR_DATA[9]
DDR_DATA[11]
CS
CAS
UDQS
001:L40;002:E39;002:AH39;002:BD39
DDR_DATA[7]
RAS
LDM
DDR_ADDR[0-12]
+0.9VTT
DDR_DATA[10]
ODT
DDR_DM1
001:Z38
001:V38
DDR_DATA[6]
L2
R205
100
OPT
DDR_DATA[5]
DQ6
CKE
DDR_WE
001:X38;002:U32;002:AI34;002:BB32
DDR_DATA[4]
DQ5
F1
+1.8V_DDR
R204
001:V38;002:AI35 DDR_CLK
001:X38;002:U32;002:AI35;002:BB33 DDR_CKE
DQ4
H9
A0
C1232
0.1uF
DDR_ADDR[4]
DDR_ADDR[5]
H1
DDR_ADDR[0]
DDR_DATA[17]
C1234
0.1uF
N2
A4
For Termination of DDR
001:L40;002:E39;002:W39;002:BD39
DDR_DATA[16]
DQ1
C1230
0.1uF
M7
A3
DDR_DATA[3]
DQ0
G2
C1226
0.1uF
M3
A2
DDR_DATA[2]
DQ3
G8
C1228
0.1uF
A1
DDR_ADDR[3]
DQ2
H3
J2
DDR_ADDR[0-12]
C1220
0.1uF
DDR_ADDR[1]
DDR_ADDR[2]
H7
VREF
For Termination of DDR
C252
0.1uF
M8
DDR_DATA[1]
C250
0.1uF
A0
DDR_DATA[0]
DQ1
C248
0.1uF
DDR_ADDR[0]
DQ0
G2
C242
0.1uF
001:L40;002:W39;002:AH39;002:BD39
G8
C246
0.1uF
J2
C240
0.1uF
VREF
DDR_ADDR[0-12]
C279
0.1uF
16V
C282
0.1uF
16V
C285
0.1uF
16V
C288
0.1uF
16V
C291
0.1uF
16V
C294
0.1uF
16V
C280
0.1uF
16V
C283
0.1uF
16V
C286
0.1uF
16V
C289
0.1uF
16V
C292
0.1uF
16V
C295
0.1uF
16V
C297
0.1uF
16V
C299
0.1uF
16V
C1201
0.1uF
16V
C1203
0.1uF
16V
C1205
0.1uF
16V
C1207
0.1uF
16V
C1209
0.1uF
16V
C1211
0.1uF
16V
C1213
0.1uF
16V
C1215
10uF
10V
C1217
0.1uF
16V
C1223
0.01uF
50V
C1237
0.1uF
16V
R253
4.7K
OPT
C1241
0.01uF
50V
R286
4.7K
OPT
C1245
0.1uF
16V
R279
4.7K
OPT
C1247
0.01uF
50V
R287
4.7K
OPT
+3.3VD
+0.9VREF
C220
0.1uF
16V
- For SDRAM Side
C260
0.1uF
16V
C256
4.7uF
10V
C2201
47uF
10V
C2202
47uF
10V
R225
10K
EN
+0.9VREFS
VTTS
VREF
C264
0.01uF
50V
J2
A0
M8
A1
M3
DDRS_ADDR[2]
A2
M7
N2
A4
N8
DDRS_ADDR[5]
A5
N3
DDRS_ADDR[6]
A6
P2
A8
P8
A9
P3
A10/AP
M2
DDRS_ADDR[11]
A11
P7
DDRS_ADDR[12]
A12
R2
001:Z13;002:U8;002:AK13;002:BB7 DDRS_BA0
001:AA13;002:U7;002:AK13;002:BB6 DDRS_BA1
001:V13;002:AK13
001:V13;002:AK12
DDRS_CLK
001:X13;002:U7;002:AK12;002:BB6
DDRS_CLK
DDRS_CKE
001:Y13;002:U5;002:AK12;002:BB4
DDRS_ODT
001:X13;002:U7;002:AK12;002:BB6
L2
BA1
L3
DDRS_RAS
001:Y13;002:U6;002:AK11;002:BB5
DDRS_CAS
001:X13;002:U6;002:AK11;002:BB5
DDRS_WE
001:V13
DDRS_DQS0
001:W13
DDRS_DQS1
001:Z13
R203
100
OPT
100
OPT
DDRS_DM0
DDRS_DQS0
001:W13
DDRS_DQS1
DDRS_DATA[2]
DQ3
DDRS_DATA[3]
H1
DQ4
H9
DQ5
DDRS_DATA[5]
F1
DQ6
DDRS_DATA[6]
F9
DQ7
DDRS_DATA[7]
C8
DQ8
DDRS_DATA[8]
C2
DQ9
DDRS_DATA[9]
D7
DQ10
D3
DQ11
D1
DQ12
DDRS_DATA[12]
D9
DQ13
DDRS_DATA[13]
B1
DQ14
DDRS_DATA[14]
B9
DQ15
DDRS_DATA[15]
J8
A1
VDD5
E1
VDD4
J9
VDD3
K8
M9
CKE
K2
R1
VDD1
ODT
K9
CAS
WE
A9
VDDQ10
C1
VDDQ9
L7
C3
VDDQ8
C7
VDDQ7
B7
C9
VDDQ6
E9
VDDQ5
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
LDM
F3
UDM
B3
LDQS
E8
A3
VSS5
UDQS
A8
E3
VSS4
J3
VSS3
N1
VSS2
NC4
L1
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
VSSDL
J7
+1.8V_DDRS
VDDL
J1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R237
220
VDDQ
C266
1uF
10V
C258
10uF
6.3V
C270
2.2uF
25V
C268
10uF
6.3V
C1218
0.1uF
16V
+1.8V_DDRS
C274
0.01uF
50V
C272
0.1uF
16V
C1224
0.01uF
50V
C1238
0.1uF
16V
R255
4.7K
OPT
C1242
0.01uF
50V
R281
4.7K
OPT
IC204
H5PS5162FFR-S6C
+0.9VREFS
VREF
J2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
DDRS_ADDR[0]
A0
M8
DDRS_ADDR[1]
A1
M3
DDRS_ADDR[2]
A2
M7
DDRS_ADDR[3]
A3
N2
DDRS_ADDR[4]
A4
N8
DDRS_ADDR[5]
A5
N3
DDRS_ADDR[6]
A6
N7
DDRS_ADDR[7]
A7
P2
DDRS_ADDR[8]
A8
P8
A9
P3
DDRS_ADDR[10]
A10/AP
M2
DDRS_ADDR[11]
A11
P7
DDRS_ADDR[12]
A12
R2
DDRS_ADDR[9]
DDRS_DATA[11]
K7
F7
5
RC FILTER
DDRS_DATA[10]
L8
UDQS
4
VCC
DDRS_DATA[4]
K3
LDQS
DDRS_DM1
001:V13
DDRS_DATA[1]
DQ2
H3
VDD2
RAS
R201
DDRS_DATA[0]
DQ1
H7
CK
CS
DDRS_CS
001:Y13;002:U6;002:AK11;002:BB5
001:Y13
200
DQ0
G2
For Termination of DDR
+1.8V_DDRS
BA0
R200
CK
G8
+0.9VTTS
DDRS_ADDR[0-12]
001:Z13;002:F13;002:U8;002:BB7
DDRS_BA0
001:AA13;002:F13;002:U7;002:BB6
DDRS_BA1
001:V13;002:F12 DDRS_CLK
150
150
R2200
R2201
R2202
DDRS_ADDR[2]
001:Y13;002:F11;002:U5;002:BB4
R2203
DDRS_ADDR[3]
001:X13;002:F11;002:U7;002:BB6
DDRS_CS
001:Y13;002:F11;002:U6;002:BB5
DDRS_RAS
001:Y13;002:F11;002:U6;002:BB5
DDRS_CAS
001:X13;002:F11;002:U6;002:BB5
DDRS_WE
R2204
DDRS_ADDR[4]
150
R2205
DDRS_ADDR[5]
150
R2206
DDRS_ADDR[6]
150
R2207
DDRS_ADDR[7]
R2208
DDRS_ADDR[8]
150
R2209
150
150
R2210
R2211
DDRS_ADDR[10]
DDRS_ADDR[11]
150
R206
DDRS_ADDR[12]
150
R207
150
R208
150
R209
150
R210
150
R211
150
R212
150
R213
150
R214
DDRS_DATA[16]
DQ1
DDRS_DATA[17]
+1.8V_DDRS
+0.9VREFS
+0.9VREFS
+1.8V_DDRS
H7
DQ2
DDRS_DATA[18]
H3
DQ3
DDRS_DATA[19]
H1
DQ4
DDRS_DATA[20]
H9
DQ5
DDRS_DATA[21]
F1
DQ6
DDRS_DATA[22]
F9
DQ7
DDRS_DATA[23]
C8
DQ8
DDRS_DATA[24]
C2
DQ9
DDRS_DATA[25]
D7
DQ10
DDRS_DATA[26]
D3
DQ11
DDRS_DATA[27]
D1
DQ12
DDRS_DATA[28]
D9
DQ13
DDRS_DATA[29]
B1
DQ14
DDRS_DATA[30]
B9
DQ15
R256
4.7K
OPT
C1225
0.01uF
50V
C1219
0.1uF
16V
R282
4.7K
OPT
C1239
0.1uF
16V
R257
4.7K
OPT
L2
BA1
L3
DDRS_BA0
DDRS_ODT
001:W13
DDRS_DQS2
001:W13
DDRS_DQS3
001:Z13
DDRS_DM2
001:Z13
DDRS_DM3
R244
R248
100
OPT
100
OPT
001:W13
DDRS_DQS2
001:X13
DDRS_DQS3
A1
VDD5
E1
VDD4
J9
VDD3
M9
VDD2
R1
VDD1
L8
A9
VDDQ10
K7
C1
VDDQ9
CAS
L7
C3
VDDQ8
WE
K3
C7
VDDQ7
C9
VDDQ6
LDQS
E9
VDDQ5
F7
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
CK
J8
CK
K8
CKE
K2
ODT
K9
CS
RAS
UDQS
B7
LDM
F3
UDM
B3
For Termination of DDR
DDRS_ADDR[0-12]
001:K12;002:E16;002:W13;002:AK17
LDQS
E8
A3
VSS5
UDQS
A8
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
NC4
L1
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
001:Z13;002:F13;002:AK13;002:BB7
DDRS_BA1 001:AA13;002:F13;002:AK13;002:BB6
001:X13;002:F11;002:AK12;002:BB6
DDRS_CKE
001:X13;002:F12;002:AK12;002:BB6
DDRS_WE
001:X13;002:F11;002:AK11;002:BB5
DDRS_CAS
001:Y13;002:F11;002:AK11;002:BB5
DDRS_RAS
001:Y13;002:F11;002:AK11;002:BB5
VSSDL
DDRS_ODT
R283
4.7K
OPT
DDRS_DATA[31]
DDRS_ADDR[9]
DDRS_CS
C1243
0.01uF
50V
+0.9VTTS
DDRS_ADDR[1]
150
150
DQ0
G2
DDRS_ADDR[0]
150
150
200
001:V13;002:F12 DDRS_CLK
001:X13;002:F12;002:U7;002:BB6 DDRS_CKE
G8
+1.8V_DDRS
BA0
R245
001:K12;002:E16;002:AK17;002:BD12
C251
0.1uF
DDRS_ADDR[10]
6
DDRS_ADDR[0-12]
C249
0.1uF
DDRS_ADDR[9]
7
3
R280
4.7K
OPT
VTT_IN
001:N11;002:N17
C247
0.1uF
DDRS_ADDR[8]
2
R254
4.7K
OPT
VTT
001:K12;002:E16;002:W13;002:BD12
C245
0.1uF
A7
DDRS_ADDR[7]
N7
8
001:N11;002:AT17
C241
0.1uF
A3
DDRS_ADDR[3]
DDRS_ADDR[4]
+0.9VREF
+1.8V_DDRS
VDDL
001:Y13;002:F11;002:AK12;002:BB4
J7
J1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
150
C1235
0.1uF
VREF
DDRS_ADDR[0]
DDRS_ADDR[1]
DDRS_ADDR[0-12]
001:K12;002:W13;002:AK17;002:BD12
1
DDRS_DATA[0-31]
DDRS_DATA[0-31]
C239
0.1uF
+0.9VREFS
C262
0.1uF
16V
+1.8V_DDR
+1.8V_DDR
+0.9VREF
GND
IC201
H5PS5162FFR-S6C
C277
0.1uF
16V
IC203
BD35331F-E2
C1233
0.1uF
C217
0.1uF
16V
C1231
0.1uF
C214
0.1uF
16V
C1229
0.1uF
C211
0.1uF
16V
C208
0.1uF
16V
C1227
0.1uF
C205
0.1uF
16V
C1221
0.1uF
C202
0.1uF
16V
+0.9VREFS
+0.9VTTS
R2224
DDRS_ADDR[0]
150
R2225
DDRS_ADDR[1]
150
150
R2226
R2227
DDRS_ADDR[2]
DDRS_ADDR[3]
150
150
150
R2228
R2229
R2230
DDRS_ADDR[5]
150
R2231
150
R2232
DDRS_ADDR[4]
DDRS_ADDR[6]
DDRS_ADDR[7]
DDRS_ADDR[8]
150
R2233
150
R2234
DDRS_ADDR[9]
DDRS_ADDR[10]
150
R2235
DDRS_ADDR[11]
150
R267
DDRS_ADDR[12]
150
R268
150
R269
150
R270
150
R271
150
R272
150
R273
150
R274
150
R275
DDRS_BA0 001:Z13;002:F13;002:U8;002:AK13
DDRS_BA1 001:AA13;002:F13;002:U7;002:AK13
DDRS_CS
001:X13;002:F11;002:U7;002:AK12
DDRS_CKE 001:X13;002:F12;002:U7;002:AK12
DDRS_WE
001:X13;002:F11;002:U6;002:AK11
DDRS_CAS 001:Y13;002:F11;002:U6;002:AK11
DDRS_RAS 001:Y13;002:F11;002:U6;002:AK11
DDRS_ODT 001:Y13;002:F11;002:U5;002:AK12
3D + 240 FRC + TCON BOARD
DDR2 SDRAM
2009. 11. 13
2
10
LGE Internal Use Only
DDR2 SDRAM SOURCE POWER for FRC
1.8V DDR SDRAM POWER
MAIN 3.3V & 3.3V IO POWER
+1.8V_DDR
VLCD_POWER
IC307
SC4215ISTRT
VLCD_POWER
(+12V)
3
6
4
5
R301
22
VOUT
VIN_6
VIN_5
VIN_4
VIN_3
VIN_2
VIN_1
VLDO
V5V
4
P2
PGOOD
11
C317
22uF
16V
10
C374
22uF
16V
9
C377
22uF
16V
EN/SYNC
R310
100K
R307
100K
R306
C309
0.47uF
50V
OPT
EN/PSV
R309
(+12V) 12.4K
1%
R2
IC304
SC424MLTRT
28
FB
L305
C325
0.1uF
16V
TON
C338
0.1uF
50V
C371
22uF
16V
C368
0.01uF
OPT
C372
22uF
16V
3
6
4
5
ADJ
VO
C356
0.22uF
50V
NC_2
NC_3
R331
12K
1%
R2
C365
0.1uF
16V
C361
22uF
16V
C373
22uF
16V
+1.8V_DDRS
Vout= 0.8*(1+R1/R2)
IC308
SC4215ISTRT
C340
1000pF
OPT
BST
19
R335
10K
1%
R1
C369
100pF
50V
+2.5VQ
NC_1
R324
100K
PGND_6
18
PGND_5
17
PGND_4
16
PGND_3
14
PGND_2
3
C353
0.1uF
16V
ILIM
7
AGND_1
C349
10uF
10V
R334
39K
OPT
27
R318
100K
7
R330
15K
1%
R1
LXS
23
13
3.6uH
4.9A
24
1
2
GND
LXBST
12
39K
R320
8.2K
LX_4
P3
ENL
8
LX_3
21
25
3.3uH
4.1A
LX_2
20
1
L307
LX_1
15
22
FB
VLCD_POWER
BST
EN
VIN
+2.5VQ
R308
39K
1%
R1
8
C311
100pF
50V
OPT
5
C308
1uF
50V
VCC
PGND_1
C302
0.1uF
7
P1
SW_2
2
C320
10uF
25V
GND
AGND_3
C301
22uF
25V
8
NC_1
R323
91K
2
SW_1
1
Vout= 0.8*(1+R1/R2)
Vout= 0.8*(1+R1/R2)
+2.5VQ
L304
120-ohm
26
IN
+3.3V
6
IC301
MP8706EN-C247-LF-Z
C334
0.1uF
50V
AGND_2
L301
120-ohm
C330
1uF
25V
1
EN
VIN
C350
10uF
10V
R338
4.3K
1%
R2
C354
0.1uF
16V
C357
0.22uF
50V
NC_2
GND
8
2
7
3
6
4
5
ADJ
R332
15K
1/10W
1%
R1
VO
NC_3
R333
12K
1/10W
1%
R2
C366
0.1uF
16V
C362
22uF
16V
1.0V DIGITAL CORE POWER
DDR2 SDRAM SOURCE POWER for FPGA
+3.3V
VLCD_POWER
L303
120-ohm
L310
2V5
IC310
MP8706EN-C247-LF-Z
120-ohm
R305
1.8V FPGA DDR SDRAM POWER
Vout= 0.8*(1+R1/R2)
100K
IN
C304
100pF
R302
3K
1%
R1
R303
9.1K
1%
R2
Vout= 0.8*(1+R1/R2)
IC302
MP2212DN
FB
GND
1
C314
0.22uF
50V
8
2
7
3
6
SW_1
EN/SYNC
+1.0VDC
C321
22uF
25V
SW_2
C326
0.1uF
L306
3.6uH
SW_2
C303
22uF
16V
C306
10uF
BS
4
5
SW_1
C315
0.1uF
50V
VCC
C316 C318
22uF 22uF
16V
16V
2
7
3
6
GND
1V8
2V5
C335
1uF
50V
VCC
C339
100pF
50V
OPT
C375
22uF
16V
R336
10K
1%
R1
C376
22uF
16V
FB
NC_1
4
5
EN/SYNC
(+12V)
R321
100K
C337
0.47uF
50V
C319
0.1uF
16V
R319
R322
100K
R337
4.7K
1%
R2
EN
VIN
39K
C352
0.1uF
16V
C348
10uF
10V
L314
3.6uH
4.9A
6.3V
OPT
Vout= 0.8*(1+R1/R2)
IC306
SC4215ISTRT
C370
22uF
16V
VLCD_POWER
BST
R311
22
NR8040T3R6N
IN
8
1
C355
0.22uF
50V
NC_2
1
8
2
7
3
6
4
5
R327
15K
1/10W
1%
R1
GND
ADJ
VO
R328
12K
1/10W
1%
R2
NC_3
C360
22uF
16V
C364
0.1uF
16V
R304
10
1%
C312
1uF
10V
1.2V FPGA CORE POWER
+3.3V
Vout= 0.8*(1+R1/R2)
1.8V FPGA DDR SDRAM VTT & VREF
L308
120-ohm
R314
100K
C327
R312
10K
R313
0
100pF
C332
0.47uF
50V
R317
5.1K
C310
22uF
16V
OPT
IC305
MP2212DN
C305
22uF
16V
C344
10uF
16V
C307
22uF
16V
IC309
BD35331F-E2
C347
0.1uF
16V
1V8
IN
OPT
C322
22uF
16V
C323
0.1uF
50V
C324
22uF
16V
BS
1
8
2
7
3
6
4
5
1V2
EN/SYNC
L309
3.6uH
SW_2
VTTS
C331
22uF
16V
SW_1
C333
0.1uF
50V
L311
BLM18PG121SN1D
C336
22uF
16V
OPT
VCC
DDR_VREF1
OPT
D302
1N4148W_DIODES
0.1uF
C329
1uF
25V
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C346
0.1uF
16V
8
2
7
3
6
4
5
C358
0.1uF
16V
VTT
VTT_IN
VCC
VDDQ
R329
220
C363
2.2uF
10V
C359
10uF
25V
C367
0.1uF
16V
C328
R316
10
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C343
0.1uF
16V
OPT
C351
0.1uF
16V
VREF
1
L312
BLM18PG121SN1D
R315
10
100V
EN
DDR_VREF0
OPT
R326
1M
FB
R325
10K
GND
GND
+3.3V
DDR_VTT
C342
0.1uF
16V
C345
0.1uF
16V
3D + 240 FRC + TCON BOARD
FRC & FPGA Power Block
2009. 11. 13
3
10
LGE Internal Use Only
TCON_SCL_M
001:AF18;004:AA10;004:AL20;005:AA15
TCON_SDA_M
001:AF18;004:AE10;004:AL20;005:AA14
+1.8V_TCON_M
33
33
R444
004:G8
004:K5
BIT_SEL_M
FRC_ON_M
TCON_AGP_M 004:AC20
004:C5
REVERSE_M
L400
120-ohm
R443
LVDS_SEL_M 004:C8
[T-CON LEFT => Master]
+1.8V_TCON
C400
0.1uF
16V
C402
0.1uF
16V
C404
0.1uF
16V
C409
0.1uF
16V
C412
0.1uF
16V
C410
0.1uF
16V
C414
1uF
10V
C416
1uF
10V
+3.3V_TCON
+3.3V_TCON_M
TD8TD8+
TE8-
004:AA3;009:Y16
TE8+
OGND_5
OVDD_5
OGND_6
TCON_AGP
157
158
159
CGND_7
CGND_8
SCLKI
EOVDD_1
EOVSS_1
NC
SCLKO
EOVDD_2
EOVSS_2
CVDD_7
CGND_9
EOVDD_3
OGND_7
OVDD_6
CVDD_6
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
EIVSS_4
OGND_8
176
177
178
EIVDD_4
C10S8
REVERSE
OVDD_7
OGND_9
CVDD_8
EOVSS_3
EOVDD_4
OVDD_8
CGND_10
OGND_10
EOVDD_5
FRCON
179
180
181
182
183
184
185
186
187
188
189
190
SDA
SCL
EOVSS_4
191
192
193
194
CVDD_9
EOVDD_6
DISN
OVDD_9
INT_VCO2
EOVDD_7
EOVSS_6
CVDD_10
CGND_11
INT_SSC2
OGND_11
CVDD_11
LVDD_5
EOVSS_5
195
196
197
198
199
200
201
202
203
204
205
206
23
134
RLV8-
R2DP
24
133
LLV0+
R2EN
25
132
LLV0-
R2EP
26
131
NLVSS_4
R3AN
27
130
LLV1+
R3AP
28
129
LLV1-
R3BN
29
128
LLV2+
R3BP
30
127
LLV2-
LVDD_2
31
126
NLVDD_3
R3CN
32
125
LLV3+
R3CP
33
124
LLV3-
R3CLKN
34
123
LLV4+
R3CLKP
35
122
LLV4-
LGND_2
36
121
NLVSS_3
R3DN
37
120
LLV5+
R3DP
38
119
LLV5-
R3EN
39
118
LLV6+
R3EP
40
117
LLV6-
R4AN
41
116
NLVDD_2
R4AP
42
115
LLV7+
R4BN
43
114
LLV7-
R4BP
44
113
NLVSS_2
R4CN
RRMV6N
008:AE10
RRMV6P
008:AE10
RRMV5N
008:AE10
RRMV5P
008:AE11
RRMV4N
008:AE11
RRMV4P
008:AE11
RRMVCLKN
008:AE11
RRMVCLKP
008:AE12
R422
2K
R425
2K
R427
2K
NC/E0
MS_SEL_M
NC/E1
VCO_SYNC_M004:P10
RRMV2N
008:AE12
RRMV2P
008:AE12
RRMV1N
008:AE12
112
LLV8+
111
LLV8-
110
NLVSS_1
R4CLKP
48
109
NLVDD_1
R4DN
49
108
RNLVDS
R414
18K
R4DP
50
107
CGND_6
42/47LX6500
R4EN
51
106
CVDD_5
105
CGND_5
+3.3V_TCON_M
RRMV1P
008:AE13
RRMV0N
008:AE13
RRMV0P
008:AE13
RLMV6N
008:AE13
RLMV6P
008:AE14
RLMV5N
008:AE14
RLMV5P
008:AE14
RLMV4N
008:AE14
RLMV4P
008:AE14
+3.3V_TCON_M
R416
2K
OPT
R418
2K
OPT
R426
2K
OPT
R423
2K
OPT
TA5-
R408
3.3K
TB5TC5-
OPT
R403
10K
Reverse option Selection
L : Normal operation
H : Reverse operation
RBF_M
R407
10K
1
8
2
7
VSS
3
6
4
5
R448
3.3K
OPT
004:J10
When No Video input, Pattern Selection
L:Black Pattern
H:Rotate Pattern
R409
10K
OPT
FRC_ON_M 004:O26
FRC Funtion Seletion
L:Disable(8Bit)
H:Enable(10Bit(D))
RLMVCLKN
008:AE15
RLMVCLKP
008:AE15
RLMV2N
008:AE15
RLMV2P
008:AE16
RLMV1N
008:AE16
RLMV1P
008:AE16
RLMV0N
008:AE16
RLMV0P
008:AE16
GOE
008:AE23;008:AL12
R434
3.3K
WP_EEPROM_TCON001:AD21;005:AJ5
SCL
TCON_SCL_M
001:AF18;004:L27;004:AA10;005:AA15
SDA
TCON_SDA_M
001:AF18;004:L27;004:AE10;005:AA14
008:AE18;008:AL18
GSC
008:AE23;008:AL12
C431
10pF
OPT
R447
33
R437
33
GSP
008:AE18;008:AL18
FLK_A
004:L10
DPM
007:W8;006:D12;006:Q5
DPM_A
004:L10
FLK
006:D12
C421
10pF
C408
10pF
OPT
R420
33
GSP_R_A
004:M10
R446
33
GSC_A
004:M10
C420
220pF
OPT
R419
33
GSP_A
004:M10
R414-*1
24K
55LX6500
R424
270
R438
220
SOE_L
004:R10;004:AF13
008:AL18
SOE_A
SOE_R
008:AE17
004:R10;004:AA13
R477
0
OPT
C436
10pF
OPT
50V
OPT
R480
0
OPT
C422
10pF
OPT_N
OPT_P
008:AE24
008:AE17;008:AL19
001:AF18;005:J26;005:AA13;005:AJ4
[TCON Reset Block]
1
6
2
5
3
4
001:AF18;004:L27;004:AL20;005:AA14
TCON_SDA_M
+3.3V_TCON
TCON_SDA001:AO39
TCON_SDA_S
001:AF17;005:J26;005:AA13;005:AJ4
R440
6.8K
R445
1K
R475
33
I2CEN
R476
33
TD6TE6-
R450
10K
I2CEN_S
R441
20K
1%
TCON_RST
004:K10;005:I9
R449
10K
R451
100
R452
100
R453
100
R454
100
R455
100
R456
100
R457
100
R458
100
R459
100
R460
R461
R462
100
TC6TCLK6-
Q400
2SA1530A-T112-1R
I2CEN_M
TE5-
TA6-
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C435
1uF
10V
WC
POL
POL_A
004:R10
C406
10pF
OPT
001:AO39 TCON_SCL
TD5-
TB6-
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
R433
3.3K
R436
100
R421
33
GOE_A
004:M10
SW400
JS2235S
TCLK5REVERSE_M 004:N26
C433
1uF
10V
C432
1uF
10V
R428
2K
OPT
0 R479
0 R478
SOE_A
004:AC20 SSC_SYNC_M
POL_A
004:AF17
004:AC20 VCO_SYNC_M
H_CONV
004:X8;004:AC21 I2CEN_M
004:AC21
004:AA14
GSC_A
GOE_A
GSP_A
004:AA15
004:AK17
004:AA17
DPM_A
MS_SEL_M
1K
1%
C430
1uF
10V
C429
0.1uF
16V
Write Protection
Low/NC : Normal Operation
High : Write Protection
EIVDD_3
EIVSS_3
OGND_4
FSEL
OPT_N
OPT_P
SOE
POL
SSC_SYNC
OVDD_4
CGND_4
CVDD_4
OGND_3
OVDD_3
TESTC
TESTB
TESTA
CGND_3
VCO_SYNC
CVDD_3
I2C_EN
H_CONV
EIVDD_2
VCORES
N_S_SEL
OGND_2
EIVSS_2
CVDD_2
CGND_2
OVDD_2
GSP_R
GSP
GSC
GOE
OGND_1
OVDD_1
FLK1
DPN
004:AK15
PWM_SEQ
GSP_R_A
R413
C427
0.1uF
16V
VCC
+3.3V_TCON_M
R406
3.3K
R402
3.3K
OPT
1K
1%
NC/E2
TCON_AGP_M004:S26
TCON_SCL_S
004:AA13;004:AF13
L:8bit
H:10bit
005:I25 INT_VCO1_M
004:AF15
FLK_A
004:G5
10bit or 8bit Seletion
R412
008:AE17;008:AL18
L:VESA format
H:JEIDA format
R405
10K
OPT
001:AF20;005:I9
LVDS Data mapping seletion
005:H25 INT_SSC1_M
004:AN7;005:I9 TCON_RST
RBF_M
R401
10K
BIT_SEL_M004:O26
C426
0.1uF
16V
50V
0
INT_VCO1
R411
PAT_DET
PWR_SEO
CVDD_1
RESET
0
R410
INT_SSC1
RBF
CGND_1
EIVDD_1
EIVSS_1
LGND_4
LVDD_4
LGND_3
LVDD_3
LVDS_SEL_M004:K26
+1.8V_TCON_M
C425
0.1uF
16V
I2C Slave Address : 0xA0
47
R404
3.3K
C424
0.1uF
16V
SSC_SYNC_M004:R10
001:AF18;004:L27;004:AL20;005:AA15
TCON_SCL_M
R400
3.3K
OPT
C423
0.1uF
16V
004:N10
I2CEN_M004:O10;004:X8
46
+3.3V_TCON_M
C419
0.1uF
16V
C428
0.1uF
16V
R417
2K
SOE_A
+3.3V_TCON_M
C418
0.1uF
16V
IC401
M24C16-WMN6T
R415
2K
45
52
C417
0.1uF
16V
+3.3V_TCON_M
R4CP
R4EP
C415
0.1uF
16V
+3.3V_TCON
R4CLKN
53
004:X3;009:Y16
135
R2DN
C413
0.1uF
16V
C411
0.1uF
16V
DPM_CTRL1
004:L10
004:X3;009:Y14
004:AA3;009:Y14
22
RLV8+
C407
0.1uF
16V
C405
0.1uF
16V
DPM_CTRL
001:AJ20
TC8-
TC8+
004:X3;009:Y13TCLK8004:AA3;009:Y13TCLK8+
NLVDD_4
C403
0.1uF
16V
104
004:X3;009:Y11
004:AA3;009:Y11
RLV7-
136
103
TB8+
137
21
LGND_1
102
TB8-
20
R2CLKP
101
004:X3;009:Y11
004:AA3;009:Y10
R2CLKN
100
TA8+
RLV7+
99
004:AA4;009:Y12
RLV6-
138
98
TA8-
RLV6+
139
19
97
004:X4;009:Y13
140
18
R2CP
96
TE7TE7+
17
R2CN
95
TD7+
004:X5;009:Y14
004:AA5;009:Y14
LVDD_1
94
004:AA5;009:Y12
16
93
TD7-
R2BP
92
004:X5;009:Y12
141
NLVSS_5
IC400
TL2425MC (GLORY)
91
004:X5;009:Y10TCLK7004:AA5;009:Y10TCLK7+
RLV5-
15
90
TC7+
RLV5+
142
14
R2BN
89
004:AA5;009:Y9
RLV4-
143
13
R2AP
88
TC7-
144
R2AN
87
004:X5;009:Y9
RLV4+
86
TB7TB7+
145
85
004:X5;009:Y8
004:AA5;009:Y8
12
84
TA7TA7+
R1EP
83
TE6+
004:X6;009:Y6
146
82
004:U3;009:Y7
004:AA6;009:Y6
11
NLVDD_5
81
TE6-
R1EN
80
004:R3;009:Y7
RLV3-
79
TD6+
147
78
TD6-
004:U3;009:Y7
10
R1DP
004:R3;009:Y5 TCLK6004:U3;009:Y5 TCLK6+
004:R3;009:Y8
RLV3+
77
TC6+
148
76
TC6-
004:U3;009:Y5
9
75
004:R3;009:Y6
149
R1DN
74
TB6+
8
RLV2-
73
004:U3;009:O15
R1CLKP
72
TB6-
RLV2+
71
004:R3;009:O15
150
70
TA6+
7
69
TE5+
TA6-
004:U4;009:O14
R1CLKN
68
004:U5;009:O13
004:R4;009:O14
NLVSS_6
67
TE5-
RLV1-
151
66
004:R5;009:O14
RLV1+
152
6
65
TD5+
153
5
R1CP
64
004:U5;009:O12
4
R1CN
63
TD5-
R1BP
62
004:R5;009:O12
NLVDD_6
61
004:R5;009:O13TCLK5004:U5;009:O13TCLK5+
RLV0-
154
60
TC5+
RLV0+
155
3
59
TC5-
004:U5;009:O11
156
2
R1BN
58
TB5+
004:R5;009:O11
1
R1AP
57
004:U5;009:O10
C401
0.1uF
16V
R1AN
56
TB5-
55
TA5TA5+
54
004:R6;009:O8
004:U6;009:O7
004:R5;009:O10
207
+3.3V_TCON_M +1.8V_TCON_M
208
LGND_5
L401
120-ohm
100
100
TA5+
TB5+
TC5+
TCLK5+
TA7TB7TC7TCLK7-
TE5+
TD7TE7-
TD5+
TA6+
TA8-
TB6+
TB8-
TC6+
TC8-
TCLK6+
TD6+
TE6+
TCLK8TD8TE8-
R463
100
R464
100
R465
100
R466
100
R467
100
R468
100
R469
100
R470
100
R471
100
R472
100
R473
100
R474
100
C434
0.47uF
50V
TA7+
TB7+
TC7+
TCLK7+
TD7+
TE7+
TA8+
TB8+
TC8+
TCLK8+
TD8+
TE8+
3D + 240 FRC + TCON BOARD
240Hz T-Con (Master,Left)
2009. 11. 13
4
10
LGE Internal Use Only
005:F6
005:K3
FRC_ON_S
TCON_AGP_S 005:AD23
005:B3
BIT_SEL_S
+3.3V_TCON
C500
0.1uF
16V
+3.3V_TCON_S
L501
120-ohm
C502
0.1uF
16V
C504
0.1uF
16V
C507
0.1uF
16V
C510
0.1uF
16V
C508
0.1uF
16V
C512
1uF
10V
C503
0.1uF
16V
C501
0.1uF
16V
C515
1uF
10V
C506
0.1uF
16V
C505
0.1uF
16V
C513
0.1uF
16V
C511
0.1uF
16V
C509
0.1uF
16V
R515
2K
R517
2K
R519
2K
005:Y4;009:O31
TB2+
005:W4;009:O26
TC2-
005:Y4;009:O27
TC2+
005:W3;009:O27 TCLK2005:Y3;009:O28 TCLK2+
005:W3;009:O35
TD2-
005:Y3;009:O35
TD2+
005:W3;009:O30
TE2TE2+
25
132
LLV0-
R2EP
26
131
NLVSS_4
R3AN
27
130
LLV1+
R3AP
28
129
LLV1-
R3BN
29
128
LLV2+
R3BP
30
127
LLV2-
31
126
NLVDD_3
R3CN
32
125
LLV3+
R3CP
33
124
LLV3-
R3CLKN
34
123
LLV4+
R3CLKP
35
122
LLV4-
LGND_2
36
121
NLVSS_3
R3DN
37
120
LLV5+
R3DP
38
119
LLV5-
R3EN
39
118
LLV6+
R3EP
40
117
LLV6-
R4AN
41
116
NLVDD_2
R4AP
42
115
LLV7+
R4BN
43
114
LLV7-
R4BP
44
113
NLVSS_2
R4CN
45
112
LLV8+
R4CP
46
111
LLV8-
R4CLKN
47
110
NLVSS_1
R4CLKP
48
109
NLVDD_1
R4DN
49
108
RNLVDS
R4DP
50
107
CGND_6
R4EN
51
106
CVDD_5
R4EP
52
105
CGND_5
008:AL19
LRMV5P
008:AL20
LRMV4N
008:AL20
LRMV4P
008:AL20
LRMVCLKN
008:AL20
LRMVCLKP
008:AL21
LRMV2N
008:AL21
LRMV2P
008:AL21
LRMV1N
008:AL21
LRMV1P
008:AL22
LRMV0N
008:AL22
LRMV0P
008:AL22
+3.3V_TCON
C525
1uF
10V
C526
1uF
10V
C527
1uF
10V
C528
1uF
10V
+3.3V
L502
120-ohm
L503
120-ohm
OPT
+3.3V_FET
+3.3V_FET
LLMV6N
008:AL22
LLMV6P
008:AL23
LLMV5N
008:AL23
LLMV5P
008:AL23
LLMV4N
008:AL23
LLMV4P
008:AL23
LLMVCLKN
008:AL24
LLMVCLKP
008:AL24
LLMV2N
008:AL24
LLMV2P
008:AL25
LLMV1N
008:AL25
LLMV1P
008:AL25
LLMV0N
008:AL25
LLMV0P
008:AL25
C535
R595 R596 R597
3.3K 3.3K 3.3K
OPT OPT OPT
001:E19;008:F18;008:V24;008:AL4;009:AP8
R599
I2C_SCL
R1500
I2C_SDA
001:E19;008:N18;008:V25;008:AL4;009:AP11
R512
18K
C533
10pF
OPT
C534
10pF
OPT SCL0
33
SDA0
33
001:AF19
M_TCON_EN
33
R1502
33
R1503
EN1
33
R1506
2K
TCON_SCL_S
R512-*1
24K
55LX6500
TCON_SDA_S
1
16
2
15
3
14
4
13
5
12
VCC
EN4
2K
R1512
R1501
SDA1
TCON_SDA_M
0.1uF
IC502
PA9516APW
SCL1
TCON_SCL_M
42/47LX6500
R598
3.3K
OPT
R1513
3.3K
OGND_5
OVDD_5
OGND_6
CVDD_6
CGND_7
CGND_8
SCLKI
EOVDD_1
EOVSS_1
NC
SCLKO
EOVDD_2
EOVSS_2
CVDD_7
CGND_9
EOVDD_3
OGND_7
OVDD_6
OGND_8
TCON_AGP
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
EIVSS_4
FRCON
C10S8
REVERSE
OVDD_7
OGND_9
CVDD_8
EOVSS_3
EOVDD_4
OVDD_8
CGND_10
OGND_10
EIVDD_4
178
179
180
181
182
183
184
185
186
187
188
189
EOVDD_5
190
191
EOVSS_4
SCL
CVDD_9
EOVSS_5
SDA
192
193
194
195
196
EOVDD_6
OVDD_9
INT_VCO2
EOVDD_7
DISN
197
198
199
200
201
EOVSS_6
CGND_11
INT_SSC2
OGND_11
CVDD_11
LVDD_5
LGND_5
CVDD_10
202
203
204
205
206
207
208
R2EN
53
005:Y3;009:O30
C524
0.1uF
16V
R522
2K
OPT
R1515
3.3K
TB2-
LLV0+
008:AL19
LRMV5N
R520
2K
OPT
R1516
3.3K
TA2+
005:W4;009:O31
133
008:AL19
LRMV6P
R518
2K
OPT
005:Q25
R1519
OPT 0
TA2-
005:Y4;009:O32
24
LRMV6N
R516
2K
OPT
005:P9
TCON_AGP_S
R1514
3.3K
005:W4;009:O32
C523
0.1uF
16V
005:N9
SSC_SYNC_S
R1518
OPT 0
TE1+
134
R2DP
R514
2K
R1504
33
R1505
33
SDA4
SCL4
EN3
2K
R1511
SCL2
SDA2
GND
104
005:Y5;009:O29
23
RLV8-
103
TE1-
RLV8+
102
TD1+
005:W5;009:O28
NLVDD_4
135
101
005:Y6;009:Y35
136
22
R2DN
100
005:Y6;009:Y35 TCLK1+
TD1-
21
LGND_1
LVDD_2
005:W6;009:Y35 TCLK1-
005:W6;009:Y35
R2CLKP
99
TC1+
RLV7-
98
TC1-
005:Y6;009:Y36
RLV7+
137
97
005:W6;009:Y36
138
20
96
TB1+
19
95
005:Y6;009:Y32
R2CP
R2CLKN
94
TB1-
RLV6-
93
TA1+
005:W6;009:Y32
RLV6+
139
92
TA1-
005:Y6;009:Y30
NLVSS_5
140
18
91
005:W6;009:Y30
141
17
90
TE4+
16
R2CN
89
005:T3;009:Y34
R2BP
LVDD_1
88
TE4-
15
IC500
TL2425MC (GLORY)
87
005:Q3;009:Y34
142
RLV5-
14
R2BN
86
TD4+
RLV5+
13
R2AP
85
TD4-
005:T3;009:Y33
RLV4-
143
R2AN
84
005:Q3;009:Y33
144
12
83
005:T3;009:Y26 TCLK4+
145
RLV4+
82
005:Q3;009:Y25 TCLK4-
NLVDD_5
81
TC4+
146
80
005:T3;009:Y25
11
R1EP
79
TC4-
R1EN
78
005:Q3;009:Y24
147
77
TB4+
10
RLV3-
76
TB4-
005:T4;009:Y33
RLV3+
75
005:Q4;009:Y32
RLV2-
148
74
TA4+
149
9
R1DP
73
TA4-
005:T4;009:Y29
8
R1DN
72
005:Q4;009:Y29
R1CLKP
71
TE3+
150
70
005:T5;009:Y31
7
RLV2+
69
TE3-
NLVSS_6
R1CLKN
68
005:Q5;009:Y31
151
67
TD3+
6
66
005:T6;009:Y31
RLV1-
R1CP
65
TD3-
RLV1+
152
64
005:Q6;009:Y30
NLVDD_6
153
5
63
005:T6;009:Y29 TCLK3+
154
4
R1CN
62
005:Q6;009:Y29 TCLK3-
3
R1BP
61
TC3+
R1BN
60
005:T6;009:Y27
RLV0-
59
TC3-
RLV0+
155
58
TB3+
005:Q6;009:Y27
156
2
57
TB3-
005:T6;009:Y28
1
R1AP
56
005:Q6;009:Y28
C522
0.1uF
16V
C521
0.1uF
16V
004:X7;005:M9
VCO_SYNC_S
R1AN
55
TA3+
54
TA3-
005:T6;009:Y27
C520
0.1uF
16V
C519
0.1uF
16V
005:L9
MS_SEL_S
005:Q6;009:Y26
C518
0.1uF
16V
R521
2K
I2CEN_S
+1.8V_TCON_S
C517
0.1uF
16V
+3.3V_TCON_S
R513
2K
OPT
+3.3V_TCON_S
C516
0.1uF
16V
R1517
OPT 0
TCON_SDA_S
001:AF17;004:AE9;005:AA13;005:AJ4
R525 33
+1.8V_TCON_S
L500
120-ohm
REVERSE_S
001:AF18;004:AA9;005:AA13;005:AJ4
TCON_SCL_S
R524 33
004:L10
INT_VCO1_M
LVDS_SEL_S 005:B6
004:K10
[T-CON RIGHT => Slave]
INT_SSC1_M
+1.8V_TCON
6
11
7
10
8
9
SDA3
SCL3
EN2
R1508 S_TCON_EN
33
LVDS_SEL_S 005:I25
R501
10K
LVDS Data mapping seletion
L:VESA format
H:JEIDA format
+3.3V_TCON_S
R505
10K
OPT
10bit or 8bit Seletion
L:8bit
H:10bit
R510
TA3-
1K
1%
TB3TC3TCLK3-
R511
1K
1%
TD3-
+3.3V_TCON
R527
100
R528
100
R529
100
R530
100
R531
100
R532
100
RBF_S
R507
10K
TB1TC1TCLK1-
100
100
R542
100
R543
100
R544
100
TD1TE1-
100
R540
R541
TA1+
TB1+
FRC_ON_S 005:M25
005:H9
When No Video input, Pattern Selection
L:Black Pattern
H:Rotate Pattern
R509
10K
OPT
IC501
M24C16-WMN6T
TC1+
TCLK1+
TC4-
FRC Funtion Seletion
L:Disable(8Bit)
H:Enable(10Bit(D))
TD4TE4-
R545
R533
100
R534
100
R535
100
R536
TA4+
TB4+
100
R537
100
R538
100
TA2TB2TC2-
TC4+
TCLK4+
TD4+
TE4+
TCLK2TD2TE2-
C514
0.1uF
16V
TD1+
TE1+
NC/E0
NC/E2
TA4-
Reverse option Selection
L : Normal operation
H : Reverse operation
TD3+
TA1-
NC/E1
TCLK4R503
10K
TC3+
TE3+
TB4REVERSE_S 005:L25
R539
TA3+
TB3+
TCLK3+
TE3-
R508
3.3K
R1520
[TCON EEPROM(16Kbit)]
+3.3V_TCON_S
R506
3.3K
OPT
OPT 0
EIVDD_3
EIVSS_3
OGND_4
FSEL
OPT_N
OPT_P
SOE
POL
SSC_SYNC
005:AD23 SSC_SYNC_S
OVDD_4
CGND_4
CVDD_4
OGND_3
OVDD_3
TESTC
TESTB
TESTA
CGND_3
CVDD_3
VCO_SYNC
005:AD24 VCO_SYNC_S
004:X7;005:AD24I2CEN_S
I2C_EN
H_CONV
EIVDD_2
VCORES
005:AD24
MS_SEL_S
N_S_SEL
OGND_2
EIVSS_2
CVDD_2
CGND_2
OVDD_2
GSP
GSC
GSP_R
GOE
DPN
OGND_1
FLK1
OVDD_1
INT_VCO1
PAT_DET
PWR_SEO
PWM_SEQ
+1.8V_TCON_S
BIT_SEL_S 005:M25
+3.3V_TCON_S
R502
3.3K
OPT
001:AF20;004:K10
R504
3.3K
CVDD_1
RESET
INT_SSC1
RBF_S
R500
3.3K
OPT
TCON_RST
+3.3V_TCON_S
005:F3
+3.3V_TCON_S
004:K10;004:AN7
RBF
CGND_1
EIVDD_1
EIVSS_1
LGND_4
LVDD_4
LGND_3
LVDD_3
001:AF19
R1507
2K
1
8
2
7
3
6
4
5
R526
3.3K
OPT
R551
3.3K
R552
3.3K
VCC
WC
WP_EEPROM_TCON001:AD21;004:AL21
SCL
TCON_SCL_S
001:AF18;004:AA9;005:J26;005:AA13
100
R546
100
R547
100
TA2+
TB2+
R548
100
R549
100
R550
100
VSS
SDA
TCON_SDA_S
001:AF17;004:AE9;005:J26;005:AA13
TC2+
TCLK2+
TD2+
TE2+
Write Protection
Low/NC : Normal Operation
High : Write Protection
I2C Slave Address : 0xA0
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3D + 240 FRC + TCON BOARD
240Hz T-Con(Slave,Right)
2009. 11. 13
5
10
LGE Internal Use Only
VDD_LCM
(+16V)
C660
10uF
25V
C649
10uF
25V
C662
10uF
25V
C664
10uF
25V
C668
10uF
25V
C666
10uF
25V
C676
10uF
25V
C674
10uF
25V
C672
10uF
25V
C670
10uF
25V
[POWER-VDD/VCC/VGH/VGL]
VDD_LCM
(+16V)
VLCD_POWER
(+12V)
R615
1K
R616
1K
L600ONSEMI_DIODE
22uH
D603
2.2A
SMAB34
VCOMROUT
40V
KEC_DIODE
R623
5.6K
VLCD_LCM_OUT
(+16V)
VCOMLFB
0
R618
1K
R617
1K
C624
680pF
50V
R625
5.1K
R629
5.1K
1%
OGND
OUT2
POS2
NEG2
AVIN
SWO
FB
NC_3
SWI
SW_2
SW_1
46
45
44
43
42
41
40
39
38
37
PGND1
C642
4
33
EN1
OPT
VFLK
5
32
EN2
31
VC
IC600
TPS65162RGZR
6
7
30
SS
VGHM
8
29
DLY2
VGH
9
28
FREQ
FBP
10
27
VIN
D600
BAV99W_NXP
R606
OPT
R645
4.7K
C602
10uF
35V
C603
10uF
35V
C688
10uF
35V
C689
10uF
35V
R612
18K
1%
24
C605
1uF
50V
R614
27K
1%
C690
1uF
50V
C638
10uF
25V
C635
10uF
25V
C640
10uF
25V
C644
10uF
25V
C645
10uF
25V
C646
10uF
25V
C647
10uF
25V
C648
10uF
25V
C641
0.1uF
50V
R636
7.5K
5%
VDD_LCM
(+16V)
VLCD_POWER
(+12V)
C651
10uF
25V
VLCD_POWER
(+12V)
C652
10uF
25V
C653
10uF
25V
C654
10uF
25V
C655
10uF
25V
C656
10uF
25V
C657
10uF
25V
C658
10uF
25V
DPM_VDD 006:S16;006:S5
VLCD_POWER
(+12V)
C627
22000pF
50V
22000pF
50V
R632
10
1/10W
1%
C623
10uF
25V
C628
22uF
25V
C631
22uF
25V
C634
22uF
25V
C637
22uF
25V
VCC_LCM
(+3.3V)
2.2A
C613
0.22uF
16V
C608
0.47uF
50V
C632
10uF
25V
L601
22uH
C612
0.047uF
50V
OPT
C607
1uF
25V
C630
10uF
25V
C621
22000pF
50V
C618
1uF
25V
SWB_2
SWB_1
FBB
NC_2
NC_1
SUP
DRVN
23
PVIN_1
22
25
21
12
20
26
DRVP
19
11
PVIN_2
18
GND
VLCD_LCM_OUT
(+12V)
R611
220K
1%
1/16W
C625
RE
CBOOT
R604
4.7K
C677
10uF
25V
0
NEG1
47
PGND2
34
DLY1
42LX6500
48
35
3
CE
VDPM
R610
200
42LX6500
C604
68pF
50V
2
VDD
17
R607
82K
5%
OUT1
REF
C600
1uF
25V
VGH_M
(+24V)
C601
100pF
50V
OPT
PGND3
16
R608
200
DPM
36
FBN
R603
0
1
15
47LX6500 47LX6500
FLK
C675
10uF
25V
VDD_LCM
(+16V)
R646
0
OPT R630
15K
R626
5.6K
POS1
13
VGH_I
(+27V)
R610-*1
330
AGND
004:AI15
007:W8;004:AN15;006:Q5
R613
0
OPT
14
R608-*1
300
VCOMLOUT
008:AL13
0
R610-*2
180
55LX6500 55LX6500
C673
10uF
25V
DPM_VDD 006:Q12;006:S5
R624
30K
1%
1/16W
C606
1uF
25V
R609
R605
330K
1%
1/8W
C671
10uF
25V
100V
008:N25 P_VCOM
R602
0
5%
1/10W
C669
10uF
25V
C629
0.1uF
50V
C626
22uF
25V
C617
22000pF
50V
VDD_LCM
(+16V)
R608-*2
150
C667
10uF
25V
OPT
R639
C665
10uF
25V
D604
R637
0
OPT
008:AL13
C622
22uF
25V
R633
0
C663
10uF
25V
1K
R638
VCOMRFB
R634
008:AE22
VLCD_LCM_OUT
(+16V)
TCON_POWER_EN
001:AJ20;007:Q15
008:AE22
C661
10uF
25V
C650
10uF
25V
D603-*1
C615
22uF
25V
C611
22uF
25V
C616
0.1uF
50V
D602
40V
SMAB34
KEC_DIODE
C619
470pF
50V
R627
4.7K
1%
C620
470pF
50V
OPT
R628
1.3K
1%
C633
22uF
16V
R631
3.9K
1%
C636
22uF
16V
C639
22uF
16V
R635
5.1K
D602-*1
VGL(-7V)
R619
33K
1%
ONSEMI_DIODE
R620
100K
1%
VGH_I
(+24V)
VGL
(-5V)
1/16W
1%
VGH
(+24V)
R621
30K
D601
BAV99W_NXP
R600 0
OPT
VGH_M
(+24V)
C609
10uF
10V
C610
C614
10uF
10V
10uF
10V
R622
1K
1%
R640
33
R601 0
DPM
007:W8;004:AN15;006:D12
DPM_VDD
006:Q12;006:S16
C643
10pF
OPT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3D + 240 FRC + TCON BOARD
Power Block (TCON)
2009. 11. 13
6
10
LGE Internal Use Only
VLCD_POWER
(+12V)
C704
0.1uF
50V
VLCD_POWER
(+12V)
C730
22uF
25V
C711
22uF
25V
Q700
SI4804BDY
Q702
SI4804BDY
R728
10
R719
10
C713
2200pF
50V
R707
R716
10K
R2
6.8K
1%
C717
2200pF
50V
C716
47pF
50V
LX1
BST1
2
7
+1.8V_TCON
L702
10uH
3.1A
D2_2
R1
D1_1
8
PGND1
DL2
5
DL1
PGOOD2
15
4
PGOOD1
VCC
16
MAX15023ETG+T 3
EN2
FB2
17
2
EN1
COMP2
18
1
FB1
IC700
C708
22uF
16V
R736
1K
1%
D1_2
7
DH1
8
DH2
6
D2_1
C729
2200pF
50V
6
R722
27K
3
1
S1
14
VLCD_POWER
(+12V)
5
R734
9.1K
24
10uF
25V
Vout = 0.6*(1+R1/R2)
4
C733
22uF
16V
C735
22uF
16V
C737
22uF
16V
C738
0.1uF
50V
R742
5.1K
R735
510
R729
0 OPT
R737
36K
TCON_POWER_EN
001:AJ20;006:P14
C732
820pF
50V
Vout = 0.6*(1+R1/R2)
R2
COMP1
C720
G1
13
23
C706
820pF
50V
S2
PGND2
R718
0 OPT
LIM1
R706
30K
1%
9
S1
22
1
BST2
8
LIM2
R704
510
D1_2
10
1K
1%
21
R713
2.2
R745
4.7
G1
IN
R705
2
LX2
5.1K
C703
22uF
16V
7
C724
0.22uF
16V
R746
4.7
C722
0.22uF
16V
S2
12
R700
C701
22uF
16V
C700
0.1uF
50V
D1_1
3
11
R1
6
G2
SGND
D2_2
G2
19
L700
10uH
3.1A
4
RT
+3.3V_TCON
5
20
D2_1
C734
0.1uF
50V
R738
18K
1%
C727
2200pF
50V
R725
16K
R731
10K
C728
47pF
50V
C723 R723
1uF 11K
50V
VLCD_POWER
(+12V)
C709
0.1uF
50V
C712
22uF
25V
C714
22uF
25V
Q701
SI4804BDY
R721
10
HVDD
(+8V)
D2_1
L701
10uH
3.1A
R1
D2_2
D1_1
R703
5.1K
C702
0.1uF
50V
C705
22uF
16V
C707
22uF
16V
R710
6.8K
1%
R708
510
R715
2.2
D1_2
5
4
6
3
7
2
8
1
R701
22K
S2
G1
S1
IN
VCC
PGOOD
007:Z8 DPM_HVDD
R720
0
OPT
R726
11K
R712
IC701
MAX15026BETD+
R2
C718
47pF
50V
10K
1%
Vout = 0.592*(1+R1/R2)
R717
10K
EN
1
14
2
13
3
12
4
11
5
10
6
9
7
8
DH
C725
0.22uF
16V
LX
BST
R747
4.7
DL
R748
LIM
COMP
C719
2200pF
50V
007:O6
004:AN15;006:D12;006:Q5
C731
1uF
C726
1uF
50V
C710
820pF
50V
DPM_HVDD
DPM
VLCD_POWER
(+12V)
C721
10uF
25V
C715
2200pF
50V
R711
120K
1%
D700
OPT
G2
FB
2.2
DRV
GND
C740
2.2uF
25V
RT
R724
27K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3D + 240 FRC + TCON BOARD
Power Block (TCON)
2009. 11. 13
7
10
LGE Internal Use Only
VDD_LCM
(+16V)
[RIGHT FFC CONNECTOR]
L800
120-ohm
P805
104060-8017
P802
FI-R51S-HF
P806
104060-8017
C801
0.1uF
50V
VCOM2
V1
008:AE21;008:AL17
R805
OUT1
0
1
28
2
27
C802
0.1uF
50V
C803
10uF
25V
C804
10uF
25V
C807
10uF
25V
C808
10uF
25V
For Shutter Glasses Sync
1
2
VCOM1
OUT16
R801
0
R810
P_VCOM 006:H14
008:AE21;008:AL17
R822
V2
008:AE21;008:AL17
R823
V3
008:AE21;008:AL17
0
R824
V4
OUT3
0
OUT4
0
3
26
4
25
5
24
OUT15
V18
008:AE18;008:AL14
R821
OUT14
R828
0
R829
V17
0
V16
33
7
008:AE18;008:AL14
8
R813
0
9
R802
0
10
R803
0
OPT
008:AE19;008:AL15
GNDA_2
008:AE20;008:AL16
R825
V5
008:AE20;008:AL16
0
R826
V6
OUT6
0
GNDA_1
VCC_LCM
(+3.3V)
008:AE20;008:AL16
R827
V7
008:AE20;008:AL16
V9
23
7
22
8
21
OUT13
OUT12
0
R831
V15
008:AE19;008:AL15
V14
VS_1
OUT7
OUT8
0
9
20
10
19
11
18
OUT11
OUT10
R832
0
V13
0
V12
R807
V10
OUT9
0
12
17
R834
0
GAMMA_BKSEL
R808
I2C_SCL
SCL
33
13
16
14
15
AO
SDA
005:T17
18
VCOMROUT
006:H18
19
LRMV0P
005:T18
20
LRMV0N
005:T18
Z_OUT
008:AL14
21
LRMV1P
LVRX1_CM 001:E34
V1
008:F24;008:AL17
24
V2
008:F24;008:AL17
LVRX1_CP 001:E34
25
V3
008:F23;008:AL17
26
V4
008:F23;008:AL17
27
V5
008:F22;008:AL16
28
V6
008:F22;008:AL16
29
V7
008:F20;008:AL16
30
V9
008:F20;008:AL16
31
V10
008:F19;008:AL16
32
V12
008:N20;008:AL15
33
V13
37
V17
008:N24;008:AL14
38
V18
008:N24;008:AL14
5
GSP
004:AD15;008:AL18
POL
004:AI17;008:AL18
29
LVRX2_AP
001:AG35
43
005:T19
LRMV2P
005:T19
24
LRMV2N
005:T19
26
LRMVCLKP
005:T20
27
LRMVCLKN
005:T20
29
LRMV4P
005:T21
30
LRMV4N
31
LRMV5P
005:T21
32
LRMV5N
005:T21
33
LRMV6P
005:T22
34
LRMV6N
005:T22
005:T21
35
008:N23;008:AL15
41
42
36
OPT_N
37
H_CONV
38
GSP
39
POL
004:R10;008:AE17
004:O10;008:AE17
004:AD15;008:AE18
004:AI17;008:AE18
40
41
SOE_L
004:AD13
42
SOE_R
43
004:AI13
008:F24;008:AE21
V1
44
H_CONV
004:O10;008:AL18
44
OPT_N
004:R10;008:AL19
45
V3
008:F23;008:AE21
46
V4
008:F23;008:AE21
V5
008:F22;008:AE20
008:F24;008:AE21
V2
30
LVRX2_BM
001:AG34
45
31
LVRX2_BP
001:AG34
46
32
47
LVRX2_CM
RLMV0P
004:V14
47
001:AG34
48
RLMV0N
004:V14
48
33
LVRX2_CP
001:AG34
49
RLMV1P
004:V15
49
V7
008:F20;008:AE20
50
RLMV1N
004:V15
50
V9
008:F20;008:AE20
51
RLMV2P
004:V15
51
V10
004:V16
52
V12
008:N20;008:AE19
53
V13
008:N21;008:AE19
52
LVRX2_CLKM001:AG35
RLMV2N
53
LVRX2_CLKP001:AG35
008:F22;008:AE20
V6
008:F19;008:AE20
54
RLMVCLKP
004:V16
54
V14
008:N21;008:AE19
55
RLMVCLKN
004:V17
55
V15
008:N22;008:AE19
56
V16
008:N23;008:AE19
56
38
LVRX2_DM
001:AG33
57
RLMV4P
004:V17
57
V17
008:N24;008:AE18
39
LVRX2_DP
001:AG34
58
RLMV4N
004:V17
58
V18
008:N24;008:AE18
40
001:AG33
004:V17
59
LVRX2_EM
60
RLMV5N
004:V18
60
41
LVRX2_EP
001:AG33
61
RLMV6P
004:V18
61
62
RLMV6N
004:V18
62
59
RLMV5P
63
64
43
44
45
46
P804
48
50
L801
51
VLCD_POWER
120-ohm
52
C805
10uF
25V
C806
10uF
25V
006:D13
VCOMLFB
006:H16
004:V19
64
RRMV0N
004:V19
65
RRMV1P
004:V19
66
67
RRMV1N
004:V20
67
68
RRMV2P
004:V20
68
GSC 004:AN17;008:AE23
69
RRMV2N
004:V20
69
GOE 004:AC17;008:AE23
70
71
RRMVCLKP
004:V21
71
72
72
RRMVCLKN
004:V21
74
RRMV4P
004:V21
74
75
RRMV4N
004:V22
75
76
RRMV5P
004:V22
76
77
RRMV5N
73
49
008:AE22
VCOMLOUT
66
RRMV0P
Z_OUT
63
65
70
47
1
V16
40
001:AG35
42
12507WR-06L
008:N22;008:AL15
LVRX2_AM
37
4
008:N21;008:AL15
V15
28
120-ohm
3
V14
35
LRMV1N
23
28
39
27
2
34
005:T19
22
25
008:N21;008:AL15
LVRX1_EP 001:E33
36
E_TDI
005:T17
LLMV6N
006:H17
VCOMRFB
23
26
VLCD_POWER
5
005:T17
LLMV6P
17
25
L802
E_TMS
LLMV5N
16
17
36
35
4
15
16
LVRX1_BP 001:E34
34
E_TDO
005:T17
15
LVRX1_EM 001:E33
P803
3
005:T16
005:T16
LLMV5P
22
12507WR-04L
E_TCK
LLMV4P
21
I2C_SDA
005:T16
LLMV4N
VGH
004:AC17;008:AL12
(+24V)
004:AN17;008:AL12
LVRX1_DP 001:E34
33
LLMVCLKN
14
GSC
20
LVRX1_DM 001:E33
005:T16
10
13
GOE
14
LVRX1_BM 001:E34
LVRX1_CLKP001:E35
LLMVCLKP
12
13
14
LVRX1_CLKM001:E35
9
11
24
R811
8
004:R10
OPT_P
23
C825
OPT
2
005:T15
1K
1%
001:E19;005:AA15;008:V25;008:AL4;009:AP11
1
LLMV2N
R835
001:E19;005:AA16;008:V24;008:AL4;009:AP8
C824
OPT
7
VGL
(-5V)
12
OPT
VSD
005:T15
LVRX1_AP 001:E35
22
001:AD16
005:T14
LLMV2P
19
20
BKSEL
LLMV1N
6
HVDD
(+8V)
10
21
008:AE20;008:AL16
005:T14
5
18
19
GNDD
005:T14
LLMV1P
LVRX1_AM 001:E35
17
008:AE19;008:AL15
005:T14
LLMV0N
4
9
18
R833
LLMV0P
3
4
13
008:AE19;008:AL15
008:AE19;008:AL15
2
3
8
L/R_SYNC
15
0
1
2
7
3D_DIMMING
010:AY5
3D_DIMMING_2
010:BE5
12
R830
C817
0.01uF
50V
11
16
0
R806
6
VS_2
C816
0.1uF
50V
6
11
OUT5
C810
10uF
25V
1
5
0
I2C_SDA
001:E19;005:AA15;008:N18;008:AL4;009:AP11
I2C_SCL
001:E19;005:AA16;008:F18;008:AL4;009:AP8
FRC_RESET
001:I17
4
5
0
FPGA_VSYNC
010:AX10
R812 OPT
VSYNC
001:AD17
6
OUT2
3D_SYNC_OUT
009:AK20
3
R809
R804
0
0
C815
10uF
25V
C814
0.1uF
50V
For LED Sync from 3D Formatter
IC801
BUF16821AIPWPR
[LEFT FFC CONNECTOR]
VCC_LCM
(+3.3V)
VDD_LCM
(+16V)
VGH
(+24V)
VGL
(-5V)
HVDD
(+8V)
73
004:V22
77
78
RRMV6P
004:V22
78
79
RRMV6N
004:V23
79
80
VCC_LCM
(+3.3V)
C818
0.1uF
50V
80
81
C820
0.01uF
50V
81
VDD_LCM
(+16V)
6
C819
0.1uF
50V
7
C821
10uF
25V
C809
10uF
25V
For P-Gamma Data Download
P807
+3.3V
2V5
+3.3V
2V5
2V5
+3.3V
+3.3V
12505WR-04A00
2V5
VDD_LCM
(+16V)
OPT
1
FDV301N
Q801
OPT
E_TMS
R839
0
OPT
R843
TMS
22
OPTC813
18pF
50V
FDV301N
Q803
1
E_TDI
4.7K
R847
2K
R846
R844
0
TDI_FLASH
3
I2C_SCL
OPT
4
R848
S
TDO
22
OPTC812
18pF
50V
R852
22
G
5.6K
R845
OPT
4.7K
R842
2K
R841
TMS_FLASH
D
R838
FDV301N
Q802
S
R819
0
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
E_TDO
R851
22
G
5.6K
R840
OPT
4.7K
R837
2K
R836
TDO_FLASH
D
TCK
22
OPTC811
18pF
50V
S
R818
S
0
D
R814
D
E_TCK
R850
22
G
5.6K
R820
OPT
4.7K
R817
TCK_FLASH
G
2K
R816
5.6K
R815
OPT
2
R849
22
FDV301N
Q804
I2C_SDA
TDI
22
OPTC822
18pF
50V
5
OPT
OPT
ZD800
5.5V
TVS
OPT
ZD801
5.5V
TVS
3D + 240 FRC + TCON BOARD
Interface
2009. 11. 13
8
10
LGE Internal Use Only
2V5
1V2
L902
BLM18PG121SN1D
C907
0.1uF
16V
C905
0.1uF
16V
C903
0.1uF
16V
R949
22
R991
EJTAG_TO_FLASH
SYSCLK
IC904
EPCS16SI8N_
R945
0
TMS_FLASH
IC1000
EP3C55F484C6N
IC1000
EP3C55F484C6N
1V2
R964
22
NCS
R965
27
DATA
R916
LVTX6_E+
100
LVTX5_AR903
LVTX5_A+
100
LVTX5_BR904
LVTX5_B+
100
LVTX5_CR905
LVTX5_C+
100
LVTX5_ELVTX5_E+
R907
100
R909
100
LVTX6_ALVTX6_A+
LVTX7_ALVTX7_A+
R912
100
R915
100
LVTX6_DLVTX6_D+
LVTX7_BR914
LVTX7_B+
100
LVTX7_C+
R934
100
R908
100
LVTX6_BLVTX6_B+
LVTX8_AR932
LVTX8_A+
100
LVTX6_CR911
LVTX6_C+
100
LVTX7_DR936
LVTX7_D+
100
LVTX7_ER935
LVTX7_E+
100
LVTX8_CR910
LVTX8_C+
100
CLK2
T1
CLK3
L6
B2_IO[0]
TC1-
M6
B2_IO[1]
TCLK1+
M2
B2_IO[2]
B1_IO[1]
TCLK1-
M1
B2_IO[3]
B1_IO[2]
TD1+
M4
B2_IO[4]
B1
B1_IO[3]
TD1-
M3
B2_IO[5]
G5
B1_IO[4]
TE4+
N2
B2_IO[6]
E4
B1_IO[5]
TE4-
N1
B2_IO[7]
E3
B1_IO[6]
M5
B2_IO[8]
C2
B1_IO[7]
TD4+
P2
B2_IO[9]
C1
B1_IO[8]
TD4-
P1
B2_IO[10]
D2
B1_IO[9]
TB4+
R2
B2_IO[11]
D1
B1_IO[10]
TB4-
R1
B2_IO[12]
H7
B1_IO[11]
N5
B2_IO[13]
TA2+
H6
B1_IO[12]
TB1+
P4
B2_IO[14]
B1_IO[13]
TB1-
P3
B2_IO[15]
B8_IO[0]
F6
VCCD_PLL3
B11
B8_IO[1]
F5
GNDA3
D10
B8_IO[2]
G6
VCCA3
E10
B8_IO[3]
A10
B8_IO[4]
TD2+
G4
B1_IO[0]
B10
B8_IO[5]
TD2-
G3
A9
B8_IO[6]
B2
LVTX8_D+
B9
B8_IO[7]
C10
B8_IO[8]
G11
B8_IO[9]
LVTX8_B+
A8
B8_IO[10]
LVTX8_B-
B8
B8_IO[11]
LVTX8_E+
A7
B8_IO[12]
LVTX8_E-
B7
B8_IO[13]
A6
B8_IO[14]
B6
B8_IO[15]
E9
B8_IO[16]
LVTX8_D-
R913
100
R902
100
R917
100
ASDO
TC1+
B8_IO[17]
TA2-
J6
C7
B8_IO[18]
TB2+
H4
B1_IO[14]
TE3+
U2
B2_IO[16]
D8
B8_IO[19]
TB2-
H3
B1_IO[15]
TE3-
U1
B2_IO[17]
E8
B8_IO[20]
/CSO
E2
B1_IO[16]
TD3+
V2
B2_IO[18]
E1
B1_IO[17]
TD3-
V1
B2_IO[19]
A5
B8_IO[21]
B5
B8_IO[22]
TE2+
F2
B1_IO[18]
TA1+
P5
B2_IO[20]
G10
B8_IO[23]
TE2-
F1
B1_IO[19]
TA1-
N6
B2_IO[21]
F10
B8_IO[24]
J5
B1_IO[20]
TA4+
R4
B2_IO[22]
B1_IO[21]
TA4-
R3
B2_IO[24]
B8_IO[25]
H5
D7
B8_IO[26]
/STATUS
K6
nSTATUS
TCLK3+
W2
A4
B8_IO[27]
TE1+
J7
B1_IO[22]
TCLK3-
W1
B2_IO[25]
B4
B8_IO[28]
TE1-
K7
B1_IO[23]
TB3+
Y2
B2_IO[26]
B2_IO[27]
B2_IO[28]
B2_IO[29]
TC3-
P7
B2_IO[30]
B1_IO[28]
TA3+
AA2
B2_IO[31]
J1
B1_IO[29]
TA3-
AA1
B2_IO[32]
DCLK
K2
DCLK
V4
B2_IO[33]
B8_IO[36]
DATA0
K1
B1_IO[30]
V3
B2_IO[34]
F7
B8_IO[38]
/CONFIG
K5
nCONFIG
TCLK4+
P6
B2_IO[35]
G7
B8_IO[39]
TDI
L5
TDI
TCLK4-
R5
B2_IO[36]
F9
B8_IO[40]
TCK
L2
TCK
T4
B2_IO[37]
E6
B8_IO[41]
TMS
L1
TMS
TC4+
T5
B2_IO[38]
TDO
L4
TDO
TC4-
R6
B2_IO[39]
L3
nCE
T6
VCCA1
G2
CLK0
U5
GNDA1
G1
CLK1
U6
VCCD_PLL1
B1_IO[24]
TCLK2+
H2
B1_IO[25]
B8_IO[31]
TCLK2-
H1
B1_IO[26]
TC3+
B3
B8_IO[32]
J3
B1_IO[27]
D6
B8_IO[33]
TC2+
J2
E7
B8_IO[34]
TC2-
C3
B8_IO[35]
C4
E5
B8_IO[42]
G9
B8_IO[43]
/CE
LVTX8_CLK+
LVTX8_CLK-
R937
100
TB3-
1V2
2V5
3
6
4
5
DCLK
EJTAG_TO_FLASH
GND
R968
22
ASDI
7
ASDO
R956
0
C921
10pF
8
TDO_FLASH
R994
22
9
R951
10K
/STATUS
TMS
0.1uF
6
R950
10K
CONFIG_DONE
R997
22
C924
5
R947
0
R967
22
DCLK
TDI
10
R952
10K
/CONFIG
11
R953
1K
/CE
OPT
+3.3V
FPGA Reset Level Shifter (3.3V to 2.5V)
OPT
SW901
JTP-1127WEM
1
2
3
4
IC901
I
1
OPT
3
OPT
R959
0
O
/3D_FPGA_RESET
2
OPT
C911
0.1uF
16V
2V5
+3.3V
KIA7029AF
OPT
R948
330
OPT
C914
0.1uF
16V
G
R1907
R1909
10K
4.7K
R1910
22
R963
0
/RESET2V5
C
R1908
B
Q902
2SC3052
10K
/FPGA_RESET
E
C
R1906
B
Q901
2SC3052
10K
E
N7
J4
B8_IO[30]
A3
VCC_1
/3D_FPGA_RESET
T3
B8_IO[29]
G8
VCC
TDI_FLASH
B2_IO[23]
Y1
F8
7
TDO
16V
EJTAG_TO_FLASH
C8
C6
LVTX7_C-
T2
A11
2
VCC_2
OPT
R958
4.7K
100
LVTX6_E-
8
R996
22
OPT
4
TCK_FLASH
R946
0
OPT
R954
1K
R901
LVTX5_CLK+
1
1K
3
EJTAG_TO_FLASH
DATA0
2V5
LVTX5_CLK-
TCK
2V5
2
/CSO
2V5
R995
22
1
X901
54.0000MHz
TRISTATE/OPEN
VDD
1
4
GND
OUTPUT
2
3
C909
0.1uF
16V
IC1000
EP3C55F484C6N
C920
100pF
50V
C919
0.1uF
16V
R944
10K
C901
0.1uF
16V
P901
12505WR-10
C917
10uF
16V
R993
1K
2V5
1V2
R992
1K
2V5
2V5
FPGA DOWNLOAD CONTROL
IR Emitter Vsync Level Shift (2.5V to 3.3V)
2V5
R2237
4.7K
R2238
22
/CE
+3.3V
+3.3V
C
R2236
FPGA_D/L_CTRL
LVTX6_CLK-
E
100
R1904
100
3.3K
LVTX6_CLK+
2V5
1V2
R955
0
OPT
LVTX3_CLKC906
0.1uF
16V
C908
0.1uF
16V
B5_IO[1]
B5_IO[2]
B7_IO[5]
MSEL[2]
MSEL2
T17
C18
B7_IO[6]
MSEL[3]
K20
MSEL3
T18
B5_IO[3]
D18
B7_IO[7]
TB6-
L22
B6_IO[0]
W20
B5_IO[4]
D17
B7_IO[8]
TB6+
L21
B6_IO[1]
W19
B5_IO[5]
C19
B7_IO[9]
K19
B6_IO[2]
TD8-
Y22
B5_IO[6]
D19
B7_IO[10]
TA6-
K22
B6_IO[3]
TD8+
Y21
B5_IO[7]
A20
B7_IO[11]
TA6+
K21
B6_IO[4]
TE7-
U20
B5_IO[8]
B20
B7_IO[12]
TE5-
J22
B6_IO[5]
TE7+
U19
B5_IO[9]
C17
B7_IO[13]
TE5+
J21
B6_IO[6]
TCLK8-
W22
B5_IO[10]
SDA2V5
B19
B7_IO[14]
TCLK5-
H22
B6_IO[7]
TCLK8+
W21
B5_IO[11]
SCL2V5
A19
B7_IO[15]
TCLK5+
H21
B6_IO[8]
TA8-
T20
B5_IO[12]
A18
B7_IO[16]
TD5-
K17
B6_IO[9]
TA8+
T19
B5_IO[13]
B18
B7_IO[17]
TD5+
K18
B6_IO[10]
TD7-
R17
B5_IO[14]
J18
B6_IO[11]
TD7+
P17
B5_IO[15]
F22
B6_IO[12]
TC8-
V22
B5_IO[16]
F21
B6_IO[13]
TC8+
V21
B5_IO[17]
LVTX3_DLVTX3_D+
R918
100
LVTX3_BLVTX3_B+
R920
100
LVTX4_ELVTX4_E+
R929
100
R924
100
R927
100
LVTX3_ELVTX3_E+
LVTX4_ALVTX4_A+
LVTX4_BLVTX4_B+
R928
100
R919
100
LVTX3_CLVTX3_C+
LVTX4_CLVTX4_C+
R930
100
LVTX4_DLVTX4_D+
R931
100
LVTX5_DLVTX5_D+
R906
100
R933
100
LVTX4_CLKLVTX4_CLK+
D15
B7_IO[18]
E15
B7_IO[19]
LVTX1_A-
G14
B7_IO[20]
LVTX1_A+
G13
B7_IO[21]
TC5-
J20
B6_IO[14]
A17
B7_IO[22]
TC5+
J19
B6_IO[15]
B17
B7_IO[23]
A16
B7_IO[24]
B16
B7_IO[25]
C15
B7_IO[26]
R938
100
B5_IO[18]
U22
B5_IO[19]
B6_IO[16]
TB8+
U21
B5_IO[20]
H20
B6_IO[17]
TCLK7-
R18
B5_IO[21]
H19
B6_IO[18]
TCLK7+
R19
B5_IO[22]
E22
B6_IO[19]
N16
B5_IO[23]
E21
B5_IO[24]
TB5+
R939
100
B7_IO[27]
B6_IO[20]
TC7-
R22
F13
B7_IO[28]
H18
B6_IO[21]
TC7+
R21
B5_IO[25]
A15
B7_IO[29]
H16
B6_IO[22]
P20
B5_IO[26]
B15
B7_IO[30]
LVTX1_C-
D22
B6_IO[23]
TB7-
P22
B5_IO[27]
C13
B7_IO[31]
LVTX1_C+
D21
B6_IO[24]
TB7+
P21
B5_IO[28]
R940
100
D13
B7_IO[32]
TA5-
F20
B6_IO[25]
TD6-
N20
B5_IO[29]
E13
B7_IO[33]
TA5+
F19
B6_IO[26]
TD6+
N19
B5_IO[30]
A14
B7_IO[34]
B14
G18
B6_IO[27]
TE6-
N17
B5_IO[31]
B7_IO[35]
H17
B6_IO[28]
TE6+
N18
B5_IO[32]
A13
B7_IO[36]
LVTX1_D-
C22
B6_IO[29]
TA7-
N22
B5_IO[33]
B13
B7_IO[37]
LVTX1_D+
C21
B6_IO[30]
TA7+
N21
B5_IO[34]
E12
B7_IO[38]
LVTX1_E-
B22
B6_IO[31]
TC6-
M22
B5_IO[35]
E11
B7_IO[39]
LVTX1_E+
B21
B6_IO[32]
TC6+
M21
B5_IO[36]
F11
B7_IO[40]
C20
B6_IO[33]
TCLK6-
M20
B5_IO[37]
A12
CLK8
D20
B6_IO[34]
TCLK6+
M19
B5_IO[38]
B12
CLK9
F17
B6_IO[35]
M16
B5_IO[39]
G17
B6_IO[36]
T22
CLK7
F18
VCCA2
T21
CLK6
E18
GNDA2
E17
VCCD_PLL2
R941
100
R942
100
R922
100
LVTX2_B1V2
2V5
LVTX2_B+
VS_STATUS2V5
AR901
MSEL[3]
MSEL[2]
MSEL[1]
MSEL[0]
1/16W
22
FPGA I2C Level Shift (3.3V <-> 2.5V)
2V5
+3.3V
SMD Gasket - 4.5T (8x6)
GAS2
GAS1
GAS1_4.5T(8x6)
R1915
R1911
22
OPT
C910
18pF
50V
GAS5
GAS6
MDS62110208
R1927
0
GAS5_4.5T(8x6)
2V5
GAS7
MDS62110208
MDS62110208
GAS6_4.5T(8x6)
GAS7_4.5T(8x6)
GAS10
GAS9
+3.3V
MDS62110208
GAS9_4.5T(8x6)
GAS8
MDS62110208
GAS8_4.5T(8x6)
GAS1-*1
22
OPT
C913
18pF
50V
FDV301N
Q904
MDS62110208
GAS11_4.5T(8x6)
GAS2-*1
MDS62110201
SCL2V5
GAS11
MDS62110208
GAS10_4.5T(8x6)
GAS12
MDS62110208
GAS12_4.5T(8x6)
SMD Gasket - 4.5T (8x5)
R1920
R1916
I2C_SCL
GAS1_4.5T(8x5)
MDS62110201
GAS2_4.5T(8x5)
GAS3-*1
MDS62110201
GAS3_4.5T(8x5)
GAS4-*1
MDS62110201
GAS4_4.5T(8x5)
0
R1926
0
OPT
GAS5-*1
FPGA_SCL
GAS6-*1
MDS62110201
GAS5_4.5T(8x5)
GAS9-*1
MDS62110201
GAS6_4.5T(8x5)
GAS10-*1
MDS62110201
GAS9_4.5T(8x5)
MDS62110201
GAS10_4.5T(8x5)
GAS7-*1
MDS62110201
GAS7_4.5T(8x5)
GAS11-*1
MDS62110201
GAS11_4.5T(8x5)
GAS8-*1
MDS62110201
GAS8_4.5T(8x5)
GAS12-*1
MDS62110201
GAS12_4.5T(8x5)
SMD Gasket - 5.5T (8x6)
GAS1-*2
GAS2-*2
MDS62110204
GAS1_5.5T(8x6)
MDS62110204
GAS2_5.5T(8x6)
GAS6-*2
GAS5-*2
MDS62110204
GAS9-*2
MDS62110204
GAS6_5.5T(8x6)
GAS10-*2
MDS62110204
GAS9_5.5T(8x6)
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GAS4
MDS62110208
GAS4_4.5T(8x6)
FPGA_SDA
GAS5_5.5T(8x6)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
MDS62110208
GAS3_4.5T(8x6)
I2C_SDA
0
FDV301N
Q903
GAS3
MDS62110208
GAS2_4.5T(8x6)
OPT
E14
LVTX1_B+
OPT
22
FDV301N
Q905
SDA2V5
R20
TB5-
LVTX1_B-
R1925
22 OPT
MDS62110208
TB8-
J17
R1921
G
VS_STATUS2V5
2K
R1923
B5_IO[0]
AA21
5.6K
R1922
AA22
TE8+
G
TE8-
MSEL1
L17
D
MSEL0
L18
R988
0
OPT
100
M17
MSEL[1]
2V5
R986
4.7K
R921
MSEL[0]
F14
R1914
5.6K
LVTX2_C+
VCCA4
OPT
LVTX2_C-
GNDA4
U18
OPT
100
VCCD_PLL4
V18
CONF_DONE
D
R923
B7_IO[4]
V17
CLK4
M18
R1919
5.6K
LVTX2_D+
B7_IO[3]
G15
CLK5
G21
SYSCLK
D
LVTX3_A+
LVTX2_D-
G16
G22
/RESET2V5
CONFIG_DONE
R1913
2K
100
B7_IO[2]
G
100
R925
B7_IO[1]
F15
S
R943
LVTX3_A-
B7_IO[0]
E16
R1918
2K
LVTX2_A+
F16
S
100
R1912
2K
R926
LVTX2_A-
2V5
IC1000
EP3C55F484C6N
1V2
R1917
2K
LVTX2_E+
2V5
VS_STATUS2V5
10K
E
+3.3V
IC1000
EP3C55F484C6N
IC1000
EP3C55F484C6N
B
Q907
2SC3052
3D_SYNC_OUT
R1932
R989
1K
C904
0.1uF
16V
C902
0.1uF
16V
/CONFIG
C
R984
0
OPT
100
LVTX3_CLK+
R1930
10K
E
C915
18pF
50V
R987
0
OPT
1V2
2V5
B
Q906
2SC3052
100
R982
0
OPT
R1905
LVTX2_E-
R2239
0
R1931
R985
1K
100
LVTX7_CLK+
R1903
10K
C
LVTX7_CLKR1902
LVTX2_CLK+
R1929
R1928
22
R983
1K
LVTX2_CLK-
Q908
2SC3052
4.7K OPT
R1924
R1901
LVTX1_CLK+
S
LVTX1_CLK-
B
10K
MDS62110204
GAS10_5.5T(8x6)
GAS3-*2
MDS62110204
GAS3_5.5T(8x6)
GAS7-*2
MDS62110204
GAS7_5.5T(8x6)
GAS11-*2
MDS62110204
GAS11_5.5T(8x6)
GAS4-*2
MDS62110204
GAS4_5.5T(8x6)
GAS8-*2
MDS62110204
GAS8_5.5T(8x6)
GAS12-*2
MDS62110204
GAS12_5.5T(8x6)
3D + 240 FRC + TCON BOARD
EP3C55_C6N (FPGA IC)
2009. 11. 13
9
10
LGE Internal Use Only
DDR_VREF1
DDR_VREF0
C1004
0.1uF
16V
IC1002
H5PS5162FFR-S6C
C1031
470pF
50V
C1028
0.1uF
16V
IC1001
H5PS5162FFR-S6C
C1006
470pF
50V
1V2
SDDR_DQ[15-0]
M3
DDR_A[12-0]
DDR_A[2]
A2
DDR_A[3]
M7
A3
DDR_A[4]
N2
A4
DDR_A[5]
N8
A5
DDR_A[6]
N3
A6
N7
A7
P2
DDR_A[7]
DDR_A[8]
A8
DDR_A[9]
P8
A9
P3
A10/AP
M2
A11
P7
A12
R2
DDR_A[10]
DDR_A[11]
DDR_A[12]
DDR_BA[0]
BA0
L2
DDR_BA[1]
BA1
L3
R1001
100
DDR2_CLK
/DDR2_CLK
M8
DDR_DQ[1]
DDR_DQ[5]
DQ2
DDR_DQ[2]
DDR_DQ[2]
SDDR_DQ[2]
DDR_A[0]
H3
DQ3
DDR_DQ[3]
DDR_DQ[0]
SDDR_DQ[0]
DDR_A[1]
H1
DQ4
DDR_DQ[4]
DDR_DQ[7]
SDDR_DQ[7]
DDR_A[2]
A2
DQ5
DDR_DQ[5]
DDR_A[3]
M7
H9
A3
N2
F1
DQ6
DDR_DQ[6]
F9
DQ7
DDR_DQ[7]
C8
DQ8
DDR_DQ[8]
C2
DQ9
DDR_DQ[9]
D7
DQ10
DDR_DQ[10]
D3
DQ11
DDR_DQ[11]
D1
DQ12
DDR_DQ[12]
DDR_DQ[9]
D9
DQ13
DDR_DQ[13]
DDR_DQ[12]
B1
DQ14
DDR_DQ[14]
DDR_DQ[11]
B9
DQ15
DDR_DQ[15]
AR1001
33
AR1002
DDR_DQ[13]
DDR_DQ[10]
A1
VDD5
E1
VDD4
J8
J9
VDD3
K8
M9
VDD2
K2
R1
VDD1
SDDR_DQ[5]
SDDR_DQ[13]
SDDR_DQ[10]
DDR_DQ[8]
SDDR_DQ[8]
DDR_DQ[15]
SDDR_DQ[15]
33
A1
DDR_A[4]
A4
AR1003
DDR_DQ[14]
1V8
33
AR1004
DDR_DQ[6]
DDR_DQ[4]
A5
N3
A6
N7
DDR_A[7]
A7
DDR_A[9]
A8
P8
P3
A10/AP
SDDR_DQ[12]
DDR_A[11]
A11
SDDR_DQ[11]
DDR_A[12]
A12
SDDR_DQ[3]
L2
DDR_BA[1]
BA1
L3
DDR2_CLK
C1019
100pF
50V
/DDR2_CLK
ODT
K9
CS
L8
/DDR_CAS
CAS
L7
C3
VDDQ8
/DDR_CAS
CAS
WE
C7
VDDQ7
/DDR_WE
WE
K3
C9
VDDQ6
E9
VDDQ5
DDR_LDQS[1]
G1
VDDQ4
DDR_UDQS[1]
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
UDM
R1007 33
B3
LDQS
E8
A3
VSS5
UDQS
A8
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
R1005 1K
NC4
L1
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
VSSDL
VDDL
J7
J1
DDR_DQ[22]
F9
DQ7
DDR_DQ[23]
C8
DQ8
DDR_DQ[24]
C2
DQ9
DDR_DQ[25]
D7
DQ10
DDR_DQ[26]
D3
DQ11
DDR_DQ[27]
DDR_DQ[25]
SDDR_DQ[25]
D1
DQ12
DDR_DQ[28]
DDR_DQ[28]
D9
DQ13
DDR_DQ[29]
DDR_DQ[27]
B1
DQ14
DDR_DQ[30]
B9
DQ15
DDR_DQ[31]
A1
VDD5
E1
VDD4
DDR_DQ[21]
IC1000
EP3C55F484C6N
2V5
C1
VDDQ9
L7
C3
VDDQ8
K3
C7
VDDQ7
C9
VDDQ6
E9
VDDQ5
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
LDQS
F7
UDQS
B7
DDR_LDM[1]
LDM
F3
DDR_UDM[1]
UDM
B3
LDQS
E8
A3
VSS5
UDQS
A8
E3
VSS4
J3
VSS3
NC4
N1
VSS2
L1
NC5
R3
NC6
R7
R1010 1K
P9
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
VSSQ4
F2
VSSQ4
VSSQ3
F8
VSSQ3
F8
VSSQ2
H2
VSSQ2
H2
VSSQ1
H8
VSSQ1
H8
B2
NC1
A2
B8
VSSQ9
NC2
E2
A7
VSSQ8
NC3
D2
VSSQ7
D8
VSSQ6
E7
VSSQ5
F2
VSSDL
VDDL
R8
J7
J1
AR1006
C1050
0.1uF
16V
C1053
100pF
50V
J11
VCCINT[0]
VCCIO1[0]
D4
J12
VCCINT[1]
VCCIO1[1]
F4
L14
VCCINT[2]
VCCIO1[2]
K4
M14
VCCINT[3]
SDDR_DQ[29]
C1068
0.1uF
16V
C1066
100pF
50V
C1070
10uF
16V
L10
GND[0]
GND[42]
C12
L11
GND[1]
GND[43]
C14
M10
GND[2]
GND[44]
C16
M11
GND[3]
GND[45]
A22
SDDR_DQ[26]
P11
VCCINT[4]
VCCIO2[0]
N4
L12
GND[4]
GND[46]
E20
DDR_DQ[24]
SDDR_DQ[24]
P12
VCCINT[5]
VCCIO2[1]
U4
L13
GND[5]
GND[47]
G20
L9
VCCINT[6]
VCCIO2[2]
W4
M12
GND[6]
GND[48]
L20
M9
VCCINT[7]
M13
GND[7]
GND[49]
P19
SDDR_DQ[28]
J13
VCCINT[8]
VCCIO3[0]
AB2
N11
GND[8]
GND[50]
V20
SDDR_DQ[27]
J14
VCCINT[9]
VCCIO3[1]
W5
K11
GND[9]
GND[51]
Y20
VCCINT[10]
VCCIO3[2]
W9
N12
GND[10]
GND[52]
AB22
VCCINT[11]
VCCIO3[3]
W11
K12
GND[11]
GND[53]
Y18
K13
GND[12]
GND[54]
Y16
N13
GND[13]
GND[55]
Y12
N10
GND[14]
GND[56]
Y11
K10
GND[15]
GND[57]
Y9
J9
GND[16]
GND[58]
Y5
SDDR_DQ[31]
33
AR1007
DDR_DQ[30]
SDDR_DQ[30]
33
SDDR_DQ[22]
K14
DDR_DQ[17]
SDDR_DQ[17]
J10
DDR_DQ[19]
SDDR_DQ[19]
AR1008
DDR_DQ[22]
DDR_DQ[20]
SDDR_DQ[20]
33
VSS1
B2
VSSQ10
C1047
10uF
16V
C1042
100pF
50V
VDDQ10
K7
SDDR_DQ[18]
SDDR_DQ[16]
SDDR_DQ[23]
DDR_DQ[26]
DDR_DQ[31]
1V8
SDDR_DQ[21]
33
DDR_DQ[29]
1V8
A9
R1008 33
R1009 1K
R1004 1K
DDR_DQ[21]
DQ6
VDD1
/DDR_RAS
DDR_UDM[0]
DQ5
F1
VDD2
VDDQ9
F3
H9
R1
C1
LDM
DDR_DQ[20]
M9
K7
R1003 33
DQ4
K2
RAS
DDR_LDM[0]
H1
K8
/DDR_RAS
B7
DDR_DQ[23]
CK
RAS
DDR_UDQS[0]
DDR_DQ[16]
DDR_DQ[19]
CKE
DDR2_CKE
DDR2_ODT
F7
DDR_DQ[18]
DDR_DQ[18]
DQ3
VDD3
/DDR_CS
UDQS
DDR_DQ[17]
DQ2
H3
J9
VDDQ10
LDQS
DDR_DQ[16]
DQ1
H7
J8
A9
R1002 33
DQ0
G2
CK
L8
DDR_LDQS[0]
R2
BA0
CS
/DDR_WE
P7
DDR_BA[0]
K9
/DDR_CS
M2
AR1005
G8
SDDR_DQ[6]
ODT
DDR2_ODT
P2
A9
DDR_A[10]
SDDR_DQ[4]
33
N8
DDR_A[6]
SDDR_DQ[9]
SDDR_DQ[1]
DDR_DQ[3]
1V8
SDDR_DQ[14]
M3
DDR_A[5]
DDR_A[8]
DDR_DQ[1]
CK
CKE
J2
A0
DDR_DQ[0]
DQ1
H7
CK
DDR2_CKE
VREF
DQ0
G2
DDR_DQ[31-16]
A1
DDR_A[12-0]
G8
DDR_A[12-0]
DDR_A[1]
M8
R1006
100
J2
A0
DDR_DQ[15-0]
VREF
DDR_A[0]
DDR_A[12-0]
IC1000
EP3C55F484C6N
SDDR_DQ[31-16]
K9
VCCINT[12]
N9
VCCINT[13]
P9
VCCINT[14]
P10
VCCINT[15]
1V8
C1069
0.1uF
16V
C1067
100pF
50V
C1071
10uF
16V
AB21
VCCIO4[0]
VCCIO4[1]
W12
VCCIO4[2]
W16
2V5
P13
VCCINT[16]
P14
VCCINT[17]
F12
GND[17]
GND[59]
AB1
N14
VCCINT[18]
H12
GND[18]
GND[60]
N3
H13
GND[19]
GND[61]
U3
J15
GND[20]
GND[62]
W3
K16
GND[21]
GND[63]
D3
L15
GND[22]
GND[64]
F3
N15
GND[23]
GND[65]
K3
R13
GND[24]
R11
GND[25]
R9
GND[26]
J16
VCCINT[19]
K15
VCCINT[20]
L16
VCCINT[21]
M15
VCCINT[22]
R12
VCCINT[23]
R10
VCCINT[24]
R8
VCCINT[25]
H9
VCCINT[26]
G12
VCCINT[27]
J8
VCCINT[28]
W18
VCCIO4[3]
VCCIO5[0]
P18
VCCIO5[1]
V19
VCCIO5[2]
Y19
VCCIO6[0]
E19
VCCIO6[1]
G19
VCCIO6[2]
L19
VCCIO7[0]
A21
VCCIO7[1]
D12
VCCIO7[2]
D14
VCCIO7[3]
D16
P8
GND[27]
H14
GND[28]
H10
GND[29]
H8
GND[30]
N8
GND[31]
M8
VCCINT[29]
T7
VCCINT[30]
T9
VCCINT[31]
T13
VCCINT[32]
VCCIO8[0]
A2
R7
GND[32]
P15
VCCINT[33]
VCCIO8[1]
D5
T8
GND[33]
H15
VCCINT[34]
VCCIO8[2]
D9
T12
GND[34]
H11
VCCINT[35]
VCCIO8[3]
D11
P16
GND[35]
K8
VCCINT[36]
L8
GND[36]
L7
VCCINT[37]
M7
GND[37]
A1
GND[38]
C5
GND[39]
C9
GND[40]
C11
GND[41]
DDR_VTT
1V8
1V8
C1001
10uF
16V
C1002
0.1uF
16V
C1003
0.1uF
16V
C1005
0.1uF
16V
C1007
0.1uF
16V
C1010
0.1uF
16V
C1008
0.1uF
16V
C1012
0.1uF
16V
C1013
0.1uF
16V
C1014
0.1uF
16V
C1015
0.1uF
16V
C1016
0.1uF
16V
C1017
0.1uF
16V
C1018
0.1uF
16V
C1020
0.1uF
16V
C1021
0.1uF
16V
C1022
0.1uF
16V
C1023
0.1uF
16V
C1024
0.1uF
16V
1V2
C1025
0.1uF
16V
C1026
0.1uF
16V
C1029
0.1uF
16V
C1032
0.1uF
16V
C1033
0.1uF
16V
C1034
0.1uF
16V
C1035
0.1uF
16V
C1036
0.1uF
16V
C1037
0.1uF
16V
C1038
0.1uF
16V
C1039
0.1uF
16V
C1040
0.1uF
16V
C1041
0.1uF
16V
C1043
0.1uF
16V
C1044
0.1uF
16V
DDR2_ODT
/DDR_CS
DDR_A[0]
DDR_A[2]
DDR_A[2]
56
AR1014
DDR_A[4]
DDR_A[6]
DDR_A[8]
DDR_A[8]
DDR_A[11]
DDR_VREF1
56
AR1010
C1011
470pF
50V
C1027
0.1uF
16V
IC1000
EP3C55F484C6N
C1030
470pF
50V
/DDR_CAS
/DDR_CAS
/DDR_RAS
/DDR_RAS
SDDR_DQ[15-0]
CLK13
LVDS_STABLE_1V8
V6
B3_IO[0]
DDR_LDM[1]
V5
B3_IO[1]
L/R_SYNC_1V8
U7
B3_IO[2]
3D_DIMMING_1V8
U8
B3_IO[3]
Y4
B3_IO[4]
Y3
B3_IO[5]
Y6
B3_IO[6]
AB12
CLK12
SDDR_DQ[14]
AA13
B4_IO[0]
SDDR_DQ[9]
AB13
B4_IO[1]
SDDR_DQ[8]
AA14
B4_IO[2]
SDDR_DQ[15]
AB14
B4_IO[3]
V12
B4_IO[4]
DDR_BA[0]
W13
B4_IO[5]
DDR2_CKE
AA3
B3_IO[7]
Y13
B4_IO[6]
DDR_BA[1]
AB3
B3_IO[8]
W6
B3_IO[9]
V7
B3_IO[10]
AA4
B3_IO[11]
AB4
B3_IO[12]
AA5
B3_IO[13]
SDDR_DQ[12]
DDR_UDQS[0]
SDDR_DQ[13]
AA15
B4_IO[7]
SDDR_DQ[10]
AB15
B4_IO[8]
SDDR_DQ[11]
U12
B4_IO[9]
/DDR_CAS
Y14
B4_IO[10]
DDR_A[11]
Y15
DDR_LDM[0]
AA16
SDDR_DQ[4]
SDDR_DQ[6]
B4_IO[12]
AB16
B4_IO[13]
DDR_LDQS[0]
V13
B4_IO[14]
DDR_A[1]
W14
B4_IO[15]
SDDR_DQ[1]
SDDR_DQ[3]
B4_IO[11]
U13
B4_IO[16]
V14
B4_IO[17]
DDR_A[9]
U14
B4_IO[18]
/DDR_RAS
U15
B4_IO[19]
V15
B4_IO[20]
W15
B4_IO[21]
T14
SDDR_DQ[7]
B4_IO[22]
SDDR_DQ[31-16]
/DDR_WE
SDDR_DQ[20]
SDDR_DQ[22]
SDDR_DQ[19]
SDDR_DQ[17]
DDR_A[10]
SDDR_DQ[21]
SDDR_DQ[18]
DDR_A[3]
SDDR_DQ[23]
SDDR_DQ[16]
AA6
AB6
B3_IO[15]
AB5
B3_IO[16]
W7
B3_IO[17]
Y7
B3_IO[18]
U9
B3_IO[19]
V8
B3_IO[20]
W8
B3_IO[21]
B3_IO[22]
SDDR_DQ[27]
AB7
B3_IO[23]
SDDR_DQ[25]
Y8
B3_IO[24]
T15
B4_IO[23]
3D_DIMMING_2_1V8
T10
B3_IO[25]
AB18
B4_IO[24]
FRAME_INFO_1V8
T11
B3_IO[26]
AA17
B4_IO[25]
V9
B3_IO[27]
DDR_A[2]
AB17
B4_IO[26]
AA18
B4_IO[27]
DDR2_ODT
AA19
B4_IO[28]
/DDR_CS
AB19
B4_IO[29]
W17
B4_IO[30]
Y17
B4_IO[31]
AA20
B4_IO[32]
AB20
B4_IO[33]
V16
B4_IO[34]
DDR2_CLK
U16
B4_IO[35]
/DDR2_CLK
U17
B4_IO[36]
DDR_A[8]
T16
B4_IO[37]
DDR_A[6]
R16
B4_IO[38]
DDR_A[5]
R14
B4_IO[39]
SDDR_DQ[0]
DDR_A[4]
SDDR_DQ[5]
FPGA_VSYNC_1V8
R15
B3_IO[28]
U10
B3_IO[29]
SDDR_DQ[30]
AA8
B3_IO[30]
SDDR_DQ[28]
AB8
B3_IO[31]
SDDR_DQ[31]
AA9
B3_IO[32]
AB9
B3_IO[33]
U11
B3_IO[34]
V11
B3_IO[35]
W10
B3_IO[36]
Y10
B3_IO[37]
DDR_UDM[0]
AA10
B3_IO[38]
DDR_A[7]
AB10
B3_IO[39]
AA11
CLK15
AB11
CLK14
DDR_UDQS[1]
SDDR_DQ[29]
DDR_A[12]
SDDR_DQ[24]
C2012
0.1uF
16V
C1074
0.1uF
16V
C2016
0.1uF
16V
C1079
0.1uF
16V
C1084
0.1uF
16V
C1089
0.1uF
16V
C1094
0.1uF
16V
C1099
0.1uF
16V
C2004
0.1uF
16V
C2009
0.1uF
16V
C2014
0.1uF
16V
C2017
0.1uF
16V
C1080
0.1uF
16V
C1085
0.1uF
16V
C1090
0.1uF
16V
C1095
0.1uF
16V
C2000
0.1uF
16V
C2005
0.1uF
16V
C2010
0.1uF
16V
C2015
0.1uF
16V
C2018
0.1uF
16V
C1081
0.1uF
16V
C1086
0.1uF
16V
C1091
0.1uF
16V
C1096
0.1uF
16V
C2001
0.1uF
16V
C2006
0.1uF
16V
C2011
0.1uF
16V
2V5
C1073
0.1uF
16V
C1078
0.1uF
16V
C1083
0.1uF
16V
C1088
0.1uF
16V
C1093
0.1uF
16V
C2008
0.1uF
16V
C2003
0.1uF
16V
C1098
0.1uF
16V
C2013
0.1uF
16V
C1075
0.1uF
16V
DDR_A[5]
1V8
56
AR1016
DDR_A[9]
DDR_A[9]
C1076
0.1uF
16V
DDR_A[12]
DDR_A[12]
DDR_A[7]
DDR_A[7]
DDR_A[3]
DDR_A[3]
56
AR1012
56
AR1017
DDR_BA[0]
DDR_BA[0]
DDR_BA[1]
DDR_BA[1]
3D Frame Info Level Shift (3.3V to 1.8V)
DDR2_CKE
DDR2_CKE
/DDR_WE
FPGA V-SYNC Level Shift (1.8V to 3.3V)
/DDR_WE
56
AR1013
56
AR1018
R1011
56
DDR_A[10]
1V8
+3.3V
R1012
56
R1014
DDR_A[10]
R1016
10K
3.3K
R1017
22
FRAME_INFO_1V8
C
R1015
B
Q1002
2SC3052
10K
C
3D_FRAME_INFO
R1013
B
Q1001
2SC3052
10K
+3.3V
+3.3V
E
R1019
R1021
10K
1K
DDR_VTT
R1022
22
FPGA_VSYNC
C
R1020
C1045
0.1uF
16V
C1048
0.1uF
16V
C1051
0.1uF
16V
C1054
0.1uF
16V
C1056
0.1uF
16V
C1058
0.1uF
16V
C1060
0.1uF
16V
C1062
0.1uF
16V
C1064
0.1uF
16V
C1065
0.1uF
16V
B
Q1004
2SC3052
10K
E
C
FPGA_VSYNC_1V8
R1018
B
Q1003
2SC3052
10K
E
V10
SDDR_DQ[26]
DDR_LDQS[1]
C2007
0.1uF
16V
E
DDR_A[0]
SDDR_DQ[2]
C2002
0.1uF
16V
C1097
0.1uF
16V
C1092
0.1uF
16V
B3_IO[14]
AA7
DDR_UDM[1]
C1087
0.1uF
16V
DDR_A[1]
DDR_A[5]
56
AR1011
AA12
C1082
0.1uF
16V
56
AR1015
DDR_A[1]
IC1000
EP3C55F484C6N
C1077
0.1uF
16V
1V2
DDR_A[4]
DDR_A[6]
DDR_A[11]
C1009
0.1uF
16V
C1072
0.1uF
16V
/DDR_CS
DDR_A[0]
56
AR1009
DDR_VREF0
2V5
DDR2_ODT
DDR_VTT
C1046
0.1uF
16V
C1049
0.1uF
16V
C1052
0.1uF
16V
C1055
0.1uF
16V
C1057
0.1uF
16V
C1059
0.1uF
16V
C1061
0.1uF
16V
C1063
0.1uF
16V
+3.3V
R1024
1V8
R1026
10K
+3.3V
3.3K
R1030
OPT
R1027
22
1V8
R1032
OPT
10K
B4_IO[40]
B
L/R_SYNC_FRC_OUT
OPT
R1023
10K
R1028
R1031
10K
OPT
C
B
E
FPGA_D/L_CTRL
R1040
1K
B
R1029
10K
OPT
B
E
R1042
10K
1K
R1043
22
R1038
22
3D_DIMMING
R1036
Q1008
2SC3052
OPT
B
3D_DIMMING_2
R1041
Q1010
2SC3052
10K
E
C
E
3D_DIMMING_1V8
R1034
B
Q1012
2SC3052
E
C
Q1009
2SC3052
10K
B
10K
C
Q1007
2SC3052
OPT
+3.3V
C
OPT
C
Q1005
2SC3052
+3.3V
LVDS_STABLE_1V8
E
L/R_SYNC
R1037
10K
R1033
22
C
Q1006
2SC3052
10K
R1035
3.3K
L/R_SYNC_1V8
C
R1025
+3.3V
+3.3V
3D_DIMMING_2_1V8
R1039
B
Q1011
2SC3052
10K
E
E
10K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3D + 240 FRC + TCON BOARD
DDR2
2009. 11. 13
10
10
LGE Internal Use Only