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Gigabit Ethernet Controller Registers Table 388: SDMA Configuration (SDC) (Continued) Offset: 0x7241C B i ts F i el d Ty p e / In i tVa l D e s cr ip t i o n 21:8 IPGIntRx RW 0x0 Rx frame IPG between interrupts counter and enable This field provides a way to force a delay from the last ICR[RxBufferQueue] interrupt from any of the queues, to the next RxBufferQueue interrupt from any of the queues. The ICR bits still reflect the new interrupt, but this masking is reflected by potentially not propagating to the chip main interrupt cause register. This provides a way for interrupt coalescing on receive packet events. The time is calculated in multiples of 64 clock cycles. Valid values are 0 (No delay between packets to CPU, the counter is effectively disabled.), through 0x3FFF (1,048,544 clock cycles). 24:22 TxBSZ RW 0x4 Tx Burst Size Sets the maximum burst size for Tx SDMA transactions: 000 = Burst is limited to 1 64-bit words. 001 = Burst is limited to 2 64-bit words. 010 = Burst is limited to 4 64-bit words. 011 = Burst is limited to 8 64-bit words. 100 = Burst is limited to 16 64-bit words. NOTE: This field effects only data-transfers. Descriptor fetch is done always with 4LW burst size. Must not be changed (other values degrade performance). However, a larger value is optimal for DDR SDRAM performance. 31:25 Reserved RO 0x0 Read Only Table 389: IP Differentiated Services CodePoint 0 to Priority (DSCP0) Offset: 0x72420 B i ts F i el d Ty p e / In i tVa l D e s cr ip t i o n 29:0 TOS_Q[29:0] RW 0x0 The Priority queue mapping of received frames with DSCP values 0 (corresponding to TOS_Q[2:0]) through 9 (corresponding to TOS_Q[29:27]). NOTE: The initial value means that ToS does not effect queue decisions. 31:30 Reserved RO 0x0 Reserved Copyright © 2007 Marvell June 25, 2007, Preliminary Doc. No. MV-S400130-00 Rev. 0.5 Document Classification: Proprietary Page 282
