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Intel® High Definition Audioβ D27:F0 Table 180. 04h: PCICMD – PCI Command Register (Sheet 2 of 2) Size: 16 bit Default: 0000h Access PCI Configuration Bit Range Default 00 0 Power Well: Core Offset Start: 04h Offset End: 05h B:D:F 0:27:0 Access Acronym RO RSVD Description Reserved 9.3.1.4 Offset 06h: PCISTS – PCI Status Register Table 181. 06h: PCISTS – PCI Status Register Size: 16 bit Default: 0010h Access PCI Configuration Bit Range Default 15 :05 0 Offset Start: 06h Offset End: 07h B:D:F 0:27:0 Access Acronym RO RSVD 04 1 RO CAP_LIST 03 0 RO IS 0 RO RSVD 02 :00 Power Well: Core Description Reserved Capabilities List Exists: Hardwired to 1. Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. Interrupt Status: 0= This bit is 0 after the interrupt is cleared. 1= This bit is 1 when the INTx_B is asserted. Reserved 9.3.1.5 Offset 08h: RID – Revision Identification Register Table 182. 08h: RID – Revision Identification Register Size: 8 bit Default: Access PCI Configuration Bit Range Default 07 :00 Refer to bit descript ion Refer to bit description Power Well: Core Offset Start: 08h Offset End: 08h B:D:F 0:27:0 Access Acronym Description RO RID Revision ID: Indicates the device specific revision identifier. For the B-0 Stepping, this value is 01h. For the B-1 Stepping, this value is 02h. 9.3.1.6 Offset 09h: CC – Class Codes Register Table 183. 09h: CC – Class Codes Register (Sheet 1 of 2) Size: 24 bit Access PCI Configuration Bit Range Default Default: 040300h Power Well: Core B:D:F 0:27:0 Offset Start: 09h Offset End: 0Bh Access Acronym Description 23 :16 04h RO BCC Base Class Code: This register indicates that the function implements a multimedia device. 15 :08 03h RO SCC Sub Class Code: This indicates the device is an Intel® HD Audioβ audio device, in the context of a multimedia device. Intel® Atom™ Processor E6xx Series Datasheet 143
