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time has elapsed. Otherwise, the current consumption during this sleep/idle phase will be ~ 1 mA
above the specified limits of the Data Sheet. Therefore,
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If code is executed from the internal flash after wake-up, at least 16 instructions should be
executed from the internal flash before re-entering sleep/idle mode.
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If code is executed from external memory or PRAM, wait until the flash BUSY bit returns to ‘0’
before re-entering sleep/idle mode.
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If PEC transfers with automatic return to sleep/idle mode shall be triggered by the wake-up event,
use e.g. the following procedure:
use an auxiliary routine in internal flash that waits until the flash is ready after wake-up from
sleep or idle mode, e.g.
- define a semaphore bit that is set to ‘1’ before the IDLE instruction is executed. All trap and
interrupt service routines invoked after wake up from idle/sleep should clear this bit to ‘0’
- disable interrupts
- execute the IDLE instruction
- if idle or sleep mode is terminated by an interrupt request, the instructions following the IDLE
instruction will be executed (the interrupt request flags remain set)
- if idle or sleep mode was terminated by an NMI#, the trap handler will be invoked
- enable interrupts to allow prioritization of requests for interrupt or PEC service
- the instructions following the IDLE instruction should test the flash BUSY bit in register FSR
when the flash is ready, and at least 12 instructions have been executed after the interrupt system has
been enabled, and if the semaphore bit is still at ‘1’ (i.e. no interrupts/traps have occurred), disable
interrupts and return to the IDLE instruction.
SLEEP_X.H1
Sleep Mode during PLL Reconfiguration
The PLL may be reconfigured by software by modifying the settings in register PLLCON. When
PLLCON is written to, and the PLL was locked at that time, flag PLLLOCK in register SYSSTAT is
cleared to '0' to indicate that a reconfiguration of the clock system is in progress. In addition, in order
not to exceed the internal frequency limits, the clock divider K is set to 16, such that fPLL = fVCO/16. This
is indicated in bit field PLLODIV in register PLLCON, which returns the value Fh when read during this
reconfiguration phase. When the reconfiguration is complete, PLLLOCK = 1 and PLLODIV returns the
value which was written to PLLCON.
When the PLL is about to be reconfigured (i.e. an instruction which writes to PLLCON has been
executed, and no bypass mode has been selected), and sleep mode is entered (instruction IDLE is
executed) before the PLL has locked on the new frequency, then, after wake-up from sleep mode, the
device will stay in clock system emergency mode (flagged by SYSSTAT.PLLEM=1) with fPLL = fVCO/16
(even after the oscillator has locked again).
Therefore, it is recommended not to enter sleep mode before the PLL has locked (i.e. wait until bit
OSCLOCK = 1, PLLLOCK = 1 and bit field PLLODIV < 0Fh)
SLEEP_X.H3
Clock system after wake-up from Sleep Mode
There are different wake-up behaviors, depending on the PLL control setting used in register PLLCON
during entry into sleep mode, and depending on whether the RTC is running on the main oscillator.
Note that in either case, the VCO is turned off during sleep mode, and does not contribute to any
additional power consumption.
•
In bypass mode with VCO off (PLLCTRL = 00b), the device will directly continue to run on the
frequency derived from the external oscillator input after wake-up from sleep if the RTC is running
on the main oscillator.
Errata Sheet XC161CJ-16F20F/40F (ES-)AD
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Mh/Es/UK, V0.4, 2004-08-19