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XC164CM
System Units (Vol. 1 of 2)
Memory Organization
Dual-Port RAM (DPRAM)
The XC164CM provides 2 Kbytes of DPRAM (00’F600H … 00’FDFFH). Any word or byte
data in the DPRAM can be accessed via indirect or long 16-bit addressing modes, if the
selected DPP register points to data page 3. Any word data access is made on an even
byte address. The highest possible word data storage location in the DPRAM is
00’FDFEH.
For PEC data transfers, the DPRAM can be accessed independent of the contents of the
DPP registers via the PEC source and destination pointers.
The upper 256 bytes of the DPRAM (00’FD00H through 00’FDFFH) are provided for
single bit storage, and thus they are bitaddressable (see hashed block in Figure 3-4).
Note: Code cannot be executed out of the DPRAM.
An area of 3 Kbytes is dedicated to DPRAM (00’F200H … 00’FDFFH). The locations
without implemented DPRAM are reserved.
Data SRAM (DSRAM)1)
The XC164CM provides 2 Kbytes of DSRAM (00’C000H … 00’C7FFH). Any word or byte
data in the DSRAM can be accessed via indirect or long 16-bit addressing modes, if the
selected DPP register points to data page 3. Any word data access is made on an even
byte address. The highest possible word data storage location in the DSRAM is
00’C7FEH.
For PEC data transfers, the DSRAM can be accessed independent of the contents of the
DPP registers via the PEC source and destination pointers.
Note: Code cannot be executed out of the DSRAM.
An area of 20 Kbytes is dedicated to DSRAM (00’8000H … 00’CFFFH). The locations
without implemented DSRAM are reserved.
1) Depends on the respective derivative. The derivatives are listed in “About this Manual” on Page 1-2.
User’s Manual
Memory_X41, V2.1
3-9
V1.2, 2006-03